KR100863727B1 - An array substrate for In-Plane switching mode LCD and the method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to an array substrate for a large area high definition transverse electric field type liquid crystal display device using low resistance wiring and a method of manufacturing the same.

In summary, the array wiring is constructed in a three-layer structure including aluminum (Al), which is a low resistance metal, and a barrier metal layer.

In this way, a high definition high definition transverse electric field liquid crystal display device can be manufactured.

Description

An array substrate for in-plane switching mode LCD and the method for fabricating the same             

1 is a plan view schematically showing one pixel of a conventional array substrate for a transverse electric field type liquid crystal display device;

2A to 2D are sectional views taken along the line II-II ′ and III-III ′ and IV-IV ′ and V-V ′ of FIG. 1 and shown according to a conventional process sequence.

3 is a plan view schematically showing one pixel of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

4A to 4D are cross-sectional views taken along the line VI-VI ′, VIII-VIII, VIII-VIII, VIII-VIII, and according to the process sequence of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate 113: gate pad

114: gate electrode 116: common wiring

117b vertical portion of common electrode 118 gate insulating film

122: first pattern of first metal layer 124: second pattern of first metal layer                 

131: active layer 132: ohmic contact layer

134: first pattern of semiconductor layer 136: second pattern of semiconductor layer

142b: vertical portion of pixel electrode 142c: horizontal portion of pixel electrode

144: source electrode 145: data pad electrode

146: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a large-area high-definition in-plane switching mode liquid crystal display device and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and image information may be expressed by changing the polarization state of light by optical anisotropy.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have attracted the most attention due to their excellent resolution and ability to implement video.

The liquid crystal display device includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between the upper and lower substrates. And a method in which the liquid crystal is driven by an electric field applied up and down by the pixel electrode, and has excellent characteristics such as transmittance and aperture ratio.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent. Therefore, new techniques have been proposed to overcome the above disadvantages. The liquid crystal display device to be described below has an advantage of excellent viewing angle characteristics by a liquid crystal driving method using a transverse electric field.

Hereinafter, a conventional array substrate for a transverse electric field type liquid crystal display device and a manufacturing method thereof will be described with reference to the drawings.

1 is a plan view schematically illustrating a part of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the drawing, the conventional array substrate 10 for a transverse electric field type liquid crystal display device has a plurality of gate wirings 12 and common wirings 16 arranged in one direction in parallel with a predetermined interval therebetween, and intersect with the two wirings. In particular, the data line 24 defining the pixel area P is formed from the gate line 12.

A gate pad electrode 13 is formed at one end of the gate line 12, and a data pad electrode 25 is formed at one end of the data line 24.

At the intersection of the gate wiring 12 and the data wiring 24, a gate electrode 14 extending from the gate wiring 12, an active layer 20 formed on the gate electrode 14, and a source are formed. A thin film transistor T including an electrode 26 and a drain electrode 28 is configured, and the source electrode 26 is connected to the data line 24.

The pixel region P includes a pixel electrode 30 connected to the drain electrode 28, and a common electrode 17 connected in parallel with the pixel electrode 30 and connected to the common wiring 16. do.

The pixel electrode 30 includes an extension part 30a extending from the drain electrode 28, a plurality of vertical parts 30b vertically extending from the extension part 30a and spaced apart from each other by a predetermined distance, and the common wiring. The upper portion of the 16 is composed of a horizontal portion (30c) for connecting the vertical portion (30b) into one.

The common electrode 17 extends vertically from the common wiring 16 to the pixel region P, and is arranged with a plurality of vertical portions 17b intersecting with the vertical portions 30b of the pixel electrodes. It consists of the horizontal part 17a which connects the part 17b to one.

The vertical portion 17b of the common electrode 17 formed in the pixel region P is configured to be spaced apart from the data line 24 by a predetermined distance.

The gate pad electrode 13 and the data pad electrode 25 may include a transparent gate pad terminal electrode 40 and a data pad terminal electrode 42 through the gate pad contact hole 33 and the data pad contact hole 35, respectively. It is constructed in contact.                         

 In the above-described configuration, the source and drain electrodes 26 and 28 and the data line 24 are generally formed in a single layer using molybdenum (Mo) or chromium (Cr).

However, since the source-drain metal currently used as described above has a large resistance, it is unsuitable for manufacturing a large-area high definition liquid crystal panel.

Hereinafter, a manufacturing process of an array substrate according to the related art will be described with reference to FIGS. 2A to 2D.

2A through 2D are cross-sectional views taken along the line II-II ′, III-III ′, IV-IV ′, and V-V ′ of FIG. 1, according to a conventional process sequence.

As shown in FIG. 2A, a gate wiring including the gate electrode 14 may be deposited by depositing one selected from a group of conductive metals including aluminum (Al) and an aluminum alloy on the substrate 10. 12 and the gate pad electrode 13 and the common wiring 16 spaced apart in parallel with the gate wiring 12 by predetermined intervals are formed at the end of the gate wiring 12.

At the same time, a common electrode 17 including a plurality of vertical portions 17b protruding vertically from the common wiring 16 and a horizontal portion (17a of FIG. 1) connecting the plurality of vertical portions 17b into one is provided. Form.

In the above configuration, the gate electrode 14, the gate wiring 12, and the gate pad electrode 13 are generally formed of a double metal layer.

Usually, when the gate electrode 14 and the gate wiring 12 are formed of a double metal layer, aluminum (Al) is used. That is, the first layer is formed of aluminum and the second layer is formed using molybdenum (Mo) or chromium (Cr).

Next, the gate insulating layer 18 is formed of silicon nitride (SiN _x ) on the entire surface of the substrate 10 including the gate wiring 12 and the common wiring 16.

Next, an amorphous silicon (a-Si: H) and an amorphous silicon (n + a-Si: H) including impurities are deposited on the gate insulating layer 18 and simultaneously patterned by a second mask process to form the gate. The first pattern 20 is disposed in the active region A on the electrode 14, the second pattern 21 is disposed on the common wiring 16, and the third pattern 22 is disposed in the data pad region D. FIG. Form.

The second pattern 21 and the third pattern 22 are formed for the purpose of improving contact characteristics of the upper metal layer.

The pure amorphous silicon layer of the first pattern 20 patterned in the active region A is called an active layer 20a, and the impurity amorphous silicon layer is called an ohmic contact layer 20b.

As shown in FIG. 2B, one selected from chromium (Cr) or molybdenum (Mo) is formed on the entire surface of the substrate 10 on which the semiconductor layers of the first, second, and third patterns 20, 21, and 22 are formed. Depositing and patterning a third mask process to intersect the gate wiring 12 and the common wiring 16 to define a pixel region, and to protrude from the data wiring 24 and to form the ohmic contact. The source electrode 26 in contact with the layer 20b, the drain electrode 28 spaced apart from the predetermined distance, and an extension part extending in one direction from the drain electrode 28 to the pixel region (P in FIG. 1) (FIG. A pixel electrode 30 including 30a of 1, a plurality of vertical portions 30b extending vertically from the extension portion, and a horizontal portion 30c connecting the plurality of vertical portions 30b into one. do.

At the same time, the data pad electrode 25 is formed at one end of the data line 24.

As shown in FIG. 2C, a protective film 32 is formed by depositing silicon nitride (SiN _x ) on the entire surface of the substrate 10 on which the source and drain electrodes 26 and 28 are formed.

The passivation layer 32 is patterned by a fourth mask process to form a gate pad contact hole 33 exposing a portion of the gate pad electrode 13 and a data pad contact exposing a portion of the data pad electrode 25. The hole 35 is formed.

Next, as shown in FIG. 2D, one selected from the group of transparent conductive metals of indium tin oxide (ITO) is deposited on the passivation layer 32 and patterned by a fifth mask process to form the gate pad electrode ( A gate pad terminal electrode 39 in contact with 13 and a data pad terminal electrode 41 in contact with the data pad electrode 25 are formed.

According to the above-described process, a conventional array substrate for a liquid crystal display device can be manufactured.

However, the array substrate manufactured by the above-described process is not suitable for manufacturing a large area high definition liquid crystal panel because the source and drain electrodes and the data wiring are not formed of low resistance wiring such as aluminum.

Accordingly, the present invention has been made for the purpose of solving the above-described problem, and the source and drain electrodes and the data wiring are formed of a triple metal layer including aluminum which is a low resistance wiring.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object is a substrate; A plurality of gate wirings including gate pad electrodes on the substrate; A plurality of common lines spaced apart from each of the plurality of gate lines; A plurality of pixel regions defining a plurality of pixel regions intersecting the plurality of gate wirings, including a data pad electrode, a barrier metal layer, a first metal layer made of aluminum or an aluminum alloy thereon, and a first metal layer positioned above the first metal layer. A plurality of data lines formed of two metal layers; A plurality of common electrodes connected to the plurality of common wires and extending to the plurality of pixel areas; A plurality of thin film transistors formed at intersections of the plurality of gate lines and the plurality of data lines, the plurality of thin film transistors including a gate electrode, an active layer, source and drain electrodes of the barrier metal layer, and the first and second metal layers; Comprising parallel to each of the plurality of common electrodes, comprising a plurality of pixel electrodes of a double metal layer including an aluminum or aluminum alloy layer, wherein the first and second metal layer has the same shape, the first metal layer The array substrate for a transverse electric field type liquid crystal display device is characterized in that the shape surrounding the three sides of the barrier metal layer.
An island-shaped metal pattern is further formed below each horizontal portion of the plurality of pixel electrodes, and the barrier metal layer includes chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). The second metal layer is a molybdenum layer.
In addition, the source electrode and the drain electrode as the triple metal layer may include a first metal layer including one selected from chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti), and aluminum or aluminum. A second metal layer, which is an alloy layer, and a third metal layer, which is a molybdenum layer, include a molybdenum (Mo) layer of the plurality of pixel electrodes.
And a first storage capacitor portion having a portion of each of the plurality of common wirings as a first electrode and a horizontal portion of each of the plurality of pixel electrodes as a second electrode, and a transparent contact with each of the plurality of pixel electrodes. A second storage capacitor portion having an electrode pattern as a second electrode and the gate wiring as a first electrode is configured, and a transparent gate pad electrode terminal in contact with the gate pad electrode and a transparent data pad electrode in contact with the data pad electrode. The terminal is further configured.
In this case, the source electrode is configured in a "U" shape, and the drain electrode is configured to be spaced inwardly of the source electrode.
According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, comprising: forming a gate wiring and a gate pad electrode connected to the gate wiring on a substrate; Forming a common wiring spaced apart from the gate wiring; A pixel region is defined to intersect the gate wiring, and is connected to a data pad electrode, and includes a barrier metal layer, a first metal layer made of aluminum or an aluminum alloy thereon, and a second metal layer positioned above the first metal layer. Forming a wiring; Forming a common electrode extending from the common wiring to the pixel region; Forming a pixel electrode of a double metal layer spaced parallel to the common electrode and including an aluminum or aluminum alloy layer, wherein the first and second metal layers have the same shape, and the first metal layer has the barrier. The present invention provides a method for manufacturing an array substrate for a transverse electric field type liquid crystal display device, which comprises three surfaces of a metal layer.
In this case, an island-shaped metal pattern is formed below the horizontal portion of the pixel electrode, and the barrier metal layer is selected from chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). And the second metal layer is a molybdenum layer.
The plurality of pixel electrodes may include a molybdenum (Mo) layer, a first auxiliary capacitor portion including a part of the common wiring as a first electrode and a horizontal portion of the pixel electrode as a second electrode, and the pixel electrode; A second auxiliary capacitor portion having a transparent electrode pattern in contact as a second electrode and the gate wiring as a first electrode is formed.
A transparent gate pad electrode terminal in contact with the gate pad electrode and a transparent data pad electrode terminal in contact with the data pad electrode are further formed.
The present invention also provides a method comprising: defining a plurality of pixel regions and a plurality of switching regions on a substrate; A plurality of gate lines and a plurality of common lines spaced apart from each other on the substrate in parallel with each other; a gate pad electrode connected to each of the plurality of gate lines; and a plurality of gate lines extending from the plurality of common lines to the plurality of pixel regions. Forming a common electrode of; Forming a first insulating film on the substrate on which the plurality of gate wirings and the plurality of common wirings are formed; Forming a pure amorphous silicon layer, an impurity amorphous silicon layer, and a first metal layer on the first insulating film; Etching the first metal layer to form a first pattern including the plurality of switching regions and extending to one side of the plurality of pixel regions, and a second pattern in a portion of the plurality of pixel regions; Etching the amorphous silicon layer and the impurity amorphous silicon layer exposed between the first pattern and the second pattern to form an active layer and an ohmic contact layer in the plurality of switching regions; Forming a second metal layer of aluminum (Al) or an aluminum alloy on the substrate on which the first pattern and the second pattern are formed; Forming a third metal layer on the second metal layer; A plurality of data wires including a data pad electrode at one end of the upper part of the first pattern by etching the second metal layer and the third metal layer, source and drain electrodes spaced apart from the plurality of switching regions; Forming a plurality of pixel electrodes spaced in parallel with the plurality of common electrodes; Forming a third insulating film on the substrate on which the plurality of data lines, the source electrode, the drain electrode, and the plurality of pixel electrodes are formed; A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device includes forming a transparent electrode pattern in contact with the gate pad electrode, the data pad terminal, and a horizontal portion of the pixel electrode.
The first metal layer is formed of chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), or titanium (Ti), and the third metal layer is a molybdenum (Mo) layer.
The transparent electrode pattern may be formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).

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Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

An embodiment of the present invention is characterized in that the source and drain electrodes and the data wiring are formed in a multilayer structure including aluminum.

3 is a plan view schematically showing one pixel of an array substrate for a liquid crystal display according to the present invention.

As shown, the array substrate 100 for a transverse electric field type liquid crystal display device according to the present invention has a gate wiring 112 and a common wiring 116 formed to be spaced apart from each other in parallel in one direction, and intersect with the two wirings. In particular, the gate wiring 112 and the data wiring 140 defining the pixel area P are formed.

A gate pad electrode 113 is formed at one end of the gate line 112, and a data pad electrode 145 is formed at one end of the data line 140.

At the intersection of the gate line 112 and the data line 140, a gate electrode 114 extending from the gate line 112, an active layer 131 and a source formed on the gate electrode 114 are disposed. A thin film transistor T including an electrode 144 and a drain electrode 146 is configured, and the source electrode 144 is connected to the data line 140.

The pixel region P includes a pixel electrode 142 connected to the drain electrode 146, and a common electrode 117 connected in parallel with the pixel electrode 142 and connected to the common wiring 116. do.

The pixel electrode 142 may include an extension part 142a extending from the drain electrode 146, a plurality of vertical parts 142b extending vertically from the extension part 142a and spaced apart from each other by a predetermined distance, and the common wiring. It consists of a horizontal portion (142c) connecting the vertical portion (142b) into one at the top of the (116).

The common electrode 117 vertically extends from the common wiring 116 to the pixel region P, and is intersected with the vertical portion 142b of the pixel electrode, and each of the vertical portions 117b. It consists of a horizontal part 117a which connects the part 117b to one.

In addition, the storage capacitors C1 and C2 connected in parallel with the pixel region P are configured, and the first storage capacitor C1 of the storage capacitors defines the pixel region P. A part of the common wiring 116 is used as the first storage electrode, and the horizontal portion 142c of the pixel electrode positioned with the gate insulating layer (not shown) interposed on the first storage electrode is used as the second storage electrode. The second storage capacitor C2 uses the transparent electrode pattern 160, which is in contact with the horizontal portion 142c of the pixel electrode, as the first storage electrode, and has a lower gate line extending from the transparent electrode pattern 160. A part of 112 is used as the second storage electrode.

In the above-described configuration, the gate pad electrode 113 is configured to be in contact with the transparent gate pad electrode terminal 156, and the data pad electrode 145 is configured to be in contact with the transparent data pad electrode terminal 158.

In the above-described configuration, the source and drain electrodes 144 and 146, the data line 140, and the data pad electrode 145 are made of aluminum (Al) or aluminum alloy (AlNd) to lower signal resistance.

However, when the aluminum layer is in direct contact with the amorphous silicon layer, a leakage current is generated by the interdiffusion phenomenon, and the contact resistance is high when the aluminum layer is in contact with the transparent electrode patterns 156, 158, and 160.

In order to solve this problem, the data line 140 includes a barrier layer, which is a first metal layer, aluminum (Al) or an aluminum alloy layer, which is a second metal layer, and a molybdenum (Mo) layer, which is a third metal layer.

The source and drain electrodes 144 and 146 include a barrier metal layer as the first metal layer, an aluminum (Al) layer as the second metal layer, and a molybdenum (Mo) layer as the third metal layer.

Therefore, the aluminum (Al) layer can be avoided in contact with the semiconductor layer and the transparent electrode pattern 160.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 4A to 4D.

4A to 4D are cross-sectional views taken along the line VI-VI ′, VIII-VIII, VIII-VIII, VIII-VIII, and according to the process sequence of the present invention.

As shown in FIG. 4A, a double metal layer including aluminum is deposited on the substrate 100 and patterned by a first mask process to form a gate wiring 112 including a gate electrode 114 and the gate wiring 112. ) And a common portion 116 spaced apart in parallel with a predetermined interval, a plurality of vertical portions 117b protruding vertically from the common wiring 116, and a horizontal portion connecting the plurality of vertical portions 117b to one. A common electrode 117 composed of 117a of FIG. 3 is formed.

Next, the gate insulating layer is selected from a group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 including the gate wiring 112 and the common wiring 116. Form 118.

Next, amorphous silicon (a-Si: H) and amorphous silicon (n + a-Si: H) including impurities are deposited on the gate insulating layer 118 to form a first silicon layer 119a and a second. The silicon layer 119b is formed.

Successively, one selected from the group of conductive metals including chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), etc. is deposited on the second silicon layer 119b. As a result, the first metal layer 120 that is a barrier layer is formed.

Next, as shown in FIG. 4B, the first metal layer 120 is etched by a second mask process to form the first pattern 122 in the TFT region T, the data wiring, and the data pad regions D1 and D2. ) And a second island pattern 124 having an island shape in the storage area C.

Subsequently, the exposed first silicon layer 119a and the second silicon layer 119b are etched using the first pattern 122 and the second pattern 124 as an etch stop layer.

As a result, as shown in FIG. 4C, an active layer 131 and an ohmic contact layer 132 are formed in the TFT region T under the first pattern 122, and the data line and the data pad are formed. In the region D1, a first semiconductor pattern 134 extending in one direction and an island-shaped second semiconductor pattern 136 are formed below the second pattern 124.

Each of the semiconductor patterns 134 and 136 may improve the deposition characteristics of the first and second patterns 122 and 124, which are upper metal layers.

Next, as shown in FIG. 4D, aluminum (Al) is formed on the entire surface of the substrate 200 on which the first pattern 122 and the second pattern 124 are patterned. And molybdenum (Mo) are continuously deposited to form a second metal layer 137 and a third metal layer 138.

Next, as shown in FIG. 4E, the second metal layer 137 and the third metal layer 138 are patterned by a third mask process, so that the double layer is formed on the data line and the data pad regions D1 and D2. The data line 140 and the data pad electrode 145 extending therefrom are formed.

At the same time, a source electrode 144 extending a predetermined area from the data line 140 to the TFT region T and a drain electrode 146 spaced apart from the predetermined area are formed, and the pixel is formed at the drain electrode 146. An extension part (142a of FIG. 3) extending to the area P and a plurality of vertical parts 142b vertically extending from the extension part 142a and the plurality of vertical parts 142b are connected to each other to form the common wiring. A pixel electrode composed of a horizontal portion 142c formed on the upper portion of 116 is formed.

Subsequently, using the source electrode 144 and the drain electrode 146 as an etch stop layer, the first pattern 122 of the first metal layer exposed between the two electrodes 144 and 146 and the ohmic contact layer thereunder ( 132 is etched to expose the active layer 131.

In the above-described process, the source and drain electrodes 144 and 146 and the data line 140 are formed of a trivalent metal layer including a first pattern 122 which is a barrier layer, an aluminum layer, and an molybdenum (Mo) layer. The pixel electrodes 142b and c may be formed of a double metal layer of an aluminum (Al) layer and a molybdenum (Mo) layer.

Accordingly, the first feature of the present invention manufactured through the above-described process is that the ohmic contact layer 1332 is formed between the source electrode 144 and the drain electrode 146 through a first pattern 122 that is a barrier layer. Indirect contact with them.

As described above, since the aluminum (Al) layer, which is the first layer of the source and drain electrodes 144 and 146, and the ohmic contact layer 132 may be prevented from directly contacting each other, the aluminum and the aluminum layer may be ohmic. Holes may be injected by inter-diffusion occurring between the contact layers 132 to prevent an increase in the off current I _off .

Therefore, afterimage or flicker occurring in the liquid crystal panel can be prevented.

The second feature of the present invention is to configure the data line 140 and the data pad electrode 145 in a three-layer structure of a barrier metal layer / aluminum layer / molybdenum.

Since the structure mentioned above contains an aluminum layer, wiring resistance can be reduced and it is suitable for a large area high definition liquid crystal panel.

At this time, the reason why the molybdenum (Mo) layer is formed on the aluminum (Al) layer is to avoid exposure of the aluminum layer in the air during the process.

This will be described later.

As shown in FIG. 4F, the benzocyclobutene (BCB) and the acrylic resin (resin) including the benzocyclobutene (BCB) are formed on the entire surface of the substrate 100 on which the data lines 144 and 146 are formed. A protective film 148 is formed by applying one selected from the group of organic insulating materials.

The passivation layer 148 may be formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO _X ).

The gate insulating layer 118 and the passivation layer 148 on the gate pad electrode 113 are sequentially etched to expose a portion of the gate pad electrode 113 and the data pad electrode. A data pad contact hole 152 and a storage contact hole 154 exposing a part of the part 145 and a part of the pixel electrode horizontal part 142c are formed.

Successively, the gate is formed by depositing one selected from the group of transparent conductive metal materials including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 148 is formed. The gate pad electrode terminal 156 in contact with the pad electrode 113, the data pad electrode terminal 158 in contact with the data pad electrode terminal 145, and the horizontal portion 140c of the pixel electrode An island-shaped transparent electrode pattern 160 extending above the adjacent gate line 112 is formed.

In the above-described configuration, the first storage capacitor C1 having the common wiring 116 as the first electrode and the horizontal portion of the pixel electrode as the second electrode 142c, and the gate wiring 112 as the first electrode. The second storage capacitor portion C2 having the transparent electrode pattern 160 as the second electrode is configured.

In the above-described process, since the gate pad terminal electrode 156 and the data pad terminal electrode 158 are in contact with the molybdenum layer instead of the aluminum layer, the problem caused by the aluminum and the transparent electrode contacting can be prevented. have.

In detail, aluminum (Al) has a low resistance and has advantages as signal wiring, but when exposed to air, an oxide film (Al ₂ O ₃ ) is formed on the surface.

When the aluminum layer on which the oxide film is formed is in contact with the transparent electrode, a problem arises in that the substrate is not properly driven because of high contact resistance.                     

Therefore, the array substrate is manufactured in a structure in which the lower metal layer which is not easily oxidized and the transparent electrode directly contact each other.

Through the above-described process, it is possible to manufacture an array substrate for a transverse electric field type liquid crystal display device according to the present invention.

Accordingly, the array substrate for a transverse electric field type liquid crystal display device according to the present invention can form a large area high definition liquid crystal panel because the source electrode, the drain electrode, and the data wiring can be formed of a low resistance metal (aluminum layer). have.

Claims (20)

A substrate; A plurality of gate wirings including gate pad electrodes on the substrate; A plurality of common lines spaced apart from each of the plurality of gate lines; Define a plurality of pixel regions crossing the plurality of gate lines, include a data pad electrode, and select one of chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). A plurality of data lines comprising a barrier metal layer formed thereon, a first metal layer formed of aluminum or an aluminum alloy thereon, and a second metal layer formed of molybdenum on the first metal layer; A plurality of common electrodes connected to the plurality of common wires and extending to the plurality of pixel areas; And a gate electrode, an active layer, selected from chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). A plurality of thin film transistors including a source electrode and a drain electrode comprising a third metal layer formed of one, a fourth metal layer of aluminum or an aluminum alloy layer, and a fifth metal layer of molybdenum; A plurality of pixel electrodes of a dual metal layer including a sixth metal layer made of aluminum or an aluminum alloy and a seventh metal layer made of molybdenum, which are staggered in parallel with each of the plurality of common electrodes; And the first and second metal layers have the same shape, and the first metal layer has a shape surrounding three surfaces of the barrier metal layer. The method of claim 1, And an island-shaped metal pattern is further formed below each horizontal portion of the plurality of pixel electrodes. delete delete delete The method of claim 1, A first auxiliary capacitor having a portion of each of the plurality of common wirings as a first electrode and a horizontal portion of each of the plurality of pixel electrodes as a second electrode, and a transparent electrode pattern contacting each of the plurality of pixel electrodes An array substrate for a transverse electric field type liquid crystal display device comprising a second auxiliary capacitor portion having a second electrode and the gate wiring as a first electrode. The method of claim 1, And a transparent gate pad electrode terminal in contact with the gate pad electrode and a transparent data pad electrode terminal in contact with the data pad electrode.  The method of claim 1, And the source electrode is formed in a “U” shape, and the drain electrode is spaced apart from the inside of the source electrode. Forming a gate wiring, a gate electrode and a gate pad electrode connected to the gate wiring, a common wiring spaced apart from the gate wiring, and a common electrode extending from the common wiring on a substrate; A barrier metal layer defining a pixel area crossing the gate line, connected to the data pad electrode, and selected from chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti); Forming a data line formed thereon with a first metal layer made of aluminum or an aluminum alloy and a second metal layer made of molybdenum and positioned on the first metal layer; An active layer corresponding to the gate electrode, chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti) formed at intersection points of the plurality of gate lines and the plurality of data lines. Forming a source electrode and a drain electrode, each of the third metal layer comprising one selected from the N-th), a fourth metal layer of aluminum or an aluminum alloy layer, and a fifth metal layer of molybdenum; Forming a pixel electrode of a double metal layer spaced parallel to the common electrode and including a sixth metal layer made of aluminum or an aluminum alloy and a seventh metal layer made of molybdenum; Wherein the first and second metal layers have the same shape, the first metal layer surrounds three surfaces of the barrier metal layer, and the gate electrode, the active layer, the source and the drain electrode constitute a thin film transistor. An array substrate manufacturing method for a transverse electric field type liquid crystal display device. The method of claim 9, A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device having an island-shaped metal pattern formed under the horizontal portion of the pixel electrode. delete delete delete The method of claim 9, A first storage capacitor portion having a part of the common wiring as a first electrode and a horizontal portion of the pixel electrode as a second electrode, a transparent electrode pattern in contact with the pixel electrode as a second electrode, and the gate wiring as a first electrode A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device having a second auxiliary capacitor portion formed as an electrode. The method of claim 9, And a transparent gate pad electrode terminal in contact with the gate pad electrode and a transparent data pad electrode terminal in contact with the data pad electrode. Defining a plurality of pixel regions and a plurality of switching regions on the substrate; A plurality of gate lines and a plurality of common lines spaced apart from each other on the substrate in parallel with each other; a gate pad electrode connected to each of the plurality of gate lines; and a plurality of gate lines connected to each of the plurality of gate lines; Forming a plurality of common electrodes extending from the plurality of common wires to the plurality of pixel regions in the plurality of common wires; Forming a first insulating film on the substrate on which the plurality of gate wirings and the plurality of common wirings are formed; A first metal layer including a pure amorphous silicon layer, an impurity amorphous silicon layer and one selected from chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti) is formed on the first insulating layer. Making a step; Etching the first metal layer to form a first pattern including the plurality of switching regions and extending to one side of the plurality of pixel regions, and a second pattern in a portion of the plurality of pixel regions; Etching the amorphous silicon layer and the impurity amorphous silicon layer exposed between the first pattern and the second pattern to form an active layer and an ohmic contact layer in the plurality of switching regions; Forming a second metal layer of aluminum (Al) or an aluminum alloy on the substrate on which the first pattern and the second pattern are formed; Forming a third metal layer made of molybdenum on the second metal layer; A plurality of data wires including a data pad electrode at one end of the upper part of the first pattern by etching the second metal layer and the third metal layer, source and drain electrodes spaced apart from the plurality of switching regions; Forming a plurality of pixel electrodes spaced in parallel with the plurality of common electrodes; Forming a third insulating film on the substrate on which the plurality of data lines, the source electrode, the drain electrode, and the plurality of pixel electrodes are formed; Forming a transparent electrode pattern in contact with the gate pad electrode, the data pad terminal, and a horizontal portion of the pixel electrode Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a. delete delete delete The method of claim 16, And wherein the transparent electrode pattern is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).

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