KR100232178B1 - Manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of liquid crystal display device Download PDFInfo
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- KR100232178B1 KR100232178B1 KR1019960035743A KR19960035743A KR100232178B1 KR 100232178 B1 KR100232178 B1 KR 100232178B1 KR 1019960035743 A KR1019960035743 A KR 1019960035743A KR 19960035743 A KR19960035743 A KR 19960035743A KR 100232178 B1 KR100232178 B1 KR 100232178B1
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- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims 2
- 230000001681 protective effect Effects 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 13
- 239000002184 metal Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Abstract
본 발명은 액정표시장치에 관한 것으로, 특히 픽셀과 픽셀 간의 쇼트를 방지하기 위한 액정표시장치의 제조방법에 관한 것이다.The present invention relates to a liquid crystal display device, and more particularly, to a manufacturing method of a liquid crystal display device for preventing a short between the pixel.
이와 같은 본 발명의 액정표시장치의 제조방법은 기판에 게이트 전극을 구비한 복수개의 게이트 라인을 형성하고 전면에 게이트 절연막을 증착하는 단계, 상기 각 게이트 전극 상측의 게이트 절연막위에 복수개의 활성층을 형성하는 단계, 상기 활성층 양측에 소오스/드레인 전극이 형성되도록 복수개의 데이터 라인을 형성하는 단계, 상기 데이터 라인을 포함한 전면에 보호막을 형성하고 상기 각 드레인 전극 상측의 보호막을 선택적으로 제거하여 복수개의 콘택 홀을 형성하는 단계, 상기 콘택홀을 통해 드레인 전극과 연결되도록 투면전극을 증착하고 1차 화소영역을 정의하여 투명전극을 제1차 선택적 식각하는 단계, 2차 화소영역을 정의하여 투명전극을 제2차 선택적 식각하는 단계를 포함하여 이루어진 것이다.The method of manufacturing the liquid crystal display device of the present invention comprises the steps of forming a plurality of gate lines having a gate electrode on a substrate, depositing a gate insulating film on the front surface, and forming a plurality of active layers on the gate insulating film above each gate electrode. Forming a plurality of data lines so that source / drain electrodes are formed on both sides of the active layer; forming a protective film on the entire surface including the data lines and selectively removing the protective films on the drain electrodes; Forming a projection electrode so as to be connected to the drain electrode through the contact hole, and defining a first pixel region to first selectively etch the transparent electrode; defining a second pixel region to form the second transparent electrode It includes a selective etching step.
Description
본 발명은 액정표시장치에 관한 것으로, 특히 픽셀과 픽셀 간의 쇼트(short)를 방지하기 위한 액정표시장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a manufacturing method of a liquid crystal display device for preventing a short between pixels.
일반적으로 액정표시장치(TFT-LCD)는 박막트랜지스터(TFT) 및 화소전극(pixel electrode)이 배열되는 하판과, 칼라 필터층(color filter) 및 공통전극(common electrode)과 블랙 매트릭스층(black matrix)이 배열되는 상판과, 상기 상하판이 일정간격을 갖고 합착되어 그 사이에 주입되는 액정층(liquid crystal)으로 구성된다.In general, a liquid crystal display (TFT-LCD) has a bottom plate on which a thin film transistor (TFT) and a pixel electrode are arranged, a color filter layer, a common electrode, and a black matrix layer. The upper and lower plates which are arranged are composed of a liquid crystal layer which is bonded to each other with a predetermined interval and injected therebetween.
이와같은 액정표시장치 중 하판의 구조를 좀더 구체적으로 설명하면 다음과 같다.Hereinafter, the structure of the lower plate of the liquid crystal display will be described in more detail.
제1도는 일반적인 액정표시장치의 셀 어레이 레이 아웃도이다.1 is a cell array layout of a general liquid crystal display.
즉, 하판의 구성은 유리기판위에 게이트 전극(2)을 구비하여 일정 간격을 갖고 일방향으로 복수개의 게이트 라인(12)이 배열되고, 상기 게이트 라인(12)을 포함한 기판 전면에 게이트 절연막(제1도에는 도시되지 않음)이 형성되고, 상기 게이트 전극(2) 상측의 게이트 절연막위에는 반도체층(4) 및 n+반도체층(제1도에는 도시되지 않음)이 형성되고 상기 게이트 라인(12)의 수직한 방향으로 일정 간격을 갖고 복수개의 데이터 라인(13)이 배열된다. 이때 데이터 라인(13)은 소오스 전극(6a)을 구비하여 소오스 전극(6a)이 상기 n+반도체층의 일측에 연결되도록 배열된다.That is, the bottom plate includes a gate electrode 2 disposed on a glass substrate, and a plurality of gate lines 12 are arranged in one direction at a predetermined interval, and a gate insulating film (first first) is formed on the entire surface of the substrate including the gate lines 12. Not shown), a semiconductor layer 4 and an n + semiconductor layer (not shown in FIG. 1) are formed on the gate insulating layer above the gate electrode 2, and the gate line 12 A plurality of data lines 13 are arranged at regular intervals in the vertical direction. In this case, the data line 13 includes a source electrode 6a so that the source electrode 6a is connected to one side of the n + semiconductor layer.
그리고 상기 소오스 전극(6a)이 연결된 n+반도체층의 타측에는 드레인 전극(6b)이 형성되고, 상기 드레인 전극(6b)에 전기적으로 연결되어 회소영역에 회소전극(11)이 형성된다.A drain electrode 6b is formed at the other side of the n + semiconductor layer to which the source electrode 6a is connected, and is electrically connected to the drain electrode 6b to form the recovery electrode 11 in the recovery region.
따라서 각 화소에는 하나의 박막트랜지스터(TFT)와 화소전극(11)이 형성된다.Therefore, one thin film transistor TFT and the pixel electrode 11 are formed in each pixel.
그런데, 최근에는 액정표시장치가 고정세화, 고개구율화의 추세에 따라 화소(pixel)간격이 10㎛에서 3㎛까지 감소하게 되고, 데이터 라인 상측까지 화소전극이 형성된다. 결국 화소 간격이 감소하므로 인하여 서로 인접한 화소전극(pixel electrode)간의 쇼트(short)에 대한 염려가 대두되고 있다.However, in recent years, as the liquid crystal display device has become increasingly high definition and high aperture ratio, the pixel interval is reduced from 10 μm to 3 μm, and pixel electrodes are formed up to the data line. As a result, the pixel spacing decreases, causing concern about short between adjacent pixel electrodes.
이와같은 구조를 갖는 종래의 액정표시장치에서 박막트랜지스터의 제조방법을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a thin film transistor in a conventional liquid crystal display device having such a structure will be described in detail as follows.
제2도는 제1도 I-I′선상의 종래의 액정표시장치 공정단면도이다.2 is a cross-sectional view of a conventional liquid crystal display device on the line I-I 'of FIG.
제2(a)도와 같이 유리기판(1)위에 금속(Al)을 증착하고 선택적으로 제거하여 게이트 전극(2)을 구비한 게이트 라인(제2도에는 도시되지 않음, 제1도에서 12)을 형성한다.As shown in FIG. 2 (a), a metal line (Al) is deposited on the glass substrate 1 and selectively removed to form a gate line having a gate electrode 2 (not shown in FIG. 2, 12 in FIG. 1). Form.
그리고 전면에 게이트 절연막(3)을 증착하고 반도체층(비정질 실리콘)(4) 및 n+반도체층(5)을 증착하고 선택적으로 제거하여 게이트 전극(2)상측의 활성영역에만 남도록 패터닝한다.The gate insulating film 3 is deposited on the entire surface, and the semiconductor layer (amorphous silicon) 4 and the n + semiconductor layer 5 are deposited and selectively removed to pattern only the active region on the gate electrode 2.
제2(b)도와 같이 전면에 금속(Cr)을 증착하고 선택적으로 제거하여 소오스/드레인 전극(6a, 6b)을 구비한 데이터 라인(13)을 형성하고, 상기 소오스/드레인 전극(6a, 6b) 사이의 채널영역에 해당되는 n+반도체층(5)을 제거한다. 이때 소오스 전극(6a)은 데이터 라인(13)과 일체형으로 형성되고 드레인 전극(6b)은 화소영역에 형성된다.As shown in FIG. 2 (b), metal Cr is deposited on the front surface and selectively removed to form a data line 13 having source / drain electrodes 6a and 6b, and the source / drain electrodes 6a and 6b. The n + semiconductor layer 5 corresponding to the channel region between ()) is removed. At this time, the source electrode 6a is formed integrally with the data line 13 and the drain electrode 6b is formed in the pixel region.
제2(c)도와 같이 전면에 보호막(7)을 형성하고, 상기 드레인 전극(6b)상측의 보호막(7)을 선택적으로 제거하여 콘택 홀(8)을 형성한다.As shown in FIG. 2C, the protective film 7 is formed on the entire surface, and the protective film 7 on the drain electrode 6b is selectively removed to form the contact hole 8.
제2(d)도와 같이 상기 콘택 홀(8)을 통해 드레인 전극(6b)과 연결되도록 전면에 투명전극(11a)을 증착한다. 그리고 상기 투명전극(11a)위에 감광막(14)을 증착하고 노광 및 현상하여 각 화소영역을 정의한다.As illustrated in FIG. 2D, the transparent electrode 11a is deposited on the front surface of the contact hole 8 so as to be connected to the drain electrode 6b. Each pixel area is defined by depositing, exposing and developing the photosensitive film 14 on the transparent electrode 11a.
제2(e)도와 같이 상기 감광막(14)을 마스크로 이용하여 투명전극(11a)을 선택적으로 제거하여 각 화소영역에 화소전극(11)을 형성한다.As illustrated in FIG. 2E, the transparent electrode 11a is selectively removed using the photosensitive film 14 as a mask to form the pixel electrode 11 in each pixel region.
종래의 액정표시장치에 있어서는 다음과 같은 문제점이 있었다.The conventional liquid crystal display device has the following problems.
제3도는 종래 액정표시장치 제조방법에 따른 문제점을 설명하기 위한 평면도이다. 즉, 제2(d)도, 제2(e)도 공정에서 화소전극(11) 형성시, 전면에 투명전극(11a)과 감광막(14)을 차례로 증착하고 사진석판술(photolithography)에 의해 노광 및 현상공정으로 각 화소영역을 정의한 다음 투명전극(11a)을 선택적으로 제거하여 화소전극(11)을 형성한다.3 is a plan view illustrating a problem according to a conventional method of manufacturing a liquid crystal display. That is, when forming the pixel electrode 11 in the second (d) and the second (e) process, the transparent electrode 11a and the photoresist film 14 are sequentially deposited on the entire surface and exposed by photolithography. And defining each pixel area by the developing process, and then selectively removing the transparent electrode 11a to form the pixel electrode 11.
이 때 감광막(14)에 의해 노출된 부분 즉, 제거될 부분의 투명전극(11a)위에 이물질이 있을 경우에는 그 부분(제2(e)도에서 “A”)이 제거되지 않는다.At this time, if there is foreign matter on the transparent electrode 11a of the portion exposed by the photosensitive film 14, that is, the portion to be removed, the portion (“A” in FIG. 2E) is not removed.
따라서 각 화소마다 각 화소전극이 독립적으로 형성되지 않고 이웃하는 화소전극과 화소전극 간에 숏팅(shorting)되는 경우가 발생하여 불량의 원인이 된다.Accordingly, each pixel electrode is not formed independently for each pixel, and a shorting occurs between the adjacent pixel electrode and the pixel electrode, which causes a failure.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로, 화소전극 형성시 두 번의 식각 공정을 통해 이웃하는 화소전극 간의 쇼트를 방지하는데 그 목적이 있다.The present invention has been made to solve such a problem, and its object is to prevent a short between neighboring pixel electrodes through two etching processes when forming a pixel electrode.
제1도는 일반적인 액정표시장치의 레이 아웃도.1 is a layout of a general liquid crystal display device.
제2(a)~2(e)도는 제1도 I-I′선상의 종래의 액정표시장치 공정 단면도.2 (a) to 2 (e) are sectional views of a conventional liquid crystal display device on the line I-I 'of FIG.
제3도는 종래 액정표시장치의 제조방법에 따른 문제점 설명 평면도.3 is a plan view illustrating a problem according to a conventional method of manufacturing a liquid crystal display.
제4(a)~4(f)도는 제1도 I-I′선상의 본 발명의 액정표시장치 공정 단면도.4 (a) to 4 (f) are sectional views of the liquid crystal display device of the present invention on the line I-I 'of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 게이트 전극1 substrate 2 gate electrode
3 : 게이트 절연막 4, 5 : 반도체층3: gate insulating film 4, 5: semiconductor layer
6a : 소오스 전극 6b : 드레인 전극6a: source electrode 6b: drain electrode
7 : 보호막 8 : 콘택 홀7: protective film 8: contact hole
11 : 화소전극 11a : 투명전극11 pixel electrode 11a transparent electrode
14, 15 : 감광막 13 : 데이터 라인14, 15: photosensitive film 13: data line
본 발명의 액정표시장치의 제조방법은 기판에 게이트 전극을 구비한 복수개의 게이트 라인을 형성하고 전면에 게이트 절연막을 증착하는 단계, 상기 각 게이트 전극 상측의 게이트 절연막위에 복수개의 활성층을 형성하는 단계, 상기 활성층 양측에 소오스/드레인 전극이 형성되도록 복수개의 데이터 라인을 형성하는 단계, 상기 데이터 라인을 포함한 전면에 보호막을 형성하고 상기 각 드레인 전극 상측의 보호막을 선택적으로 제거하여 복수개의 콘택 홀을 형성하는 단계, 상기 콘택 홀을 통해 드레인 전극과 연결되도록 투명전극을 증착하고 1차 화소영역을 정의하여 투명전극을 제1차 선택적 식각하는 단계, 2차 화소영역을 정의하여 투명전극을 제2차 선택적 식각하는 단계를 포함하여 이루어짐에 그 특징이 있다.A method of manufacturing a liquid crystal display device according to the present invention comprises the steps of forming a plurality of gate lines having a gate electrode on a substrate and depositing a gate insulating film on the entire surface, forming a plurality of active layers on the gate insulating film on each gate electrode; Forming a plurality of data lines such that source / drain electrodes are formed on both sides of the active layer, forming a protective film on the entire surface including the data lines, and selectively removing the protective films on the drain electrodes, thereby forming a plurality of contact holes. Depositing a transparent electrode to be connected to the drain electrode through the contact hole and defining a first pixel region to first selectively etch the transparent electrode; defining a second pixel region to etch the transparent electrode secondly Its features are that it comprises a step.
상기와 같은 본 발명의 액정표시장치 박막트랜지스터의 제조방법을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a liquid crystal display device thin film transistor according to the present invention will be described in detail as follows.
제4(a)~4(f)도는 본 발명의 액정표시장치 제조 공정 단면도이다.4 (a) -4 (f) are sectional drawing of the manufacturing process of the liquid crystal display device of this invention.
먼저, 제4(a)도와 같이 유리 기판(1)위에 금속(Al)을 증착하고 선택적으로 제거하여 게이트 전극(2)을 구비한 게이트 라인을 형성하고, 상기 게이트 라인이 형성된 기판(1)전면에 게이트 절연막(3)을 증착하고, 전면에 반도체층(비정질 실리콘)(4) 및 n+반도체층(5)을 증착하고 선택적으로 제거하여 게이트 전극(2)상측에 남도록 패터링한다. 이때 상기 반도체층(4, 5)은 게이트 전극(2)상측 뿐만아니라 데이터 라인이 형성될 부분에도 남도록 패터링하여도 무방하다.First, as shown in FIG. 4 (a), metal (Al) is deposited on the glass substrate 1 and selectively removed to form a gate line including the gate electrode 2, and the front surface of the substrate 1 on which the gate line is formed. The gate insulating film 3 is deposited on the semiconductor layer, and the semiconductor layer (amorphous silicon) 4 and the n + semiconductor layer 5 are deposited on the entire surface and selectively removed to pattern the gate layer 2 to remain on the gate electrode 2. In this case, the semiconductor layers 4 and 5 may be patterned so as to remain not only on the gate electrode 2 but also in the portion where the data line is to be formed.
제4(b)도와 같이 전면에 금속(Cr)을 증착하고 선택적으로 제거하여 소오스/드레인 전극(6a, 6b)을 및 데이터 라인(13)을 형성하고, 상기 소오스 전극(6a)과 드레인 전극(6b) 사이의 채널영역에 해당하는 n+반도체층(5)을 제거한다. 이때 소오스 전극(6a)은 데이터 라인(13)과 일체형으로 형성되고 드레인 전극(6b)은 화소영역에 형성된다.As shown in FIG. 4 (b), metal (Cr) is deposited on the entire surface and selectively removed to form source / drain electrodes 6a and 6b and data lines 13, and the source electrode 6a and the drain electrode ( The n + semiconductor layer 5 corresponding to the channel region between 6b) is removed. At this time, the source electrode 6a is formed integrally with the data line 13 and the drain electrode 6b is formed in the pixel region.
제4(c)도와 같이 전면에 보호막(7)을 형성하고, 상기 드레인 전극(6b)상측의 보호막(7)을 선택적으로 제거하여 콘택 홀(8)을 형성한다.As shown in FIG. 4 (c), the protective film 7 is formed on the entire surface, and the protective film 7 on the drain electrode 6b is selectively removed to form the contact hole 8.
제4(d)도와 같이 상기 콘택 홀(8)을 통해 드레인 전극(6b)과 연결되도록 전면에 투명전극(11a)을 증착한 후, 상기 투명전극(11a)위에 제1감광막(14)을 증착하고 화소전극 패턴 마스크를 이용하여 제1감광막(14)을 노광하고 현상하여 화소영역을 정의한다.As shown in FIG. 4 (d), the transparent electrode 11a is deposited on the front surface of the contact hole 8 to be connected to the drain electrode 6b, and then the first photosensitive film 14 is deposited on the transparent electrode 11a. The pixel region is defined by exposing and developing the first photosensitive film 14 using a pixel electrode pattern mask.
제4(e)도와 같이 상기 현상된 제1감광막(14)을 마스크로 이용하여 1차 상기 투명전극(11a)을 선택적으로 식각한다. 이 때 종래와 마찬가지로 “A”부분에서 이물질에 의해 화소전극이 패터닝되지 않을 수 있다.As illustrated in FIG. 4E, the first transparent electrode 11a is selectively etched using the developed first photosensitive film 14 as a mask. At this time, as in the prior art, the pixel electrode may not be patterned by the foreign material in the portion “A”.
제4(f)도와 같이 상기 제1감광막(14)을 제거한 후, 다시 상기 투명전극(11a)위에 제2감광막(15)을 증착하고 상기와 동일한 화소전극 패턴 마스크를 이용하여 제2감광막(15)을 노광 및 현상한다. 그리고 현상된 제2감광막(15)을 마스크로 이용하여 상기 투명전극(11a)을 한번 더 선택적으로 제거하여 최종적으로 각 화소에 화소전극(11)을 형성한다.After removing the first photosensitive film 14 as shown in FIG. 4 (f), the second photosensitive film 15 is deposited on the transparent electrode 11a and the second photosensitive film 15 is deposited using the same pixel electrode pattern mask as described above. ) Is exposed and developed. Then, the transparent electrode 11a is selectively removed once more using the developed second photosensitive film 15 as a mask, thereby finally forming a pixel electrode 11 in each pixel.
이상에서 설명한 바와 같은 본 발명의 액정표시장치의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the liquid crystal display device of the present invention has the following effects.
즉, 본 발명은 전면에 투명전극을 증착하고 동일 패턴으로 2번에 걸쳐 투명전극을 식각하여 화소전극을 형성하므로 이물질에 의한 식각 불량이 일어나지 않기 때문에 각 화소전극 간의 쇼트를 방지할 수 있다.That is, the present invention forms a pixel electrode by depositing a transparent electrode on the front surface and etching the transparent electrode twice in the same pattern, thereby preventing short circuits between the pixel electrodes because etching defects caused by foreign substances do not occur.
즉, 식각 시, 이물질이 발생하더라도 동일 부분에서 2번 이물질이 발생하는 경우가 극히 드물기 때문에 화소전극 간의 쇼트를 방지할 수 있다.That is, during the etching, even if foreign matter occurs, the second foreign matter rarely occurs in the same part, so that a short between the pixel electrodes can be prevented.
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| KR1019960035743A KR100232178B1 (en) | 1996-08-27 | 1996-08-27 | Manufacturing method of liquid crystal display device |
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| KR100662778B1 (en) * | 1999-05-20 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | An LCD and a fabricating method thereof |
| KR100569272B1 (en) * | 1999-12-28 | 2006-04-10 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing fringe field switching mode lcd |
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