KR101966865B1 - Liquid Crystal Display Device and Manufacturing Method the same - Google Patents

Abstract

A liquid crystal display panel including vertical data lines, vertical scan lines, vertical common voltage lines, horizontal scan lines, and horizontal common voltage lines; And a driver for supplying a data signal and a scan signal to the vertical data lines and the vertical scan lines, wherein the liquid crystal display panel calculates the greatest common divisor for the total number of vertical scan lines and the total number of vertical common voltage lines, The sum of the divisors of the total number of vertical scan lines obtained by using the greatest common divisor and the sum of the divisors of the total number of vertical common voltage lines is calculated and the vertical scan lines and the vertical common voltage lines corresponding to the sum are calculated as line by line A first vertical interconnection group is set so that vertical data lines are spaced apart one by one and adjacent to vertical scanning interconnection lines and vertical common voltage interconnection lines, The wiring group is set differently from the first vertical wiring group, and the wiring group is set to the vertical data lines of the first and second vertical wiring groups And a pixel array in which the first and second vertical wiring groups are defined as one pixel array is repeatedly formed on the lower substrate.

Description

[0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display and a method of manufacturing the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) Usage is increasing.

Among the above-described flat panel display devices, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used. The liquid crystal display displays an image in such a manner that light incident from the backlight unit is emitted by adjusting the arrangement direction of the pixel electrode included in the liquid crystal display panel and the electric field liquid crystal layer caught by the common electrode. The liquid crystal display device is manufactured by being divided into various driving methods according to the structure of the pixel electrode and the common electrode included in the liquid crystal display panel.

On the other hand, the liquid crystal display panel has a bezel region in which no image is displayed. Narrow bezel techniques that minimize these bezel areas have been tried in various ways. However, the conventional narrow bezel technology has technical limitations on the microprocessing, and research is needed to improve it.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and it is an object of the present invention to provide a narrow bezel for minimizing a bezel area and to provide an output bump of a driving part electrically connected to wirings formed on a liquid crystal display panel, And to provide a liquid crystal display device and a method of manufacturing the same that can minimize the occurrence of output bumps.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel including vertical data lines, vertical scan lines, vertical common voltage lines, horizontal scan lines, and horizontal common voltage lines; And a driver for supplying a data signal and a scan signal to the vertical data lines and the vertical scan lines, wherein the liquid crystal display panel calculates the greatest common divisor for the total number of vertical scan lines and the total number of vertical common voltage lines, The sum of the divisors of the total number of vertical scan lines obtained by using the greatest common divisor and the sum of the divisors of the total number of vertical common voltage lines is calculated and the vertical scan lines and the vertical common voltage lines corresponding to the sum are calculated as line by line A first vertical interconnection group is set so that vertical data lines are spaced apart one by one and adjacent to vertical scanning interconnection lines and vertical common voltage interconnection lines, The wiring group is set differently from the first vertical wiring group, and the wiring group is set to the vertical data lines of the first and second vertical wiring groups And a pixel array in which the first and second vertical wiring groups are defined as one pixel array is repeatedly formed on the lower substrate.

The second vertical wiring group may have a mirror shape for the first vertical wiring group.

The polarity to be applied to the vertical data lines of the second vertical wiring group may be the same as the polarity to be applied to the vertical data lines of the first vertical wiring group.

The first and second vertical wiring groups may each include two vertical common voltage wiring arranged on one side and the other side with respect to one subpixel.

The first vertical interconnection group includes a first vertical interconnection line, a first vertical interconnection line and a second vertical interconnection line spaced apart from each other by a first vertical interconnection line, a first vertical interconnection line adjacent to the first vertical interconnection line, A second vertical common voltage wiring line spaced apart by a second subpixel connected to the second vertical data line, a second vertical common data line interposed between the first vertical data line and the second vertical data line, A fourth vertical data line adjacent to the second vertical scanning line, a fourth vertical data line connected to the second vertical scanning line, a fourth vertical data line connected to the third vertical data line, A third vertical common voltage wiring that is spaced apart from each other by subpixels, a fifth vertical data wiring that is adjacent to the third vertical common voltage wiring, and a fourth vertical ball A sixth vertical data line adjacent to the third vertical data line, a third vertical scan line spaced apart by a sixth subpixel connected to the sixth vertical data line, A seventh vertical data line, a fifth vertical common voltage line spaced apart by a seventh subpixel connected to the seventh vertical data line, and an eighth vertical data line adjacent to the fifth vertical common voltage line.

The polarities applied to the first vertical data line to the eighth vertical data line can be alternated in the order of negative polarity and positive polarity.

The second vertical wiring group includes the ninth through sixteenth vertical data lines, and the polarities applied to the ninth vertical data line through the sixteenth vertical data line may alternate in the order of negative polarity and positive polarity.

The polarity applied to the subpixel positioned in the Nth row and the polarity applied to the subpixel located in the (N + 1) th row in the liquid crystal display panel may be opposite.

One horizontal scan line and one horizontal common voltage line may be disposed between the subpixel positioned in the Nth row and the subpixel positioned in the (N + 1) th row.

One horizontal scan wiring may be connected to one vertical scan wiring, one horizontal common voltage wiring may be connected to a plurality of vertical common voltage wirings, and the vertical common voltage wirings may have a net shape.

In another aspect, the present invention provides a liquid crystal display having a liquid crystal display panel including vertical data lines, vertical scan lines, vertical common voltage lines, horizontal scan lines, and horizontal common voltage lines, Calculating a greatest common divisor for the total number of vertical common voltage wirings, calculating a sum of a divisor for the total number of vertical scan wirings obtained by using the greatest common divisor and a sum of divisors for the total number of vertical common voltage wirings; The vertical scan lines and the vertical common voltage lines are spaced apart one by one in the line by line and the vertical data lines are arranged adjacent to the vertical scan lines and the vertical common voltage lines, ; Setting a second vertical wiring group adjacent to the first vertical wiring group in a horizontal direction differently from a first vertical wiring group; Setting polarities to be applied to the vertical data lines of the first and second vertical wiring groups, respectively; And defining the first and second vertical wiring groups as one pixel array, and repeatedly forming one pixel array on the lower substrate.

The second vertical wiring group may have a mirror shape for the first vertical wiring group.

The polarity to be applied to the vertical data lines of the second vertical wiring group may be the same as the polarity to be applied to the vertical data lines of the first vertical wiring group.

The first and second vertical wiring groups may each include two vertical common voltage wiring arranged on one side and the other side with respect to one subpixel.

The first vertical interconnection group includes a first vertical interconnection line, a first vertical interconnection line and a second vertical interconnection line spaced apart from each other by a first vertical interconnection line, a first vertical interconnection line adjacent to the first vertical interconnection line, A second vertical common voltage wiring line spaced apart by a second subpixel connected to the second vertical data line, a second vertical common data line interposed between the first vertical data line and the second vertical data line, A fourth vertical data line adjacent to the second vertical scanning line, a fourth vertical data line connected to the second vertical scanning line, a fourth vertical data line connected to the third vertical data line, A third vertical common voltage wiring that is spaced apart from each other by subpixels, a fifth vertical data wiring that is adjacent to the third vertical common voltage wiring, and a fourth vertical ball A sixth vertical data line adjacent to the third vertical data line, a third vertical scan line spaced apart by a sixth subpixel connected to the sixth vertical data line, A seventh vertical data line, a fifth vertical common voltage line spaced apart by a seventh subpixel connected to the seventh vertical data line, and an eighth vertical data line adjacent to the fifth vertical common voltage line.

The polarities applied to the first vertical data line to the eighth vertical data line can be alternated in the order of negative polarity and positive polarity.

The second vertical wiring group includes the ninth through sixteenth vertical data lines, and the polarities applied to the ninth vertical data line through the sixteenth vertical data line may alternate in the order of negative polarity and positive polarity.

The polarity applied to the subpixel positioned in the Nth row and the polarity applied to the subpixel located in the (N + 1) th row in the liquid crystal display panel may be opposite.

One horizontal scan line and one horizontal common voltage line may be disposed between the subpixel positioned in the Nth row and the subpixel positioned in the (N + 1) th row.

One horizontal scan wiring may be connected to one vertical scan wiring, one horizontal common voltage wiring may be connected to a plurality of vertical common voltage wirings, and the vertical common voltage wirings may have a net shape.

The present invention realizes a Narrow bezel that minimizes a bezel area by optimizing the arrangement of wiring in consideration of an RC delay and the like, and optimally arranges output bumps of a driver electrically connected to wirings formed on a liquid crystal display panel Thereby minimizing the occurrence of unused output bumps, and a method of manufacturing the same. The present invention also provides a liquid crystal display device and a method of manufacturing the same that can improve the display quality and reliability by minimizing the polarity symmetry of the vertical data lines and minimizing the variation of the link resistance between the vertical scan lines.

1 is a schematic block diagram of a liquid crystal display according to an embodiment of the present invention;
Fig. 2 is a block diagram of a device in which a part of the block shown in Fig. 1 is modularized; Fig.
3 is an enlarged view of the COF shown in Fig.
4 is a structural view showing a vertical wiring and a horizontal wiring;
5 is a flowchart illustrating a method of calculating an optimum position of vertical interconnections according to an embodiment of the present invention.
FIGS. 6 to 10 are examples of optimal placement of vertical interconnections according to the flow of FIG. 5;
11 to 15 are diagrams illustrating exemplary structures of subpixels to which the present invention is applicable.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a block diagram of a part of the block shown in FIG. 1, And FIG. 4 is a structural view showing a vertical wiring and a horizontal wiring.

1 to 4, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel PNL, a driving unit 10, a timing controller 12, a TCON, and a host system 14, ) And the like.

The host system (14, SYSTEM) converts the digital video data of the input image into a format suitable for the display panel (PNL). The host system 14 supplies timing signals (Vsync, Hsync, DE, MCLK, etc.) together with the digital video data of the input video to the timing controller 12. [

The timing controller 12 (TCON) supplies digital video data of the input image supplied from the host system 14 to the driving unit 10. [ The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock CLK from the host system 14. The timing controller 12 generates a source timing control signal and a gate timing control signal for controlling the driver 10 using the timing signals Vsync, Hsync, DE, and CLK.

The liquid crystal display panel PNL may be implemented in any known liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode or FFS (Fringe Field Switching) mode. Further, the liquid crystal display panel PNL can be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, and the like.

The liquid crystal display panel PNL includes subpixels formed between an upper substrate and a lower substrate opposed to each other with the liquid crystal cell Clc therebetween. An alignment film for setting a pre-tilt angle of the liquid crystal is formed on the inner upper layer of the upper substrate and the lower substrate of the liquid crystal display panel PNL. A polarizing plate is attached to the outer surfaces of the upper substrate and the lower substrate of the liquid crystal display panel (PNL).

In the lower substrate of the liquid crystal display panel PNL, vertical wirings VL and horizontal wirings HL are formed. The vertical wirings VL are formed along the vertical direction (y-axis direction) of the liquid crystal display panel PNL and the horizontal wirings HL are formed along the horizontal direction (x-axis direction) of the liquid crystal display panel PNL , They are located at an intersection.

The vertical wirings VL include a vertical data line DL, a vertical scan line GL and a vertical common voltage line CL, and the horizontal lines HL include a horizontal scan line Gi, (Vcomi). The vertical data line DL, the vertical scan line GL and the vertical common voltage line CL carry the data signal, the scan signal and the common voltage in the vertical direction (y-axis direction). The horizontal scan wiring Gi transfers the scan signal transferred in the vertical direction (y-axis direction) by the vertical scan wiring GL in the horizontal direction (x-axis direction). The horizontal common voltage wiring Vcomi changes the common voltage transferred in the vertical direction (y-axis direction) by the vertical common voltage wiring CL in the horizontal direction (x-axis direction) and transmits it.

Inside the upper substrate of the liquid crystal display panel (PNL), a black matrix and a color filter are formed. The black matrix may be formed outside the upper substrate according to the structure of the liquid crystal display panel (PNL), or may be omitted when a component performing the same function exists. The color filter may be formed inside the upper substrate or inside the lower substrate depending on the structure of the liquid crystal display panel (PNL).

In the liquid crystal display panel PNL, a display area PIXEL ARRAY is defined by subpixels, and a bezel area BZ serving as a non-display area is defined. The subpixels are formed in the form of a matrix of m * n in the intersection area of the vertical data line DLi and the horizontal scan line Gi. One subpixel PIX includes a thin film transistor TFT, a liquid crystal cell Clc, a storage capacitor Cst, a pixel electrode 1 and a common electrode 2. In the thin film transistor TFT, a gate electrode is connected to the horizontal scan line Gi, a first electrode is connected to the vertical data line DLi, and a second electrode is connected to the pixel electrode 1.

The driving unit 10 (DIC) includes a data driver SIC and a scan driver GIC. The driving unit 10 is made of an integrated circuit (IC) and mounted on a flexible circuit board in the form of a chip on film (COF). An input terminal of the COF is connected to a PCB (Printed Circuit Board), and an output terminal of the COF is connected to a lower substrate of the liquid crystal display panel (PNL). In COF, an insulating layer is formed between the wirings (FIG. 3, dotted line) connected to the data driver SIC and the wirings (FIG. 3, solid line) connected to the scan driver GIC do.

The data driver SIC latches the digital video data of the input image under the control of the timing controller 12 (TCON), and converts the digital video data into data of a parallel data structure. At this time, the data driver SIC converts the digital video data into an analog gamma compensation voltage by using a digital-to-analog converter (ADC) to generate a data voltage and supplies the data voltage to the vertical data line DL Supply. The scan driver GIC sequentially supplies a scan signal (gate pulse or scan pulse) synchronized with the data voltage from the first vertical scan line to the nth vertical scan line under the control of the timing controller 12.

In the embodiment, the data driver SIC and the scan driver GIC are mounted in a COF form. However, the scan driver GIC may be formed in a thin film form by a gate in panel (GIP) process. .

However, if the driving unit 10 is formed in the COF connected to the upper end of the liquid crystal display panel PNL and the scan signal is supplied to the horizontal scan line Gi via the vertical scan line GL, the following advantages are obtained .

First, a space for forming the scan driver (GIC) is not required or a separate flexible circuit board for mounting is not required. Second, wiring routing for electrical connection between the scan driver (GIC) and the liquid crystal display panel (PNL) can be minimized and the number of wires in the bezel area BZ can be minimized. As a result, a Narrow bezel that minimizes the space (or width) occupied by the bezel area BZ of the liquid crystal display panel PNL can be realized.

In order to realize a narrow bezel in a structure in which the data driver SIC and the scan driver GIC are not formed in a separate space but are formed in the same space as in FIG. 3 or formed in the form of an integrated IC, Should be optimized.

4, the vertical wirings VL include a vertical data line DL, a vertical scan line GL, and a vertical common voltage line CL, and their arrangement is not limited to the implementation of narrow- It is a factor that has a profound effect on quality, so it can not be optimized in a vague way.

Therefore, in order to optimize the arrangement of the vertical wirings VL, it is necessary to minimize the polarity asymmetry between the vertical common wiring CL and the vertical data wiring DL and to reduce the polarity asymmetry between the vertical common wiring GL and the vertical common wiring CL RC (where R is the resistance -Resistance, C is the capacitance-capacitance) delay, and so on.

Hereinafter, a method of calculating the optimum position of the vertical interconnection and forming it on the lower substrate according to the embodiment of the present invention will be described in detail.

5 is a flowchart showing a method of calculating an optimum position of vertical wirings according to an embodiment of the present invention, and Figs. 6 to 10 are examples of optimal placement of vertical wirings according to the flow of Fig.

The total number of the vertical scan lines GL and the maximum common number of the total number of the vertical common voltage lines CL are calculated. CL) can be calculated by using a factorial decomposition or an exponent.

The sum of the divisors for the total number of the vertical scan lines GL and the sum of the divisors for the total number of the vertical common voltage lines CL are calculated using the greatest common divisor. The sum of the divisors for the total number of vertical common wiring lines CL and the sum of the divisor for the total number of vertical common wiring lines CL and the sum of the divisors for the total number of vertical common wiring lines CL .

In the embodiment of the present invention, the greatest common divisor for the vertical scan lines GL and the vertical common voltage lines CL and the divisors thereof are calculated as a method for optimizing the arrangement of the vertical lines VL. However, in the case of the vertical data lines DL, since the vertical data lines DL are wired one by one for each vertical space between the subpixels, the arrangement thereof is excluded from consideration in calculating the optimum position of the vertical wirings. In addition, in the case of the horizontal scan wiring Gi and the horizontal common voltage wiring Vcomi, one wiring is arranged for each horizontal space between the subpixels.

A total number of vertical data lines DL is defined as A, a total number of vertical scan lines GL is defined as B, and a vertical common voltage The total number of wires CL is defined as C. And K is a greatest common factor for the total number of vertical scan lines GL and the total number of vertical common voltage lines CL. The divisor for the total number of vertical scan lines GL is defined as D, and the divisor for the total number of vertical common voltage lines CL is defined as E. The total number A of the vertical data lines DL of the liquid crystal display panel having this resolution is 1920 * 3 = 5760, and the vertical (vertical) The total number (B) of the scan lines GL is 1080 * 2 = 2160. In addition, the total number C of vertical common voltage lines CL required in the liquid crystal display panel having this resolution is 3600 as an example of A (5760) -B (2160).

- formula for calculating the optimal number of vertical wires -

According to the formula for calculating the optimum number of vertical wirings, the greatest common number K for the total number of vertical scanning wirings GL and the total number of vertical common voltage wirings CL is 720, and the vertical scanning wirings GL ) Is 3, and the divisor (E) for the total number of vertical common voltage lines (CL) is 5. The sum of the divisor D for the total number of the vertical scan lines GL and the divisor E for the total number of the vertical common voltage lines CL is 8. 8, which is derived by adding the divisor D to the total number of the vertical scan lines GL and the divisor E for the total number of the vertical common voltage lines CL, It is the smallest unit that can be.

When the sum of the divisor D for the total number of the vertical scan lines GL and the sum of the divisors E for the total number of the vertical common voltage lines CL is calculated in the optimum position calculating formula of the vertical lines, The vertical scanning lines GL and the vertical common voltage lines CL are arranged on the basis of the number of the vertical scanning lines GL and the vertical common voltage lines CL.

The vertical scanning lines GL and the vertical common voltage lines CL are separated one by one in the line by line and the vertical data lines DL are arranged in the vertical scanning lines GL and the vertical common voltage lines CL, The vertical common wiring lines CL and the vertical data lines DL are formed in such a manner that the first vertical wiring groups VL1 are arranged adjacent to the vertical scanning lines GL, ), The first vertical wiring group VL1 is set (see FIG. 6). [

The first to eighth data lines DL1 to DL8 included in the vertical data lines DL of the first vertical wiring group VL1 are spaced apart one by one in the spacing space between the subpixels. The vertical scan lines GL and the vertical common voltage lines CL of the first vertical interconnection group VL1 are spaced one by one in line by line. However, since the number of the vertical common voltage lines CL is larger than the number of the vertical scan lines GL of the first vertical interconnection group VL1, two (1) and one And the vertical common voltage wiring is arranged to be adjacent. For example, the third vertical common voltage wiring CL3 and the fourth vertical common voltage wiring CL4 are disposed adjacent (or continuously) to one side and the other side with respect to the fifth subpixel PIX5.

The first vertical common wiring line CL1 is arranged in the vertical space region where the first vertical data line DL1 of the first vertical wiring group VL1 is arranged and the second vertical data line DL2 is arranged And the first vertical scanning wiring GL1 is arranged in the vertical space region. However, this is only an example, and the positions of the second to fifth vertical common wiring lines CL2 to CL5 and the second to third vertical scanning wiring lines GL2 to GL3 may be changed depending on their positions. The location may also change.

Meanwhile, the first through fifth vertical common voltage lines CL1 through CL5 are electrically connected to the first horizontal common voltage line Vcom1 through the first contact hole CCH. The first vertical scan line GL1 is electrically connected to the first horizontal scan line G1 by a second contact hole GCH. Here, the common voltage wiring including the first to fifth vertical common voltage wiring lines CL1 to CL5 and the first horizontal common voltage wiring line Vcom1 is formed by connecting the subpixels PIX1 to PIX8, But it is not limited thereto.

The first vertical wiring group VL1 and the second vertical wiring group VL2 neighboring in the horizontal direction x are set differently from the first vertical wiring group VL1 at step S140 Represents a lower substrate)

Setting the second vertical wiring group VL2 different from the first vertical wiring group VL1 means that the positions of the vertical scanning wiring and the vertical common voltage wiring are different. Specifically, the positions of the vertical scanning wiring and the vertical common voltage wiring included in the second vertical wiring group VL2 are set to have a mirror shape with respect to the vertical scanning wiring included in the first vertical wiring group and the vertical common voltage wiring. (See Fig. 8)

Since the positions of the vertical scanning wiring and the vertical common voltage wiring included in the first vertical wiring group VL1 and the second vertical wiring group VL2 are mirror-shaped, the vertical data wiring of the second vertical wiring group VL2 The ninth to sixteenth data lines DL9 to DL16 included in the data line DL are spaced apart one by one in the spacing space between the sub-pixels. The vertical scan lines GL and the vertical common voltage lines CL of the second vertical interconnection group VL2 are spaced one by one in line by line. However, since the number of the vertical common voltage lines CL is larger than the number of the vertical scanning lines GL of the second vertical wiring group VL2, two (one) and one And the vertical common voltage wiring is arranged to be adjacent. For example, when looking at the seventh vertical common voltage wiring CL7 and the eighth vertical common voltage wiring CL8, they are arranged adjacent (or continuously) to one side and the other side with reference to the eleventh subpixel PIX11.

The sixth vertical common data line CL6 is arranged in the vertical space region where the ninth vertical data line DL9 of the second vertical wiring group VL2 is arranged and the tenth vertical data line DL10 is arranged And the fourth vertical scanning line GL4 is disposed in the vertical space region. However, this is only one example, and their positions may be switched to correspond to the first vertical wiring group VL1, and the seventh to tenth vertical common voltage wirings CL7 to CL10 and the fifth to tenth vertical common voltage wiring The positions of the sixth vertical scanning lines GL5 to GL6 may also be changed.

Meanwhile, the first vertical wiring group VL1 and the second vertical wiring group VL2 set according to the above-described method are summarized below with reference to FIG.

- first vertical wiring group (VL1) -

The first vertical data line DL1 adjacent to the first vertical common voltage line CL1 and the first vertical common voltage line CL1 and the first sub pixel PIX1 connected to the first vertical data line DL1 A second vertical data line DL2 adjacent to the first vertical scanning line GL1, a second sub pixel PIX2 connected to the second vertical data line DL2, A third vertical data line DL3 adjacent to the second vertical common voltage line CL2 and a third vertical data line DL3 connected to the third vertical data line DL3, A fourth vertical data line DL4 adjacent to the second vertical scanning line GL2, and a fourth vertical data line DL4 connected to the fourth vertical data line DL4, which are spaced apart from each other with the pixel PIX3 interposed therebetween, The third vertical common voltage wiring CL3, the fifth vertical data line DL5 adjacent to the third vertical common voltage wiring CL3, and the fifth vertical data line DL5, which are spaced apart from each other by four subpixels PIX4, The fourth vertical common voltage wiring CL4 and the sixth vertical data line DL6 adjacent to each other with the fourth subpixel PIX5 interposed therebetween, A third vertical scanning line GL3 which is spaced apart by a sixth sub pixel PIX6 connected to the sixth vertical data line DL6, a seventh vertical data line GL4 which is adjacent to the third vertical scanning line GL4, A fifth vertical common voltage wiring CL5 which is spaced apart by a seventh subpixel PIX7 connected to the seventh vertical data line DL7 and a fifth vertical common voltage wiring CL5 which is adjacent to the fifth vertical common voltage wiring CL5, Vertical data wiring (DL8).

- second vertical wiring group (VL2) -

The ninth subpixel PIX9 connected to the ninth vertical data line DL9 and the ninth vertical data line DL9 adjacent to the sixth vertical common voltage line CL6, the sixth vertical common voltage line CL6, A tenth subpixel PIX10 connected to the tenth vertical data line DL10 and the tenth vertical data line DL10 adjacent to the fourth vertical scan line GL4 and the fourth vertical scan line GL4, The eleventh vertical data line DL11 and the eleventh vertical data line DL11 connected to the seventh vertical common voltage wiring CL7, the seventh vertical common voltage wiring CL7, The eighth vertical common voltage wiring CL8, the eighth vertical common voltage wiring CL8 and the twelfth vertical data wiring DL12 and the twelfth vertical data wiring DL12, which are spaced apart from each other with the pixel PIX11 interposed therebetween, The fifth vertical scanning line GL5 and the fifth vertical scanning line GL5 which are spaced apart from each other by the connected twelfth subpixel PIX12, The ninth vertical common voltage wiring CL9 and the ninth vertical common voltage wiring CL9 which are spaced apart from each other by the thirteenth subpixel PIX13 connected to the thirteenth vertical data line DL13, The sixth vertical scanning line GL6 and the sixth vertical scanning line GL6 which are spaced apart from each other with the fourteenth subpixel PIX14 connected to the vertical data line DL14, the fourteenth vertical data line DL14, The tenth vertical common voltage wiring CL10 and the tenth vertical common voltage wiring CL10 which are spaced apart with the fifteenth subpixel PIX15 connected to the fifteenth vertical data line DL15 and the fifteenth vertical data line DL15, And a sixteenth vertical data line DL16 adjacent to the sixteenth vertical data line DL16.

When the first and second vertical wiring groups VL1 and VL2 are set, the polarities to be applied to the vertical data lines DL1 to DL18 of the first and second vertical wiring groups VL1 and VL2 are respectively set The polarities to be applied to the vertical data lines DL9 to DL18 of the second vertical wiring group VL2 are applied to the vertical data lines DL1 to DL8 of the first vertical wiring group VL1 And has a polarity opposite to the polarity to be.

The first to eighth vertical data lines DL1 to DL8 of the first vertical wiring group VL1 are connected to the negative polarity and the positive polarity by negative, , (-), (+), (-), and (+). The negative polarity (-) and the positive polarity (+) of the ninth to eighteenth vertical data lines DL9 to DL18 of the second vertical wiring group VL2 are negative, positive, , (-), (+), (-), and (+).

When the vertical data lines DL1 to DL8 of the first vertical wiring group VL1 and the ninth to eighteenth vertical data lines DL9 to DL18 of the second vertical wiring group VL2 are overlapped, Are the same. However, when the first vertical wiring group VL1 and the second vertical wiring group VL2 are folded into a mirror shape, the polarity signals applied to them are opposite.

Referring to the first to sixteenth vertical data lines DL1 to DL16 located in the first horizontal scan line G1, the sub-pixels positioned in the corresponding line are negative (-) and positive (+ ), (+), (-), (+), (-), (+), (-) and (+). However, referring to the first to sixteenth vertical data lines DL1 to DL16 located in the second horizontal scan line G2, the subpixels located in the corresponding line are positive (+) and negative (-) (+), (-), (+), (-), (+), (-), (+), (-).

The first and second vertical wiring groups VL1 and VL2 to be calculated and arranged in the manner described above are defined as one pixel array PA and one pixel array PA is repeatedly formed on the lower substrate (S160)

One pixel array PA including the first and second vertical wiring groups VL1 and VL2 is repeatedly formed on the lower substrate, and an upper substrate is prepared, and the upper substrate is bonded and the liquid crystal layer is injected. A liquid crystal display panel (PNL) having the same structure is manufactured.

As described above, one horizontal scan line and one horizontal common voltage line are arranged between the horizontal space between the subpixel located in the Nth row and the (N + 1) th row. The polarity applied to the subpixel located in the (N + 1) th row is opposite to the polarity applied to the subpixel located in the (N + 1) th row. To this end, the subpixels located in the (N + 1) th row may be connected to receive data signals from the neighboring thin film transistors (TFTs) in the horizontal direction as shown, but are not limited thereto.

The vertical data lines and the vertical scan lines formed in the liquid crystal display panel PNL are formed as described above so that the output bumps BMP of the driver DIC connected thereto are also arranged in the arrangement of the wirings included in one pixel array PA As shown in Fig. For example, the output bumps BMP of the driving unit DIC may be formed of D, G, D, D, G, D, D, D, G, D, D, D, G, D, G, D, D, G, D and D. Here, D corresponds to an output bump connected to the vertical data line DL, and G corresponds to an output bump connected to the vertical scanning line GL.

When the vertical data lines and the vertical scan lines are formed as described above, the vertical common voltage line CL is connected to the main common voltage line MCL wired to the left outer side, the right outer side, or the left / right outer side of the liquid crystal display panel PNL, Lt; / RTI > The vertical common voltage wiring CL and the horizontal common voltage wiring Vcom1 to Vcom5 are formed in a net shape in order to minimize the RC delay and the like and are connected to the main common voltage wiring line MCL.

On the other hand, if the greatest common divisor of the total number A of vertical data lines DL and the total number B of vertical scan lines GL is calculated, 360 is obtained. At this time, the divisor for the total number of vertical data lines DL is 16 and the divisor for the total number of vertical scan lines GL is 6. [ The sum of the divisor 16 for the total number of the vertical data lines DL obtained using the greatest common divisor and the divisor 6 for the total number of the vertical scan lines GL is calculated to be 22.

As a result, only the total number of the vertical data lines DL and the total number of the vertical scan lines GL are related at the side of the driver DIC, so that the 22 output bumps BMP are connected to one pixel array PA. Is an output bump group corresponding to the output bump group. As described above, by disposing the vertical wirings included in the liquid crystal display panel and disposing the output bumps of the driver electrically connected to the vertical wirings, generation of unused output bumps can be minimized.

Hereinafter, the structure of a subpixel to which the present invention is applicable will be described.

11 to 15 are diagrams illustrating exemplary structures of subpixels to which the present invention is applicable.

11 shows a structure in which a pixel electrode Pxl is formed on a common electrode Vcom. 11, the common electrode Vcom is formed in a shape corresponding to the opening region, and the pixel electrode Pxl is formed in the shape of a split electrode. Here, the common electrode Vcom is formed below the vertical data line Data. The pixel electrode Pxl includes an electrode having an inequality shape (<) at the center of the opening region and an electrode having a diagonal shape whose upper and lower sides are symmetrical with respect to the electrode.

12 shows a structure in which the pixel electrode Pxl is formed on the common electrode Vcom. In the subpixel shown in FIG. 12, the common electrode Vcom and the pixel electrode Pxl are formed in the form of split electrodes. Here, the common electrode Vcom is formed below the vertical data line Data. And the pixel electrode PxI includes an electrode having a shape vertically divided in the opening region.

13 shows a structure in which the common electrode Vcom is formed on the pixel electrode Pxl. In the subpixel shown in FIG. 13, the pixel electrode Pxl is formed in a shape corresponding to the opening region, and the common electrode Vcom is formed in the shape of a split electrode. Here, the pixel electrode PxI is formed under the vertical data line Data. And the common electrode Vcom includes an electrode having a shape vertically divided in the opening region.

14 shows a structure in which a pixel electrode Pxl is formed on a common electrode Vcom. In the subpixel shown in FIG. 14, the common electrode Vcom is formed as a front electrode and the pixel electrode Pxl is formed as a split electrode. Here, the common electrode Vcom is formed between the upper portion of the vertical data line Data and the pixel electrode Pxl. And the pixel electrode PxI includes an electrode having a shape vertically divided in the opening region.

15 shows a structure in which the common electrode Vcom is formed on the pixel electrode Pxl. In the subpixel shown in FIG. 15, the pixel electrode Pxl is formed in a shape corresponding to the opening region, and the common electrode Vcom is formed in the shape of a split electrode. The common electrode Vcom includes an electrode having a shape divided vertically in the opening region, and having an inequality (<) shape.

In the above description, only a few examples of subpixels to which the present invention is applicable have been described. However, the present invention is applicable to a liquid crystal display panel that operates in other modes as well as the above-described structure. Note that I-Vcom shown in FIGS. 13 to 15 is the same as the common electrode Vcom, but differs from FIG. 11 and FIG. 12 in that it has a structure of overlapping with the data line Data.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a narrow bezel which minimizes the bezel area by optimizing the arrangement of wirings in consideration of an RC delay and the like and to optimize the output bumps of the driver electrically connected to the wirings formed on the liquid crystal display panel And the problem of occurrence of unused output bumps can be minimized, and a method of manufacturing the same. The present invention also provides a liquid crystal display device and a method of manufacturing the same that can improve the display quality and reliability by minimizing the polarity symmetry of the vertical data lines and minimizing the variation of the link resistance between the vertical scan lines.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

PNL: liquid crystal display panel 10, DIC:
12, TCON: timing controller 14, SYSTEM: host system
SIC: data driver GIC: scan driver
VL: vertical wiring lines HL: horizontal wiring lines
DL: vertical data line GL: vertical scan line
CL: vertical common voltage wiring VL1: first vertical wiring group
VL2: second vertical wiring group PA: one pixel array
BMP: Output bumps

Claims (20)

A liquid crystal display panel including vertical data wirings, vertical scan wirings, vertical common voltage wirings, horizontal scan wirings, and horizontal common voltage wirings; And
And a driver for supplying a data signal and a scan signal to the vertical data lines and the vertical scan lines,
The liquid crystal display panel
Wherein the maximum common number is calculated based on the total number of vertical scan lines and the total number of vertical common voltage lines and the sum of the sum of the total number of vertical scan lines and the total number of vertical common voltage lines The sum of the divisors is calculated,
The vertical scan lines and the vertical common voltage lines corresponding to the sum are spaced apart one by one by a line by line and the vertical data lines are arranged adjacent to the vertical scan lines and the vertical common voltage lines, The first vertical wiring group is set so that the first vertical wiring group,
The second vertical wiring group neighboring in the horizontal direction with the first vertical wiring group is set to be different from the first vertical wiring group,
Setting polarities to be applied to vertical data lines of the first and second vertical wiring groups, respectively,
Wherein one pixel array defined by defining the first and second vertical wiring groups as one pixel array is formed repeatedly on the lower substrate. The method according to claim 1,
The second vertical wiring group
And the second vertical wiring group has a mirror shape with respect to the first vertical wiring group. The method according to claim 1,
The polarity to be applied to the vertical data lines of the second vertical wiring group
And the second vertical wiring group has a polarity same as a polarity to be applied to the vertical data lines of the first vertical wiring group. The method according to claim 1,
The first and second vertical wiring groups
Each of which includes two vertical common voltage wirings arranged on one side and the other side with respect to one subpixel. The method according to claim 1,
The first vertical wiring group
A first vertical common voltage wiring, a first vertical data wiring adjacent to the first vertical common voltage wiring,
A first vertical scan line spaced apart by a first sub-pixel connected to the first vertical data line, a second vertical data line adjacent to the first vertical scan line,
A second vertical common voltage wiring line spaced apart by a second sub pixel connected to the second vertical data line, a third vertical data line wiring line adjacent to the second vertical common voltage wiring line,
A second vertical scan line spaced apart by a third sub-pixel connected to the third vertical data line, a fourth vertical data line adjacent to the second vertical scan line,
A third vertical common voltage wiring spaced apart by a fourth subpixel connected to the fourth vertical data wiring, a fifth vertical data wiring adjacent to the third vertical common voltage wiring,
A fourth vertical common voltage wiring line spaced apart by a fifth subpixel connected to the fifth vertical data line, a sixth vertical data wiring line adjacent to the fourth vertical common voltage wiring line,
A third vertical scan line spaced apart by a sixth sub-pixel connected to the sixth vertical data line, a seventh vertical data line adjacent to the third vertical scan line,
A fifth vertical common voltage wiring spaced apart by a seventh subpixel connected to the seventh vertical data wiring, and an eighth vertical data wiring adjacent to the fifth vertical common voltage wiring. 6. The method of claim 5,
Wherein polarities applied to the first vertical data line to the eighth vertical data line are alternated in the order of positive polarity and negative polarity. 6. The method of claim 5,
The second vertical wiring group
And ninth to sixteenth vertical data lines,
Wherein the polarities applied to the ninth to sixteenth vertical data lines alternate in the order of positive polarity and negative polarity. The method according to claim 1,
The liquid crystal display panel
And the polarity applied to the subpixel positioned in the (N + 1) th row is opposite to the polarity applied to the subpixel located in the (N + 1) th row. 9. The method of claim 8,
And one horizontal scan line and one horizontal common voltage line are disposed between the subpixel positioned in the Nth row and the subpixel positioned in the (N + 1) th row. 10. The method of claim 9,
The one horizontal scan line is connected to one vertical scan line,
Wherein the one horizontal common voltage wiring is connected to a plurality of vertical common voltage wiring,
Wherein the vertical common voltage wirings have a net shape. delete delete delete delete delete delete delete delete delete delete

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