KR20090041787A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to make the amount of electric charge, charged in pixels between horizontal lines when realizing an image of specific color, identically maintained. In a liquid crystal panel(100), sub pixels which form one zig-zag column are connected to the same data line and are driven. A gate driver(110) operates a gate line of the liquid crystal panel. A data driver(120) operates a data line of the liquid crystal panel. A timing control unit(130) controls the gate driver and data driver. A voltage generation unit(200) produces the driving voltage.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device. More specifically, in a liquid crystal display device in which subpixels are connected in a zigzag form and driven based on one data line, a subpixel having the same color as one of the R, G, and B subpixels formed in pixel units. The pixels are connected to and driven by the same data line, so that the luminance of the pixels between horizontal lines is uniformly maintained when an image of a specific color is implemented.

In general, the liquid crystal display device displays an image by adjusting the light transmittance of each liquid crystal cell according to the pixel voltage. Of course, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, a driving circuit such as a gate driver and a data driver to drive the liquid crystal panel, and a timing controller for controlling two drivers. do.

Above all, various driving methods have been known in connection with the improvement of the image quality of the liquid crystal display device having the above-described configuration. Among them, in order to drive the liquid crystal cells on the liquid crystal panel, frame inversion and line inversion driving methods such as inversion and dot inversion systems have been used. In this case, the inversion method means that each sub-pixel of red (R), green (G), and blue (B) is divided into a plurality of horizontal lines formed of pixel units of R, G, and B, and R, G, and B are pixels. Whenever a frame formed by a plurality of horizontal lines as a unit is changed, a method of driving by inverting the polarity of the pixel voltage supplied to the liquid crystal cells on the liquid crystal panel is described.

Recently, however, it has been extended to change the structure of LCD panels in relation to improvement of image quality.

1 is a view showing the structure of a liquid crystal display device according to the prior art as one example thereof.

As shown in FIG. 1, a conventional liquid crystal display includes sub-pixels 13 having different colors of R, G, and B on both left and right sides based on one data line. A liquid crystal panel 12 connected and driving liquid crystal cells of the same polarity in a zig-zag form, and a gate driver 14 for driving gate lines GL1 to GLn of the liquid crystal panel 12. ), A data driver 16 for driving the data lines DL1 to DLm + 1 of the liquid crystal panel 12, and a timing controller 18 for controlling the gate driver 14 and the data driver 16. It is configured to include).

Of course, the liquid crystal display device is driven in a horizontal 1-dot inversion method and a vertical 1-dot inversion method. More specifically, when the gate voltage corresponding to the first horizontal line is supplied from the gate driver 14 through the first gate line GL1, the data driver 16 receives data of R, G, and B inputted data. The pixel voltage corresponding to the first horizontal line of the first gate line GL1 is supplied to the data lines DL1 to DLm + 1 by converting to an analog pixel voltage. In this case, the data driver 16 converts the R, G, and B data into pixel voltages by using gamma voltages supplied from a gamma voltage circuit (not shown) to supply pixel voltages in a horizontal 1-dot inversion manner.

Subsequently, when the gate voltage corresponding to the second horizontal line is supplied from the gate driver 14 through the second gate line GL2, the data driver 16 may match the data polarity of the first horizontal line with the line inversion scheme. The pixel voltages corresponding to the second horizontal lines opposite to each other are supplied to the data lines DL1 to DLm + 1.

As a result, the liquid crystal display alternately displays different data polarities of positive (+) and negative (-) on the odd-numbered data line and the even-numbered data line per unit frame in a horizontal 1-dot inversion manner. The line inversion and the frame inversion are given to implement an image in a horizontal 1 dot and a vertical 1 dot manner.

FIG. 2 shows the subpixels of R and G that are turned on when a yellow image is implemented on the liquid crystal panel 12 of FIG. 1 arranged in RG, B, and R pixel units. A waveform diagram showing a potential state.

As shown in FIG. 2, when the yellow image is implemented on the liquid crystal panel 12 of FIG. 1, the (m-2) th data line DLm-2 that manages R, G, and B pixels in the first horizontal line, respectively ), The (m-1) th data line DLm-1 to turn on the G subpixels of the (m-1) th data line DLm-1 and the m th data line DLm. A high level voltage is applied to the (m-2) th data line DLm-2 to drive the subpixels of R constituting the pixel adjacent to the G subpixels. A low level voltage is applied to the subpixels of B, which are applied to the subpixels of G adjacent to the subpixels of G, to drive the yellow first pixel through the mth data line DLm.

In addition, the voltage applied to the first pixel is the (m-1) th data line DLm-1 and the mth data line DLm that manage R, G, and B pixels in the second horizontal line. And a low level voltage applied to the m th data line DLm is converted to a high level to apply the G sub pixels of the (m + 1) th data line, and is applied to the G sub pixels. The high level voltage applied to the (m-1) th data line DLm-1 is maintained and applied to the subpixels of R constituting the pixel adjacent to the pixel. The pixel is adjacent to the G subpixels. The second pixel is driven by applying a low-level voltage applied to the (m + 1) th data line to the subpixels of B configuring.

In other words, it is continuously high in the subpixels of G of the odd horizontal line and connected to the (m-1) th data line DLm-1, and the subpixels of R located in the even-numbered horizontal line. The voltage applied at the level reduces the line resistance of the corresponding data line, or reduces the disturbance factors related to parasitic capacitance, such as having to charge the parasitic capacitor of the data line first, thereby reducing the pixel voltage sufficient for the R and G subpixels. Is applied. On the other hand, the G subpixels of the even-th horizontal line connected to the mth data line DLm are affected by the line resistance and parasitic capacitance of the data line due to the B subpixels turned off. The amount of charge charged in the G subpixels arranged in the odd horizontal lines during the given one horizontal period becomes small.

As a result, the amount of charges charged to the R and G sub-pixels arranged in each horizontal line to form part of the pixel is different from each other, so that the luminance difference of the color between the horizontal lines is generated when an image of a specific color is realized. (line dim) phenomenon is causing.

Of course, this phenomenon is not only a yellow image as described above, but also a cyan image by turning on the G and B subpixels of the R, G, and B subpixels in pixel units, or R It also occurs when turning on and turning on the subpixels of B to implement a purple image, which is a cause of deterioration of image quality.

The present invention has been made to solve the above problems, and its purpose is to allow subpixels of the odd and even horizontal lines to form different arrangements, but one of the subpixels of R, G, and B pixels The present invention provides a liquid crystal display device connected to the same data line to maintain the same amount of charge charged in pixels between horizontal lines when an image of a specific color is implemented.

The liquid crystal display according to the present invention for achieving the above object is a subpixel of R (red), green (G), blue (B) in the unit pixel defined by the intersection of a plurality of gate lines and data lines When the pixels are formed in a plurality of horizontal lines, the same color subpixels and two zig-zag-shaped columns are arranged in the vertical and eventh horizontal lines to form the same color, respectively. A liquid crystal panel including subpixels, wherein subpixels of the same color of one of the subpixels of the same color forming two columns in the zigzag pattern are connected to the same data line; A data driver for applying a pixel voltage to a plurality of data lines formed in the liquid crystal panel; A gate driver for applying a control signal to a gate line of the liquid crystal panel; And a timing controller configured to control the gate and the data driver by receiving data and vertical / horizontal synchronization signals from the outside and generating data realignment and control signals.

As a result of the above configuration, in the liquid crystal display according to the present invention, when the image of a specific color is implemented on the screen, the luminance of the pixel which is formed between the horizontal lines and driven is maintained to be uniform, thereby improving the overall image quality.

Hereinafter, the configuration will be described in more detail with reference to the accompanying drawings.

3 is a view showing a driving unit of the liquid crystal display according to the present invention, and FIG. 4 is a view showing a pixel structure formed in the liquid crystal panel of FIG.

Referring to FIGS. 3 and 4, the liquid crystal display according to the present invention includes R in dot units on a unit pixel defined by crossing a plurality of gate lines GL1 to GLn and data lines DL1 to DLm + 1. When the G and B subpixels are formed in a plurality of horizontal lines, two zig-zag columns are formed with the same color subpixels arranged in each of the odd and even horizontal lines and aligned in the vertical line direction. The liquid crystal panel includes subpixels having the same color, and subpixels forming the zig-zag column of one of the subpixels having the same color are connected to the same data line to drive each other. 100; A gate driver 110 for driving the gate lines GL1 to GLn of the liquid crystal panel 100 and a data driver 120 for driving the data lines DL1 to DLm + 1 of the liquid crystal panel 100. And a timing controller 130 for controlling the gate driver 110 and the data driver 120, a power supply voltage generator 200 for generating a driving voltage, and light to the liquid crystal panel 100. A backlight 220, a lamp driver 210 generating a driving voltage for driving the backlight 220, and controlling the backlight 220 according to a control signal from the timing controller 130, and the power supply voltage. The generator 200 includes a reference voltage generator 230 that receives the power supply voltage Vdd from the generator 200 to generate a reference voltage Vref and provide the reference voltage Vref to the data driver 120.

First, the liquid crystal panel 100 includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm + 1 that are insulated from and cross each other on the gate lines GL1 to GLn. The liquid crystal cells are arranged in a matrix form for each unit pixel defined by crossing the lines GL1 to GLn and the data lines DL1 to DLm + 1. Each liquid crystal cell includes a thin film transistor 101 connected to any one of the n gate lines GL1 to GLn and one of the (m + 1) data lines DL1 to DLm + 1.

First of all, as the thin film transistor 101 is connected in a zigzag form with neighboring unit pixels along the data lines DL1 to DLm + 1, the liquid crystal cells included in the same column of the same vertical line are horizontal. Each line is alternately connected to different adjacent data lines DL1 to DLm + 1, and thus liquid crystal cells are implemented in a zigzag form based on the respective data lines DL1 to DLm + 1.

More specifically, in FIG. 4, the liquid crystal panel 100 includes three identical column lines in which R, G, and B subpixels are pixels, that is, one vertical line among three identical vertical lines has the same color. The two vertical lines are arranged in liquid crystal cells capable of expressing the same color in a zigzag form. For example, liquid crystal cells for realizing the colors of R and G are alternately arranged in the first column line, and liquid crystal cells for realizing the colors of G and R are alternately arranged in the second column line, and the third column. Liquid crystal cells that implement the color of B are arranged in the line.

At this time, the liquid crystal cells of the odd horizontal lines which are connected to the odd gate lines GL1, GL3, ..., GLn-1 and implement the pixels in which the subpixels are arranged in the order of R, G, and B are based on themselves. Connected to the first to mth data lines DL1 to DLm positioned in the -X axis direction, respectively, while connected to the even-numbered gate lines GL2, GL4, ..., GLn, in order of G, R, and B. The liquid crystal cells of the even-th horizontal line implementing the pixel in which the sub-pixels are arranged are connected to the second to m + 1 th data lines DL2 to DLm + 1 positioned in the + X-axis direction based on their own. Each is connected.

As a result, odd-numbered data lines DL1, DL3, ..., DLm and even-numbered data lines DL2, DL4, ..., DLm + 1 are assigned to the odd-numbered and even-numbered liquid crystal cells for each horizontal line. Among the subpixels alternately connected and arranged in the order of R, G, B and G, R, B in the odd and even horizontal lines, the G subpixels are the same data lines DL2, DL5,... , DLm-1).

On the other hand, the backlight 220 is composed of a plurality of lamps such as Cold Cathode Fluorescent Lamp (CCFL) or External Electrode Fluorescent Lamp (EEFL), which are turned on by AC high voltage, and the front (or upper) light provided from the lamps. It is sent to the liquid crystal panel 100 located in.

The lamp driver 210 receives a DC voltage of about 24 V from the power supply voltage generator 200, converts the DC voltage into a DC AC waveform, and converts the AC waveform into an AC AC voltage having a high voltage and applies it to the backlight 220.

The power supply voltage generator 200 receives an AC voltage from the outside and generates a DC voltage of about 12V, and a DC-DC converter generating various types of DC voltages using the DC voltage. DC convertor). Here, the DC-DC converter is formed by being integrated in a pulse width modulation integrated circuit (PWM IC), and is coupled to the peripheral circuit surrounding the PWM IC to form a common voltage (Vcom), a power supply voltage (Vdd), and a gate on / off. Off voltages Vgl and Vgh are generated.

The reference voltage generation unit 230 divides the power supply voltage Vdd provided from the power supply voltage generation unit 200 to generate gamma reference voltages Vref of various levels, and again converts the gamma reference voltage Vref into a data driver. A gamma gradation voltage circuit (not shown). In this case, a plurality of gamma reference voltages Vref having various levels are generated through a plurality of resistors connected in series.

The timing controller 130 receives a vertical / horizontal synchronization signal (Vsync, Hsync) from the interface 10 coupled with an external system (or device) to control the gate driver 110 and the data driver ( And a control signal generation unit for generating a data control signal of 120, and a data rearranging unit for rearranging the R, G, and B data from the interface 10 and supplying the data control unit 120 to the data driver 120 again. At this time, the rearranged R, G, B data is set to correspond to the gray level information of the R, G, B data by the logic voltage Vlog generated and sent from the power supply voltage generation unit 200.

The timing controller 130 first generates a gate shift clock (GSC), a gate output enable (GOE), a gate start pulse (GSP), and the like as a gate control signal. Is a signal that determines the time when the gate of the thin film transistor is turned on / off, GOE is a signal for controlling the output of the gate driver 110, GSP is the first drive of the screen of one vertical synchronization signal This signal indicates the line.

In addition, the timing controller 130 is a data control signal for controlling the data driver 120 as a source sampling clock (SSC), a source output enable (SOE), and a source start pulse (Source Start Pulse: SSP), Polarity Reverse (POL), Data Polarity (REV), and odd / even pixel data (Odd / Even Data) signals.

Here, the SSC is used as a sampling clock for latching data in the data driver 120 and determines a driving frequency of the data drive IC. The SOE causes the data latched by the SSC to be transferred to the liquid crystal panel 100. The SSP is a signal indicating the start of latching or sampling of data during one horizontal synchronization period. POL is a signal indicating polarity to drive the liquid crystal positively and negatively for inversion driving of the liquid crystal. REV is a signal for selecting the polarity of the data to be transmitted, and odd / even pixel data is a signal representing odd data of odd pixels and even data of even pixels.

The gate driver 110 receives the gate voltages Vgl and Vgh generated by the power supply voltage generation unit 200 and sequentially applies the gate voltages Vgl to the gate lines GL1 to GLn according to the control signal of the timing controller 130. , Vgh is supplied to drive the thin film transistors 101 connected to the corresponding gate lines GL1 to GLn.

The data driver 120 converts the input R, G, and B data into pixel voltages, which are analog signals, and converts the pixel voltages of one horizontal line into one horizontal line during a horizontal period in which the gate voltages are supplied to the respective gate lines GL1 through GLn. Supply to data lines DL1 to DLm + 1. In this case, the data driver 120 converts the R, G, and B data into pixel voltages by using gamma voltages supplied from a gamma voltage gray scale circuit (not shown) to supply pixel voltages in a horizontal 1-dot inversion manner per horizontal line. In addition, the entire screen is given a line inversion and a frame inversion to implement an image in a horizontal 1 dot and a vertical 1 dot method.

More specifically, the data driver 120 includes a data register into which data RGB is input from the timing controller 130, a shift register for generating a sampling clock, the shift register, and (m + 1) pieces. The gamma gradation voltage supplied to the digital to analog converter (DAC) by dividing the first and second latches and the gamma reference voltages Vref connected between the data lines DL1 to DLm + 1. Circuitry, digital / analog converter and output.

Here, the data register temporarily stores the data RGB from the timing controller 130 and supplies the stored data RGB to the first latch.

The shift register shifts the source start pulse SSP from the timing controller 130 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register shifts the source start pulse SSP to transfer the carry signal CAR to the next shift register.

The first latch samples the digital video data RGB from the data register in response to a sampling signal sequentially input from the shift register, and latches the digital video data RGB by one line.

After latching the digital data RGB input from the first latch, the second latch enables the data to be simultaneously output in response to the latched digital video data RGB in response to the SOE signal from the timing controller 130.

The gamma gradation voltage circuit divides the gamma reference voltages Vref of various levels generated by the reference voltage generation unit 230 to generate gamma gradation voltages corresponding to each gradation such as 64 gradations or 256 gradations.

The DAC selects and outputs the gray level voltage of the corresponding level supplied from the gamma gray voltage circuit in response to the video data RGB from the second latch. Of course, the gray scale voltage is selected and output as either one of positive polarity (+) and negative polarity (−) according to the polarity control signal POL from the timing controller 130.

The output circuit temporarily stores the analog R, G, and B pixel voltages selected by the DAC in an internal buffer and outputs them to the liquid crystal panel 100.

Through this process, the thin film transistor 101 on the liquid crystal panel 100 responds to the pixel voltages from the data lines DL1 to DLm + 1 in response to the gate voltages Vgl and Vgh from the gate lines GL1 to GLn. Or gray scale voltage) is supplied to the liquid crystal cell, and the liquid crystal cell controls the transmittance of light provided from the backlight 220 by driving the liquid crystal positioned between the common electrode and the pixel electrode in response to the pixel voltage. The image is realized by the transmittance of light passing through the panel 100.

5 is a diagram illustrating a pixel operating state for implementing a yellow image on the liquid crystal panel of FIG. 4 according to the first embodiment of the present invention.

As illustrated in FIG. 5, in order to implement a yellow image on the liquid crystal panel 100, R and G sub pixels of the R, G, and B sub pixels formed on the liquid crystal panel 100 are turned on. do. In this case, the G subpixels of each horizontal line are driven by a high level pixel voltage applied through the same data lines DL2, DL5, ..., DLm-1, but the subpixels of R of the odd horizontal line are driven. The subpixels of R of the and eventh horizontal lines are different data lines DL1, DL4, DL7, ..., DLm-2; DL3, DL6, ..., DLm, which are alternately applied with high and low pixel voltages. Is driven through.

As a result, the data lines DL2, DL5, ..., DLm-1 that manage the G subpixels arranged in the even-numbered horizontal line are connected to the same data lines DL2, DL5, ..., DLm-1. Pre-charging of the data lines DL2, DL5, ..., DLm-1, for example data lines DL2, DL5, ..., DLm-1, due to the G subpixels turned on in the odd horizontal line. Since the parasitic capacitors present in the same state are first charged, the inhibitory factors such as line resistance and parasitic capacitance are reduced so that sufficient charging is performed on the G subpixels arranged in the even-numbered horizontal line during the horizontal period. do. In other words, this means that the G subpixels arranged in the even-numbered horizontal line are arranged in the even-numbered horizontal line and are free of the data lines DL2, DL5, ..., DLm-1 due to the turned-on G subpixels. Since charging is done, the same is true with sufficient charging.

On the other hand, the data lines DL1, DL4, DL7, ..., DLm-2, DL3, DL6, ..., DLm, which manage the subpixels of R arranged in the odd and even horizontal lines, are the even and odd numbers. Line charging and discharging of the data lines DL1, DL4, DL7, ..., DLm-2; DL3, DL6, ..., DLm due to the B subpixels arranged in the horizontal line and turned off The state is repeated and thus, for example, in order to charge the subpixels of R arranged in the even-order horizontal line, the data lines DL3, DL6, ..., DLm that manage the subpixels of R are first charged. Because the process must be preceded, due to the influence of the line resistance and parasitic capacitance of the data lines DL3, DL6, ..., DLm during the given horizontal period, sufficient charging is performed on the R pixels in comparison with the above case. It becomes impossible. Of course, this also applies to charging the subpixels of R arranged in the odd horizontal line.

However, the present invention is connected to the same data lines DL2, DL5, ..., DLm-1, respectively, and is charged to the subpixels of R formed in the odd and even horizontal lines adjacent to the G subpixels driving. The size of the charging amount becomes the same, and furthermore, the size of the total charging amount of the pixel having the R, G, and B subpixels as one pixel unit is also kept the same, so that the pixel which is yellow for each horizontal line is obtained. Since the yellow color has the same luminance, the line dim phenomenon is prevented.

On the other hand, in this case, for example, the red, green, and blue images are implemented on the liquid crystal panel 100 by turning on all the sub-pixels of R, G, and B, respectively. In this case, the R and B subpixels have the same luminance as each subpixel does not have sufficient charging for each subpixel during a given horizontal period, whereas the G subpixels are given for each horizontal line. Sufficient charging is performed on the subpixels during one horizontal period, thereby achieving the same luminance. In both cases, the line dim phenomenon is prevented because the subpixels formed on the odd and even horizontal lines have the same amount of charge regardless of how much the charge amount is charged to each subpixel.

6 is a diagram illustrating a pixel operation state for implementing a cyan image on the liquid crystal panel of FIG. 4 according to the second embodiment of the present invention.

As shown in FIG. 6, in order to implement a turquoise image on the liquid crystal panel 100, subpixels G and B of the R, G, and B subpixels formed on the liquid crystal panel 100 may be turned on. . At this time, a high level pixel voltage is applied to the G subpixels formed on the odd and even horizontal lines through the same data lines DL2, DL5, ..., DLm-1, but the subpixel of B of the odd horizontal lines is applied. The pixels and the subpixels of B of the even-th horizontal line are different data lines DL3, DL6, ..., DLm; DL4, DL7, ..., DLm + 1 to which the high and low pixel voltages are alternately applied. Is driven through.

As a result, the subpixels of G connected to the same data lines DL2, DL5, ..., DLm-1 and arranged on each horizontal line are already in the data lines DL2, DL5, DL8, ..., DLm-1. Since the precharging of the data lines DL2, DL5, DL8, ..., DLm-1 is performed due to the high-level pixel voltage applied to the data lines DL2, DL5,... , The inhibitory factors due to the line resistance and parasitic capacitance of DLm-1) can be reduced so that sufficient charging can be provided to the subpixels of G arranged on each horizontal line, while B placed on the odd and even horizontal lines Different data lines DL1, DL4, DL7, ..., DLm-2, DL3, DL6, ..., DLm, which manage the subpixels of the respective pixels, are each data lines DL1, DL4, DL7, ..., DLm-. 2, each data line DL1, DL4, due to the subpixels of R connected to DL3, DL6, ..., DLm and turned off; The charging and discharging states of DL7, DLm-2, DLm-2, DL3, DL6, ..., DLm are repeatedly present so that different data lines DL1, DL4, DL7, ..., The line resistance and parasitic capacitance of DLm-2, DL3, DL6, ..., DLm) may be affected to prevent sufficient charging of the corresponding subpixels.

However, similarly to the foregoing, the amount of charges charged in the B subpixels formed in each horizontal line is the same, so that the total amount of the charge amount of the pixel having the R, G, and B subpixels as one unit is the same. As a result, pixels having a turquoise color for each horizontal line have a turquoise color having the same luminance, thereby preventing a line dim phenomenon.

7 is a diagram illustrating a pixel operation state for implementing a purple image on the liquid crystal panel of FIG. 4 according to the third embodiment of the present invention.

As shown in FIG. 7, the subpixels R and B of the R, G, and B subpixels formed on the liquid crystal panel 100 may be turned on for the purple image on the liquid crystal panel 100. In this case, the R and B subpixels arranged in each horizontal line are pixels of a high level applied through the same data lines DL1, DL3, DL4, DL6, DL7, ..., DLm-2, DLm, DLm + 1. Driven by a voltage, while G subpixels arranged in each horizontal line are driven by a low level pixel voltage applied through the same data lines DL2, DL5, ..., DLm-1.

Thus, the subpixels of R and B arranged in the even-numbered horizontal line and the subpixels of R and B arranged in the even-numbered horizontal line are the same data lines DL1, DL3, DL4, DL6, DL7,. Due to the high level pixel voltage applied to DLm-2, DLm, DLm + 1), the data lines DL1, DL3, DL4, DL6, DL7, ..., DLm-2, DLm, DLm + 1 are already free. Since charging is performed, the inhibitory factors due to the line resistance and parasitic capacitance of the data lines DL1, DL3, DL4, DL6, DL7, ..., DLm-2, DLm, DLm + 1 are reduced during the given horizontal period. Thus, sufficient charging is performed on both the R and G subpixels arranged in each horizontal line.

This means that the amount of charges charged to each of the R and B subpixels formed in each horizontal line is the same, so that the total amount of charge of the pixels having the R, G, and B subpixels as one unit is the same. As a result, the pixels that are purple for each horizontal line have the same purple color to prevent the line dim phenomenon.

In addition, suppose that the luminance of R and B is different with reference to FIG. 7. At this time, the same data lines DL1, DL3, DL4, DL6, DL7, ..., DLm-2, DLm, DLm + 1 are connected so that R is always charged by B, whereas B is always charged by R. As a result, the total charging amount of R, G, and B, which is the pixel unit in the odd-numbered and even-numbered horizontal lines, becomes the same, and as a result, a line dim phenomenon is prevented by implementing purple colors having the same luminance.

In short, the present invention provides a liquid crystal display device in which sub-pixels are connected in a zigzag form and driven based on one data line, based on the above descriptions. A subpixel having the same color of one of the subpixels is connected to and driven by the same data line. To this end, one sub-pixel having the same color connected to and driven by the same data line may be any one of R, G, and B pixels. According to the present invention, G subpixels are connected to the same data line. Only one example has been described. As a result, the subpixels of the liquid crystal display have a pixel array of "RGBRGB ...... RGB" in the odd horizontal line, while the pixel array of "GRBGRB ...… GRB" in the even horizontal line.

If the subpixels of R are configured to be connected to the same data line to drive, the subpixels of the liquid crystal display form a pixel array of "GRBGRB ...... GRB" in the odd horizontal line, and "RGBRGB" in the even horizontal line. ... will have a pixel array of RGB ".

Therefore, the present invention can be variously modified within the scope without departing from the technical spirit of the scope of the claims to be disclosed in the following claims.

1 is a view showing the configuration of a liquid crystal display device according to the prior art;

FIG. 2 is a waveform diagram illustrating potential states of subpixels R and G that are turned on when a yellow image is implemented on the liquid crystal panel of FIG.

3 is a view illustrating a driving unit of a liquid crystal display according to the present invention.

4 is a diagram illustrating a pixel structure formed on a liquid crystal panel of FIG. 3.

5 is a diagram illustrating a pixel driving state for implementing a yellow image on the liquid crystal panel of FIG. 4;

FIG. 6 is a diagram illustrating a pixel driving state for implementing a cyan image on a liquid crystal panel of FIG. 4.

7 is a diagram illustrating a pixel driving state for implementing a purple image on the liquid crystal panel of FIG. 4;

Claims (5)

When the subpixels of R (red), green (G), and blue (B), which are defined by crossing a plurality of gate lines and data lines, are formed in a plurality of horizontal lines, It includes subpixels of the same color arranged in each of the odd and even horizontal lines in the vertical direction and in two columns in a zig-zag pattern, each having the same color. , A liquid crystal panel in which subpixels of the same color forming one zig-zag column of two subpixels of the same color forming two columns in the zig-zag behavior are connected to the same data line; A data driver applying a pixel voltage to a plurality of data lines formed in the liquid crystal panel; A gate driver for applying a control signal to a gate line of the liquid crystal panel; And And a timing controller configured to control the gate and the data driver by receiving data and vertical / horizontal synchronization signals from the outside and generating data rearrangement and control signals. The R, G, and B subpixels formed on the odd horizontal lines form an array of "RGBRGB ... ..RGB", and the R, G, B subpixels formed on the even horizontal line are "GRBGRB." A liquid crystal display device comprising an array of ... GRB ". 2. The R, G and B subpixels formed in the odd horizontal lines form an array of "GRBGRB ...... GRB", and the R, G and B subpixels formed in the even horizontal line are "RGBRGB." ... Liquid crystal display characterized by forming an array of "RGB". The liquid crystal display device according to claim 1, wherein the sub pixels on the liquid crystal panel have the same polarity in a zigzag form. The liquid crystal display device according to claim 1, wherein the subpixels connected to and driven on the same data line are G subpixels.

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