KR20140062297A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display according to the present invention includes: a liquid crystal display panel on which a plurality of gate lines and a plurality of data lines intersect and which includes liquid crystal cells in an intersection part; and a data driving circuit which includes output channels connected to the data lines one-to-one and controls the polarity of data outputted to output channels with a column inversion method. On the liquid crystal panel, the data with a polarity inversion cycle of either -+-++-+- or +-+--+-+ is repeatedly applied to the horizontally adjacent liquid crystal cells to which the gate lines are extended and the data with an opposite polarity is applied to the vertically adjacent liquid crystal cells to which the data lines are extended.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to various display devices such as portable information devices, office equipment, computers, and televisions. Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

The liquid crystal display adopts an inversion method in which the polarity of data applied to the liquid crystal cell is periodically inverted in order to alleviate deterioration of the liquid crystal over time. The inversion method includes a line inversion method of inverting the polarity of data in units of vertical 1-dot unit and horizontal liquid crystal cell line as shown in FIG. 1, and a method of inverting the polarity of data in vertical 1-dot unit and horizontal 2-dot unit as shown in FIG. A version method in which a horizontal two-dot is inverted is known.

When implementing the line inversion method of FIG. 1 or the version method of two horizontal dots of FIG. 3, a method for reducing the number of output transitions of the data driver in order to reduce the power consumption of the data driver has been proposed. For example, the polarity of data output from the data driver to the data line is controlled in a column-inversion manner, and the connection between the liquid crystal cell and the data line is controlled so that a line inversion method in the liquid crystal display panel or a horizontal two- A power consumption reduction technique which realizes a power consumption reduction method is known.

However, if the resolution is improved while periodically reversing the polarity of the data, the time required to invert the polarity of the pixels is shortened, and smear phenomenon occurs.

The smear phenomenon is a phenomenon in which when a window smear pattern in which white / black is repeated in a two-pixel-by-two pixel line along a vertical direction in a background pattern of a halftone as shown in Fig. 2 is generated, Which means a luminance variation in a pattern similar to a window smear pattern. Therefore, the smear defect appears as a line dim phenomenon in the vertical direction. The reason for the smear phenomenon is that the dominant polarity in the window smear pattern is inverted in the horizontal liquid crystal cell line and the common voltage of the corresponding line is changed according to the dominant polarity.

Referring to FIG. 3, the principle of generating a smear defect will be described in detail as follows. In FIG. 3, the dominant polarity is the positive polarity (+) liquid crystal cell having a white gradation and the negative polarity (-) liquid crystal cell having a white gradation in each horizontal liquid crystal cell line of the window smear pattern, . In other words, the dominant polarity is set to negative (-) in each of the odd horizontal liquid crystal cell lines (L # 1, L # 3, L # 5, L # (+) In the cell lines (L # 2, L # 4, L # 6).

The common voltage Vcom must be maintained at a constant input level between the positive (+) data voltage and the negative (-) data voltage. However, since the common electrode to which the common voltage Vcom is applied and the pixel electrode to which the data voltage is applied are coupled to the liquid crystal capacitor and the storage capacitor, the positive polarity (+) and the negative polarity -) direction.

The common voltage Vcom is shifted in the negative polarity direction in the odd and even horizontal liquid crystal cell lines L # 1, L # 3, L # 5, L # 7 and L # n, Resulting in a luminance deviation in the pattern. In this background pattern, positive (+) liquid crystal cells are displayed brighter than negative (-) liquid crystal cells. The positive polarity (+) liquid crystal cells are displayed in the Y-gradation higher than the X-gradation to be originally displayed due to the (-) shift of the common voltage Vcom.

The common voltage Vcom shifts in the negative polarity direction in the excellent horizontal liquid crystal cell lines L # 2, L # 4 and L # 6, resulting in a luminance deviation in the background pattern belonging to the horizontal liquid crystal cell line. In this background pattern, negative (-) liquid crystal cells are displayed brighter than positive (+) liquid crystal cells. The negative polarity (-) liquid crystal cells are displayed at Y gradations higher than the X gradation to be originally displayed due to the (+) shift of the common voltage Vcom.

These smear phenomena degrade the display quality.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of preventing a common voltage shift according to a data pattern to suppress smear phenomenon.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and liquid crystal cells are formed at intersections thereof; And a data driving circuit including output channels connected in a one-to-one manner to the data lines and controlling a polarity of data output to the output channels in a column inversion manner; The liquid crystal cells adjacent in the horizontal direction in which the gate lines extend in the liquid crystal display panel are provided with data of which polarity inversion period is any one of '- + - ++ - + -' and '+ - + - + - +' And data of opposite polarities are applied to the liquid crystal cells neighboring in the vertical direction in which the data lines are extended.

In the present invention, the polarity of data applied to data lines is controlled in a column-by-version manner, and the horizontal polarity inversion period of data applied to the liquid crystal cells through the pixel array connection structure is set to '- + - ++ - And '+ - + - + - +'. As a result, the present invention prevents the common voltage shift according to the data pattern, thereby effectively suppressing the smear phenomenon without using a separate pattern recognition algorithm or the like.

1 is a diagram showing a polarity pattern of a line-inversion method;
FIG. 2 is a view showing a specific data pattern in which a smear phenomenon occurs. FIG.
FIG. 3 is a view for explaining a principle in which a smear phenomenon occurs in a version method with horizontal 2 dots. FIG.
4 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
5 is a view showing a pixel array of a liquid crystal display panel for suppressing smear phenomenon.
6 is a view showing a part of the pixel array of FIG. 5;
7 is a view showing the principle of suppressing the smear phenomenon in the pixel array structure as shown in Figs. 5 and 6. Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 7. FIG.

4 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 15 and the gate lines 16. [

On the lower glass substrate of the liquid crystal display panel 10, a pixel array is formed. The pixel array includes liquid crystal cells Clc formed at intersections of the data lines 15 and the gate lines 16, TFTs connected to the pixel electrodes 1 of the liquid crystal cells, A common electrode 2 and a storage capacitor Cst. The pixel array can be implemented as shown in Fig. 5 so as to suppress the smear phenomenon. Each of the liquid crystal cells Clc is connected to the TFT and driven by an electric field between the pixel electrode 1 and the common electrode 2. On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and the like are formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS . The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives digital video data RGB of an input image from the system board 14 through a low voltage differential signaling (LVDS) interface method and converts the digital video data RGB of the input video into mini-LVDS And supplies it to the data driving circuit 12 through an interface method. The timing controller 11 aligns the digital video data (RGB) input from the system board 14 in accordance with the configuration of the pixel array as shown in FIG. 7, and supplies the data to the data driving circuit 12.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 14, And generates control signals for controlling the operation timing of the drive circuit 12 and the gate drive circuit 13. [ The control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit 13 and a data timing control signal for controlling the operation timing of the data drive circuit 12. [ The timing controller 11 controls the timing controller 11 so that the digital video data RGB input at a frame frequency of 60 Hz is displayed on the pixel array of the liquid crystal display panel 10 at a frame frequency of 60 x i The frequency of the timing control signal and the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the data driving circuit 12. The source sampling clock SSC is a clock signal for controlling sampling timing of data in the data driving circuit 12 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages sequentially output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driving circuit 12.

The data driving circuit 12 includes a shift register, a latch array, a digital-analog converter, an output circuit, and the like. The data driving circuit 12 latches the digital video data RGB according to the data timing control signal, converts the latched data into analog positive / negative gamma compensation voltages, and supplies a plurality of data voltages whose polarities are inverted at predetermined intervals Lt; / RTI > to the data lines 15 via the output channels of the output lines.

Each of the output channels is connected to the data lines 15 on a one-to-one basis. The data driving circuit 12 controls the polarity of the data voltages output to the output channels in a column inversion manner in order to reduce power consumption. Based on the column-inversion scheme, the polarity of the data voltages output on the same output channel is inverted on a frame-by-frame basis, and the polarities of the data voltages output on the neighboring output channels are opposite to each other.

The gate driving circuit 13 sequentially supplies gate pulses to the gate lines 16 in accordance with gate timing control signals using a shift register and a level shifter. The shift register of the gate drive circuit 13 may be formed directly on a lower glass substrate according to a GIP (Gate-Driver In Panel) method.

5 shows a pixel array of the liquid crystal display panel 10 for suppressing smear phenomenon. Figure 6 shows a portion of the pixel array of Figure 5;

Referring to FIG. 5, the pixel array includes data lines D1 to D17 and gate lines G1 to G5, and liquid crystal cells are arranged in each intersection region. The polarity of the data applied to the data lines D1 to D17 is controlled in a column inversion manner. The polarities of data applied to the neighboring data lines are inverted with respect to each other. Each liquid crystal cell is connected to a data line disposed on its left side or right side via a TFT. Each liquid crystal cell receives data from a data line by being turned on according to a gate pulse from the gate line. Data in which the polarity inversion period is any one of '- + - ++ - + -' and '+ - + - + - +' is repeatedly applied to eight liquid crystal cells neighboring in the horizontal direction And data of opposite polarities are applied to the liquid crystal cells neighboring in the vertical direction (data line extending direction). For example, as shown in FIG. 5, 'negative', positive (+), negative (-), positive (+), and negative Data in which the positive polarity (+), the negative polarity (-), the positive polarity (+), and the negative polarity (-) 'are inverted are applied, and in each of the excellent horizontal liquid crystal cell lines, (+), Negative (-), positive (+), negative (-), negative (-), positive (+), negative (-), positive &Quot; is applied.

To this end, the liquid crystal cells adjacent to each other in the vertical direction and arranged horizontally in the horizontal direction share the odd-numbered gate lines therebetween, and the liquid crystal cells arranged in the odd- Share the gate line.

Liquid crystal cells arranged adjacent to each other in the vertical direction between the first data line and the second data line to which data of different polarities are applied are alternately connected to the first data line and the second data line. The TFTs connected to the same data line are arranged in a zigzag manner along the vertical direction to electrically connect the liquid crystal cell and the data line disposed on the left side (or right side) of the liquid crystal cell.

Referring to FIG. 6, the connection structure of the liquid crystal cell will be described in detail. In order to drive the sixteen liquid crystal cells P11 to P18 and P21 to P28 disposed in the two horizontal liquid crystal cell lines, 9 data lines D1 to D9 arranged in sequence and three gate lines G1, G2 and G3 sequentially arranged along the vertical direction are allocated to the two horizontal liquid crystal cell lines. Liquid crystal cells P11 to P18 are sequentially arranged in the horizontal direction in the horizontal liquid crystal cell line, and liquid crystal cells P21 to P28 are arranged in the horizontal direction in the horizontal liquid crystal cell line.

The liquid crystal cell P11 is connected to the data line D2 disposed on the right side thereof through the TFT T11 and connected to the gate line G2 disposed thereunder to charge the negative polarity (-) data. The liquid crystal cell P12 adjacent to the liquid crystal cell P11 in the horizontal direction is connected to the data line D3 disposed on the right side thereof via the TFT T12 and connected to the gate line G1 disposed thereon to charge the positive polarity data . The liquid crystal cell P13 adjacent to the liquid crystal cell P12 in the horizontal direction is connected to the data line D4 disposed on the right side thereof via the TFT T13 and connected to the gate line G2 disposed thereunder to charge the negative polarity (-) data do. The liquid crystal cell P14 adjacent to the liquid crystal cell P13 in the horizontal direction is connected to the data line D5 disposed on the right side thereof via the TFT T14 and connected to the gate line G1 disposed thereon to charge the positive polarity data .

The liquid crystal cell P15 horizontally adjacent to the liquid crystal cell P14 is connected to the data line D5 disposed on the left side thereof via the TFT T15 and connected to the gate line G2 disposed thereunder to charge the positive polarity data . The liquid crystal cell P16 adjacent to the liquid crystal cell P15 in the horizontal direction is connected to the data line D6 disposed on the left side thereof via the TFT T16 and connected to the gate line G1 disposed thereon to charge the negative (-) data . The liquid crystal cell P17 adjacent to the liquid crystal cell P16 in the horizontal direction is connected to the data line D7 disposed on the left side thereof via the TFT T17 and connected to the gate line G2 disposed thereunder to charge the positive polarity data do. The liquid crystal cell P18 adjacent to the liquid crystal cell P17 in the horizontal direction is connected to the data line D8 disposed on the left side thereof via the TFT T18 and connected to the gate line G1 disposed thereon to charge the negative (-) data .

The liquid crystal cell P21 vertically adjacent to the liquid crystal cell P11 is connected to the data line D1 disposed on the left side thereof via the TFT T21 and connected to the gate line G2 disposed thereon to charge the positive data. The liquid crystal cell P22 neighboring the liquid crystal cell P21 and horizontally adjacent to the liquid crystal cell P12 and vertically adjacent to the liquid crystal cell P12 is connected to the data line D2 disposed on the left side thereof via the TFT T22 and connected to the gate line G3 disposed thereunder, Charge the polarity (-) data. The liquid crystal cell P23 which is adjacent to the liquid crystal cell P22 in the horizontal direction and is adjacent to the liquid crystal cell P13 vertically is connected to the data line D3 disposed on the left side thereof via the TFT T23 and connected to the gate line G2 disposed thereon, (+) Data is charged. The liquid crystal cell P24 which is adjacent to the liquid crystal cell P23 in the horizontal direction and which is adjacent to the liquid crystal cell P14 in the vertical direction is connected to the data line D4 disposed on the left side thereof via the TFT T24 and connected to the gate line G3 disposed thereunder, Charge the polarity (-) data.

The liquid crystal cell P25, which is horizontally adjacent to the liquid crystal cell P24 and vertically adjacent to the liquid crystal cell P15, is connected to the data line D6 disposed on the right side thereof via the TFT T25 and connected to the gate line G2 disposed thereon, +) ≪ / RTI > The liquid crystal cell P26 adjacent to the liquid crystal cell P25 and horizontally adjacent to the liquid crystal cell P16 and vertically adjacent to the liquid crystal cell P16 is connected to the data line D7 disposed on the right side thereof via the TFT T26 and connected to the gate line G3 disposed thereunder, Charge the polarity (+) data. The liquid crystal cell P27 adjacent to the liquid crystal cell P26 in the horizontal direction and vertically adjacent to the liquid crystal cell P17 is connected to the data line D8 disposed on the right side thereof via the TFT T27 and connected to the gate line G2 disposed thereon, (-) data is charged. The liquid crystal cell P28 adjacent to the liquid crystal cell P27 in the horizontal direction and vertically adjacent to the liquid crystal cell P18 is connected to the data line D9 disposed on the right side thereof via the TFT T28 and connected to the gate line G3 disposed thereunder, Charge the polarity (+) data.

FIG. 7 shows the principle of suppressing the smear phenomenon in the pixel array structure as shown in FIG. 5 and FIG.

In the present invention, the polarity of data applied to the data lines is controlled in a column-by-version manner, while the horizontal polarity inversion period of data applied to the liquid crystal cells through the pixel array connection structure is set to ' - + - 'and' + - + - + - + '. When data is supplied to the pixel array such that the low gray level and the white gray level alternate in units of three liquid crystal cells (i.e., one pixel) adjacent to each other in the horizontal direction as shown in FIG. 7, The polarity (+) and negative polarity (-) cancel each other on average, so that the dominant polarity does not appear in each horizontal line.

The pixels having a low gray level and the pixels having a white gray level in the (N + 1) th horizontal line between the Nth horizontal line between the gate lines G1 and G2 and the gate lines G2 and G3 are mixed with each other to form a check board. The gradation pattern of the (N + 2) th horizontal line located between the gate lines G3 and G4 is obtained by shifting the gradation pattern of the Nth horizontal line by one liquid crystal cell to the right, The gray level pattern of the (N + 1) th horizontal line is shifted to the right by one liquid crystal cell. The pixels having a low gray level and the pixels having a white gray level in the (N + 2) th horizontal line and the (N + 3) th horizontal line are mixed with each other to form a check board. The gradation pattern of the (N + 4) th horizontal line located between the gate lines G5 and G6 is obtained by shifting the gradation pattern of the Nth horizontal line by two liquid crystal cells to the right, The gray level pattern of the (N + 1) th horizontal line is shifted to the right by two liquid crystal cells. The pixels having a low gray level and the pixels having a white gray level in the (N + 4) th horizontal line and the (N + 5) th horizontal line are mixed with each other to form a check board.

FIG. 7 shows polarity distribution of pixels of each horizontal line sharing each gate line. Pixels arranged in the pixel lines X1 to X8 while sharing the respective gate lines G2 to G7 each have eight polarity distributions. Since these eight pixel data polarities cancel each other, the dominant polarity does not appear for each of the two vertically adjacent horizontal lines across the gate line. Therefore, the common voltage Vcom is not shifted by the dominant polarity, and the common voltage Vcom is maintained at the original input level.

As described above, according to the present invention, the polarity of data applied to the data lines is controlled by the column inversion method, and the horizontal polarity inversion period of data applied to the liquid crystal cells through the pixel array connection structure is set to '- + - ++ - + - 'and' + - + - + - + '. As a result, the present invention prevents the common voltage shift according to the data pattern, thereby effectively suppressing the smear phenomenon without using a separate pattern recognition algorithm or the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: data driving circuit 13: gate driving circuit

Claims (6)

A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and liquid crystal cells are formed at intersections thereof; And
And a data driving circuit including output channels connected one-to-one to the data lines and controlling a polarity of data output to the output channels in a column inversion manner;
The liquid crystal cells adjacent in the horizontal direction in which the gate lines extend in the liquid crystal display panel are provided with data of which polarity inversion period is any one of '- + - ++ - + -' and '+ - + - + - +' And data of opposite polarities are applied to the liquid crystal cells neighboring in the vertical direction in which the data lines are extended. The method according to claim 1,
In the liquid crystal display panel, the liquid crystal cells adjacent to each other in the vertical direction and horizontally arranged in the horizontal direction share the odd-numbered gate lines therebetween, and the liquid crystal cells arranged in the odd- And the odd-numbered gate lines of the odd-numbered gate lines are shared. The method according to claim 1,
The liquid crystal cells arranged adjacent to each other in the vertical direction between the first data line and the second data line to which data of different polarities are applied are alternately connected to the first data line and the second data line;
And the TFTs connected to the same data line are arranged in a zigzag manner along the vertical direction to electrically connect the liquid crystal cell and a data line disposed on the left or right side of the liquid crystal cell. The method according to claim 1,
The liquid crystal display panel includes nine data lines D1 to D9 sequentially arranged along the horizontal direction and two horizontal liquid crystal cell lines GL1 to GL3 by three gate lines G1 to G3 sequentially arranged along the vertical direction. 16 liquid crystal cells are driven;
Among the sixteen liquid crystal cells, the liquid crystal cell P11, the liquid crystal cell P12, the liquid crystal cell P13, the liquid crystal cell P14, the liquid crystal cell P15, the liquid crystal cell P16, the liquid crystal cell P17 and the liquid crystal cell P18, Disposed in a horizontal liquid crystal cell line;
Among the sixteen liquid crystal cells, the liquid crystal cell P21, the liquid crystal cell P22, the liquid crystal cell P23, the liquid crystal cell P24, the liquid crystal cell P25, the liquid crystal cell P26, the liquid crystal cell P27, and the liquid crystal cell P28 are arranged adjacent to the first horizontal liquid crystal cell line And the liquid crystal display device. 5. The method of claim 4,
The liquid crystal cell P11 is connected to the data line D2 disposed on the right side of the liquid crystal cell P11 via the TFT T11 and connected to the gate line G2 disposed below the liquid crystal cell P11 to charge the negative polarity data and; The liquid crystal cell P12 adjacent to the liquid crystal cell P11 in the horizontal direction is connected to the data line D3 disposed on the right side of the liquid crystal cell P12 via the TFT T12 and connected to the gate line G1 disposed on the liquid crystal cell P12 Charging the positive (+) data; The liquid crystal cell P13 adjacent to the liquid crystal cell P12 in the horizontal direction is connected to the data line D4 disposed on the right side of the liquid crystal cell P13 via the TFT T13 and connected to the gate line G2 disposed below the liquid crystal cell P13 To charge negative (-) data; The liquid crystal cell P14 adjacent to the liquid crystal cell P13 in the horizontal direction is connected to the data line D5 disposed on the right side of the liquid crystal cell P14 via the TFT T14 and connected to the gate line G1 disposed on the liquid crystal cell P14 Thereby filling data of positive polarity (+);
The liquid crystal cell P15 horizontally adjacent to the liquid crystal cell P14 is connected to the data line D5 disposed on the left side of the liquid crystal cell P15 through the TFT T15 and connected to the gate line G2 disposed below the liquid crystal cell P15 To charge data of positive polarity (+); The liquid crystal cell P16 adjacent to the liquid crystal cell P15 in the horizontal direction is connected to the data line D6 disposed on the left side of the liquid crystal cell P16 via the TFT T16 and connected to the gate line G1 disposed on the liquid crystal cell P16 To charge negative data (-); The liquid crystal cell P17 adjacent to the liquid crystal cell P16 in the horizontal direction is connected to the data line D7 disposed on the left side of the liquid crystal cell P17 via the TFT T17 and connected to the gate line G2 disposed below the liquid crystal cell P17 To charge data of positive polarity (+); The liquid crystal cell P18 adjacent to the liquid crystal cell P17 in the horizontal direction is connected to the data line D8 disposed on the left side of the liquid crystal cell P18 via the TFT T18 and connected to the gate line G1 disposed on the liquid crystal cell P18 And the negative polarity (-) data is charged. 6. The method of claim 5,
The liquid crystal cell P21 vertically adjacent to the liquid crystal cell P11 is connected to the data line D1 disposed on the left side of the liquid crystal cell P21 via the TFT T21 and connected to the gate line G2 disposed on the liquid crystal cell P21 Thereby filling data of positive polarity (+); The liquid crystal cell P22 which is adjacent to the liquid crystal cell P21 in the horizontal direction and is vertically adjacent to the liquid crystal cell P12 is connected to the data line D2 disposed on the left side of the liquid crystal cell P22 via the TFT T22, (-) data connected to the gate line G3 disposed under the gate line G3; The liquid crystal cell P23 adjoining the liquid crystal cell P22 in the horizontal direction and vertically adjacent to the liquid crystal cell P13 is connected to the data line D3 disposed on the left side of the liquid crystal cell P23 via the TFT T23 and connected to the liquid crystal cell P23 (+) Data connected to the gate line G2 disposed on the gate line G2; The liquid crystal cell P24 adjacent to the liquid crystal cell P23 in the horizontal direction and vertically adjacent to the liquid crystal cell P14 is connected to the data line D4 disposed on the left side of the liquid crystal cell P24 via the TFT T24, (-) data connected to the gate line G3 disposed under the gate line G3;
The liquid crystal cell P25 which is horizontally adjacent to the liquid crystal cell P24 and is vertically adjacent to the liquid crystal cell P15 is connected to the data line D6 disposed on the right side of the liquid crystal cell P25 via the TFT T25, (+) Data connected to the gate line G2 disposed above the gate line G2; The liquid crystal cell P26 adjacent to the liquid crystal cell P25 in the horizontal direction and vertically adjacent to the liquid crystal cell P16 is connected to the data line D7 disposed on the right side of the liquid crystal cell P26 via the TFT T26, (+) Data connected to the gate line G3 disposed under the gate line G3; The liquid crystal cell P27 adjacent to the liquid crystal cell P26 in the horizontal direction and vertically adjacent to the liquid crystal cell P17 is connected to the data line D8 disposed on the right side of the liquid crystal cell P27 via the TFT T27, (-) data connected to the gate line G2 disposed on the gate line G2; The liquid crystal cell P28 adjacent to the liquid crystal cell P27 in the horizontal direction and vertically adjacent to the liquid crystal cell P18 is connected to the data line D9 disposed on the right side of the liquid crystal cell P28 via the TFT T28, (+) Data is connected to the gate line (G3) disposed below the liquid crystal display panel.

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