KR20110072290A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to reduce the power consumption of a liquid crystal display by varying the brightness of a backlight unit according to the change of the polarity of a data voltage. CONSTITUTION: An LCD panel(100) supplies data voltages of which polarity is reversed in frame inversion. A backlight unit projects light on the LCD panel. A backlight driver(105) drives the light source of the backlight unit. A back light controller(104) supplies back light dimming data to the backlight driver. The back light controller controls the brightness of the back light to be higher than that of a frame period.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

BACKGROUND ART Liquid crystal display devices have tended to be gradually widened due to their light weight, thinness, and low power consumption. The liquid crystal display device is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment, indoor and outdoor advertising display devices, and the like. The liquid crystal display displays an image by controlling an electric field applied to the liquid crystal cells to modulate the light incident from the backlight unit.

The liquid crystal display device is driven in an inversion method in which polarities of data voltages charged in neighboring liquid crystal cells are opposite to each other and the polarities of the data voltages are periodically reversed in order to reduce DC afterimages and prevent deterioration of liquid crystals.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a thin film transistor (TFT) that is formed for each pixel and switches a data voltage supplied to the pixel electrode, and a data driving circuit for supplying data voltage to data lines of the liquid crystal display panel. A gate driving circuit for sequentially supplying gate pulses (or scan pulses) to gate lines of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

FIG. 1 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in a frame inversion. 2 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in a line inversion. 3 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in dot inversion.

In the frame inversion as shown in FIG. 1, all output channels of the data driving circuit output data voltages of the same polarity for one frame period, and invert the data voltage in one frame period. In the frame inversion, all the liquid crystal cells in the liquid crystal display panel charge the data voltages of the same polarity within one frame period.

In the line inversion as shown in Fig. 2, all output channels of the data driving circuit output data voltages of the same polarity within the same horizontal period and invert the polarity of the data voltage in one horizontal period and one frame period. In the line inversion, the odd-line liquid crystal cells and even-line liquid crystal cells of the liquid crystal display panel charge data voltages having opposite polarities.

In the dot inversion of FIG. 3, the polarity of the data voltage output through the odd output channels of the data driving circuit and the polarity of the data voltage output through the even output channels of the data driving circuit are opposite to each other. In the dot inversion, the polarity of the data voltage output through the output channels of the data driving circuit is inverted in one horizontal period period and one frame period period. In the dot inversion, the polarities of the data voltages charged in the left and right neighboring liquid crystal cells and the up and down neighboring liquid crystal cells are opposite to each other.

The power consumption of the liquid crystal display device increases as the polarity of the data voltage increases the number of inversions, that is, as the current consumption increases in the data lines. Therefore, the power consumption of the liquid crystal display device is the smallest in the frame inversion, relatively large in the line inversion and dot inversion, the largest in the dot inversion.

Frame inversion consumes less power than line inversion and dot inversion, but flicker is better observed than line inversion and dot inversion. This phenomenon will be described with reference to FIG. 4.

4 is a waveform diagram showing gate pulses and an output (SIC output data) of a data driving circuit in line inversion or dot inversion.

Referring to FIG. 4, a positive data voltage is charged in a first liquid crystal cell during a first horizontal period, and a negative data voltage is supplied in a second liquid crystal cell during a second horizontal period. The voltage (+ Vp) of the first liquid crystal cell charged with the positive data voltage is lowered by ΔVp due to the parasitic capacitance of the TFT. On the other hand, the voltage (-Vp) of the second liquid crystal cell charged with the negative data voltage is increased by ΔVp due to the parasitic capacitance of the TFT. In the line inversion or the dot inversion, the liquid crystal cells charged with the positive data voltage and the liquid crystal cells charged with the negative data voltage are alternated in units of one line or in units of one dot. Therefore, it is difficult for an observer to sense the difference between the luminance of the liquid crystal cell in which the positive data voltage is charged and the luminance of the liquid crystal cell in which the negative data voltage is charged at the line inversion or the dot inversion. In FIG. 4, "GP1" refers to the first gate pulse generated during the first horizontal period, and "GP2" refers to the second gate pulse generated during the second horizontal period. "Vdata" is a data voltage output from the data driving circuit.

On the other hand, if the polarities of the data voltages charged in all liquid crystal cells for one frame period in the frame inversion are the same, the observer may feel flicker in which the luminance fluctuates in one frame period. According to the driving characteristics of the liquid crystal display, the display image may appear bright during the frame period in which the positive data voltage is charged in the frame inversion, and the display image may appear bright during the frame period in which the negative data voltage is charged.

The present invention provides a liquid crystal display device by applying a frame inversion to reduce power consumption and to prevent display quality degradation at the frame inversion.

In one aspect of the present invention, a liquid crystal display device includes: a liquid crystal display panel to which data voltages whose polarities are reversed are supplied to a frame inversion; A backlight unit radiating light onto the liquid crystal display panel; A backlight driver for driving light sources of the backlight unit; And a backlight controller configured to supply backlight dimming data to the backlight driver to control backlight brightness.

The backlight controller controls the backlight brightness to be higher than the backlight brightness of the frame period when the data voltage of the second polarity is supplied to the liquid crystal display panel during the frame period during which the data voltage of the first polarity is supplied to the liquid crystal display panel.

The present invention can apply the frame inversion and the backlight brightness according to the change in polarity of the data voltage to reduce the power consumption of the liquid crystal display device and prevent the display quality degradation.

The liquid crystal display of the present invention may be implemented in a liquid crystal mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, or fringe field switching (FFS). . The liquid crystal display of the present invention may be implemented in a normally white mode or a normally black mode when divided into transmittance versus voltage characteristics.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a backlight unit 110, a backlight controller 104, a backlight driver 105, a timing controller 101, and a data driver. 102 and a gate driver 103.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes m × n liquid crystal cells arranged in a matrix by a cross structure of m data lines D1 to Dm and n gate lines G1 to Gn.

The lower glass substrate of the liquid crystal display panel 100 includes a TFT array including data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes connected to the TFTs, a storage capacitor Cst, and the like. Is formed. 6 to 8 show various examples of the TFT array. A color filter array including a black matrix and a color filter is formed on the upper glass substrate of the liquid crystal display panel 100. The common electrode facing the pixel electrode with the liquid crystal cell interposed therebetween is formed on the upper glass substrate in the vertical electric field driving method such as TN mode and VA mode, together with the pixel electrode in the horizontal electric field driving method such as IPS mode and FFS mode. It is formed on the lower glass substrate.

Polarizing plates having optical axes perpendicular to the upper and lower glass substrates of the liquid crystal display panel 100 are attached. In at least one of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer.

The backlight unit 110 is disposed under the liquid crystal display panel 100. The backlight unit 110 uniformly irradiates light onto the liquid crystal display panel 100 including a plurality of light sources that are turned on and off by the backlight driver 105. The backlight unit 110 may be implemented as a direct type backlight unit or an edge type backlight unit. The light source of the backlight unit 110 may include one or two or more light sources of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode (LED). have. The backlight driver 105 lights and turns on the light sources of the backlight unit 110 by a pulse width modulation (PWM) method or a pulse amplitude modulation (PAM) method in response to the backlight dimming data DIM input from the backlight controller 104. Turn off

The backlight controller 104 analyzes the input image to calculate a representative value of the input image, selects backlight dimming data DIM according to the representative value, and modulates pixel data of the input image. In order to reduce flicker in the frame inversion, the backlight controller 104 adjusts the backlight brightness in the same manner as in FIGS. 9 to 12 according to the polarity of the data voltage supplied to the liquid crystal display panel 100. The backlight controller 104 may be built in the timing controller 101.

The timing controller 101 receives digital video data (RGB) from an external host computer through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 101 inputs digital video data RGB inputted from the host computer to the backlight controller 104 and transmits the data R'G'B 'modulated by the backlight controller 104 to the data driver 102. To be sent).

The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock CLK from a host computer through an LVDS or TMDS interface receiving circuit. Get input. The timing controller 101 generates timing control signals GDC and DDC for controlling the operation timing of the data driver 102 and the gate driver 103 based on the timing signal input from the host computer. The timing control signals include a gate timing control signal GDC for controlling the operation timing of the gate driver 103, and a data timing control signal for controlling the operation timing of the data driver 102 and the polarity of the data voltage.

The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is applied to a gate drive integrated circuit (IC) that generates the first gate pulse to control the shift start timing of the gate drive IC. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal DDC includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), and a source output enable signal (Source Output Enable, SOE) and the like. The source start pulse SSP is applied to the source drive IC sampling the first pixel data among the source drive ICs of the data driver 102 to control the shift start timing. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driving circuit 102 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs. If the digital video data to be input to the data driver 102 is transmitted using mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The data driver 102 includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The source drive ICs latch the digital video data R'G'B 'under the control of the timing controller 101. Source drive ICs convert digital video data (R'G'B ') into analog positive and negative gamma compensation voltages to reverse the polarity of the data voltages. Each of the source drive ICs is connected to data lines of the liquid crystal display panel by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driver 103 includes one or more gate drive ICs. Gate drive ICs include shift registers, level shifters, output buffers, and so on. The gate drive ICs sequentially supply gate pulses (or scan pulses) to the gate lines G1 to Gn in response to gate timing control signals GDC. Gate drive ICs of the gate driver 103 are connected to the gate lines of the lower glass substrate of the liquid crystal display panel 100 through a TAP process or on the lower glass substrate of the liquid crystal display panel 100 by a GIP (Gate In Panel) process. Can be formed directly on the.

6 to 8 are equivalent circuits showing various examples of the TFT array formed on the liquid crystal display panel 100.

In the TFT array shown in FIG. 6, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4. To feed. In the TFT array shown in FIG. 3, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels B along a row direction (or line direction) perpendicular to the column direction. . When the resolution of the TFT array shown in FIG. 4 is m × n, m × 3 (where 3 is RGB) data lines and n gate lines are required.

In the TFT array shown in FIG. 7, the number of data lines D1 to D4 required at the same resolution is 1/2 as compared to the TFT array shown in FIG. 6 by subpixels neighboring in the line direction sharing the same data line. The number of source drive ICs required can be reduced by one half. In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. In the TFT array illustrated in FIG. 7, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a line direction perpendicular to the column direction. Two liquid crystal cells adjacent in the line direction share the same data line and sequentially charge the data voltages supplied through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are defined as the first liquid crystal cell and the first TFT TFT1, respectively, and the liquid crystal cell and the TFT disposed on the right side of the data line D1 to D4 are defined. A connection relationship between the TFTs TFT1 and TFT2 will be described as defined by the second liquid crystal cell and the second TFT TFT2, respectively. The first TFT TFT1 supplies data voltages from the data lines D1 to D4 to the pixel electrodes of the first liquid crystal cell in response to gate pulses from the odd gate lines G1, G3, G5, and G7. The gate electrode of the first TFT TFT1 is connected to the odd gate lines G1, G3, G5, and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT (TFT1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT TFT2 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the second liquid crystal cell in response to the gate pulses from the even gate lines G2, G4, G6, and G8. The gate electrode of the second TFT TFT2 is connected to the even gate lines G2, G4, G6, and G8, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the second TFT (TFT2) is connected to the pixel electrode of the second liquid crystal cell.

The TFT array shown in FIG. 8 can arrange the sub-pixels of the same color in the row direction to reduce the number of data lines required at the same resolution as 1/3 compared to the TFT array shown in FIG. The number can be reduced to 1/3. In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the line direction. In the TFT array illustrated in FIG. 8, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G in the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6. To feed.

6 to 8 illustrate some examples of the TFT array applicable to the present invention, and the present invention is not limited thereto. The TFT arrays shown in FIGS.

9 is a waveform diagram illustrating a backlight control method according to a first embodiment of the present invention.

Referring to FIG. 9, the liquid crystal display of the present invention controls the polarity of the data voltage by one frame inversion method and the backlight brightness by PWM. The one-frame inversion method charges the data voltages of the same polarity to all liquid crystal cells of the liquid crystal display panel 100 within one frame period and inverts the polarity of the data voltage in one frame period.

When the liquid crystal display device of the normally white mode is driven by the one-frame inversion method, an even frame in which the luminance of the odd frame periods Fn and Fn + 2 to which the positive data voltage is supplied is supplied at the same gray level and the negative data voltage is supplied. It is higher than the periods Fn + 1 and Fn + 3. The backlight controller 104 performs a backlight during odd frame periods (Fn and Fn + 2) in which the positive data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally white mode is driven in the one frame inversion method. Increase the data value of the dimming data (DIM). The backlight driver 105 controls the duty ratio of the PWM signal in response to the backlight dimming data DIM during the odd frame periods Fn and Fn + 2 when the positive data voltage is supplied to the liquid crystal display panel 100. ) To increase the backlight brightness. In FIG. 9, "A + a" is the backlight on time increased according to the increased duty ratio during the odd frame periods Fn and Fn + 2, and "A" is the even frame period Fn + 1, Fn + 3) is the backlight on time determined by the default duty ratio.

On the other hand, when the liquid crystal display device of the normally black mode is driven by the one-frame inversion method, the luminance of the excellent frame periods (Fn + 1, Fn + 3) to which the negative data voltage is supplied is equal to the positive data voltage at the same gray level. It is higher than the odd frame periods Fn and Fn + 2 supplied. The backlight controller 104 has an excellent frame period (Fn + 1, Fn + 3) in which the negative data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally black mode is driven in the one frame inversion method. While increasing the data value of the backlight dimming data (DIM). The backlight driver 105 increases the duty ratio of the PWM signal in response to the backlight dimming data DIM during the even frame periods Fn + 1 and Fn + 3 when the negative data voltage is supplied to the liquid crystal display panel 100. Increase the brightness

10 is a waveform diagram illustrating a backlight control method according to a second embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display of the present invention controls the polarity of the data voltage by N (N is a positive integer of 2 or more) frame inversion method and the backlight brightness by PWM. The N frame inversion method charges the data voltages of the same polarity to all liquid crystal cells of the liquid crystal display panel 100 during the N frame period, and inverts the polarity of the data voltage at every N frame period.

When the liquid crystal display device of the normally white mode is driven by the N frame inversion method, the frame period during which the negative data voltage is supplied at the same gray level as the luminance of the frame periods Fn and Fn + 1 to which the positive data voltage is supplied ( It is higher than Fn + 2, Fn + 3). The backlight controller 104 dims the backlight during the frame periods (Fn and Fn + 1) during which the positive data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally white mode is driven by the one frame inversion method. Increase the data value of the data DIM. The backlight driver 105 adjusts the duty ratio of the PWM signal in response to the backlight dimming data DIM during the odd frame periods Fn and Fn + 2 when the positive data voltage is supplied to the liquid crystal display panel 100. Increase the backlight brightness.

On the other hand, when the liquid crystal display device of the normally black mode is driven by the N frame inversion method, the positive data voltage is supplied when the luminance of the frame periods Fn + 2 and Fn + 3 to which the negative data voltage is supplied is the same gray level. It is higher than the frame periods Fn and Fn + 1. The backlight controller 104 performs the frame periods Fn + 2 and Fn + 3 during which the negative data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally black mode is driven by the N frame inversion method. The data value of the backlight dimming data DIM is increased. The backlight driver 105 increases the duty ratio of the PWM signal in response to the backlight dimming data DIM during the frame periods Fn + 2 and Fn + 3 when the negative data voltage is supplied to the liquid crystal display panel 100, thereby increasing the backlight luminance. Increase

11 is a waveform diagram illustrating a backlight control method according to a third embodiment of the present invention.

Referring to FIG. 11, the liquid crystal display of the present invention controls the polarity of the data voltage by the one frame inversion method and the backlight brightness by the PAM.

When the liquid crystal display device of the normally white mode is driven by the one-frame inversion method, an even frame in which the luminance of the odd frame periods Fn and Fn + 2 to which the positive data voltage is supplied is supplied at the same gray level and the negative data voltage is supplied. It is higher than the periods Fn + 1 and Fn + 3. The backlight controller 104 performs a backlight during odd frame periods (Fn and Fn + 2) in which the positive data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally white mode is driven in the one frame inversion method. Increase the data value of the dimming data (DIM). The backlight driver 105 increases the brightness of the PAM signal by increasing the amplitude of the PAM signal in response to the backlight dimming data DIM during the odd frame periods Fn and Fn + 2 when the positive data voltage is supplied to the liquid crystal display panel 100. .

On the other hand, when the liquid crystal display device of the normally black mode is driven by the one-frame inversion method, the luminance of the excellent frame periods (Fn + 1, Fn + 3) to which the negative data voltage is supplied is equal to the positive data voltage at the same gray level. It is higher than the odd frame periods Fn and Fn + 2 supplied. The backlight controller 104 has an excellent frame period (Fn + 1, Fn + 3) in which the negative data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally black mode is driven in the one frame inversion method. While increasing the data value of the backlight dimming data (DIM). The backlight driver 105 increases the duty ratio of the PAM signal in response to the backlight dimming data DIM during the even frame periods Fn + 1 and Fn + 3 when the negative data voltage is supplied to the liquid crystal display panel 100. Increase the brightness

12 is a waveform diagram illustrating a backlight control method according to a fourth embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display of the present invention controls the polarity of the data voltage by the N frame inversion method and the backlight brightness by the PAM.

When the liquid crystal display device of the normally white mode is driven by the N frame inversion method, the frame period during which the negative data voltage is supplied at the same gray level as the luminance of the frame periods Fn and Fn + 1 to which the positive data voltage is supplied ( It is higher than Fn + 2, Fn + 3). The backlight controller 104 dims the backlight during the frame periods (Fn and Fn + 1) during which the positive data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally white mode is driven by the one frame inversion method. Increase the data value of the data DIM. The backlight driver 105 increases the brightness of the PAM signal by increasing the amplitude of the PAM signal in response to the backlight dimming data DIM during the odd frame periods Fn and Fn + 2 when the positive data voltage is supplied to the liquid crystal display panel 100. .

On the other hand, when the liquid crystal display device of the normally black mode is driven by the N frame inversion method, the positive data voltage is supplied when the luminance of the frame periods Fn + 2 and Fn + 3 to which the negative data voltage is supplied is the same gray level. It is higher than the frame periods Fn and Fn + 1. The backlight controller 104 performs the frame periods Fn + 2 and Fn + 3 during which the negative data voltage is supplied to the liquid crystal display panel 100 when the liquid crystal display device of the normally black mode is driven by the N frame inversion method. The data value of the backlight dimming data DIM is increased. The backlight driver 105 increases the amplitude of the PAM signal in response to the backlight dimming data DIM during the frame periods Fn + 2 and Fn + 3 when the negative data voltage is supplied to the liquid crystal display panel 100 to increase the backlight brightness. Increase

The liquid crystal display according to another exemplary embodiment of the present invention controls the polarity of the data voltage by the frame inversion method and the backlight brightness by the hybrid method using the PWM and the PAM. For example, during the frame period during which the positive data voltage (or the negative data voltage) is supplied, the duty ratio of the PWM signal for controlling the backlight brightness can be increased and the amplitude of the PWM signal can be increased.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

FIG. 1 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in a frame inversion.

2 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in a line inversion.

3 is a diagram illustrating polarities of data voltages applied to a liquid crystal display in dot inversion.

4 is a waveform diagram showing gate pulses and the output of the data driving circuit in line inversion or dot inversion.

5 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

6 to 8 are equivalent circuits showing various examples of the TFT array.

9 is a waveform diagram illustrating a backlight control method according to a first embodiment of the present invention.

10 is a waveform diagram illustrating a backlight control method according to a second embodiment of the present invention.

11 is a waveform diagram illustrating a backlight control method according to a third embodiment of the present invention.

12 is a waveform diagram illustrating a backlight control method according to a fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 102: data driver

103: gate driver 104: backlight controller

105: backlight driver

Claims (5)

A liquid crystal display panel to which data voltages whose polarities are inverted are supplied to the frame inversion; A backlight unit radiating light onto the liquid crystal display panel; A backlight driver for driving light sources of the backlight unit; And A backlight controller configured to supply backlight dimming data to the backlight driver to control backlight brightness; The backlight controller controls the backlight brightness to be higher than the backlight brightness of the frame period when the data voltage of the second polarity is supplied to the liquid crystal display panel during the frame period during which the data voltage of the first polarity is supplied to the liquid crystal display panel. Display device. The method of claim 1, The backlight controller, A first backlight dimming data value for controlling the backlight brightness during a frame period during which a data voltage of a first polarity is supplied to the liquid crystal display panel; And a second backlight dimming data value for controlling luminance. The method of claim 2, The backlight driver, And increasing the duty ratio of the PWM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming value. The method of claim 2, The backlight driver, And increasing the amplitude of the PAM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming value. The method of claim 2, The backlight driver, And increasing the duty ratio and amplitude of the PWM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming value.

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