KR101493081B1 - Liquid crystal display device and method of driving the same - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are disclosed.

A driving method of a liquid crystal display device generates a plurality of positive and negative data voltages and supplies each data voltage to dots on each gate line. A first supply delay period is located between adjacent data voltages having different polarities and a second supply delay period is located between adjacent data voltages having the same polarity. 1 and the second supply delay section have different intervals from each other.

Therefore, according to the present invention, data voltages of the same polarity are charged to dots on adjacent gate lines at the same charge amount, thereby preventing a line defect such as an odd defect or an even defect, thereby improving image quality.

Liquid crystal display, supply delay section, SOE signal vertical 2 dots

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality and a driving method thereof.

Due to the development of the information society, display devices capable of displaying information are actively being developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Of these, liquid crystal display devices have advantages such as light weight, low power consumption, and full color video implementation, and are widely applied to mobile phones, navigation, monitors, and televisions.

The liquid crystal display displays an image corresponding to a video signal by adjusting the light transmittance of the liquid crystal cells on the liquid crystal panel.

The liquid crystal display device may be either a line inversion mode, a column inversion system, a dot inversion system, or a 2-dot inversion mode. And is driven in one manner. The two-dot inversion scheme is divided into a vertical two-dot version scheme and a horizontal two-dot version scheme.

Among these driving methods, the vertical two-dot inversion method inverts data signals supplied to the liquid crystal panel with the same polarity in units of two gate lines as shown in FIG. At this time, data signals having different polarities are supplied to the respective data lines. In addition, the vertical two-dot inversion method reverses the polarity in frame units in terms of time.

As shown in Fig. 2, in order to drive in the vertical two-dot version mode, first, by the first gate high voltage VGH1 generated in the gate driver and supplied to the nth gate line GLn of the liquid crystal panel The first thin film transistor connected to the nth gate line GLn is turned on. The dot means a pixel region defined by a gate line and a data line of a liquid crystal panel. Accordingly, each dot may be a red dot, a green dot, and a blue dot. A pixel capable of realizing full color by red dots, green dots and blue dots can be defined. The first data voltage VD1 output from the data driver and supplied to the data line, for example, the first data line, is applied to the first thin film transistor via the first thin film transistor turned on on the nth gate line GLn And charged to the pixel electrode.

Then, the second thin film connected to the (n + 1) th gate line GLn + 1 by the second gate high voltage VGH2 generated in the gate driver and supplied to the (n + 1) th gate line GLn + The transistor is turned on. The second data voltage VD2 output from the data driver and supplied to the first data line is turned on on the (n + 1) -th gate line GLn + 1, And charged to two pixel electrodes.

The first and second data voltages VD1 and VD2 have the same positive polarity and the same luminance. Accordingly, the first data voltage VD1 having the same polarity is charged to the first pixel electrode on the nth gate line GLn, and the second data voltage VD2 having the same polarity is supplied to the (n + 1) th gate line GLn +1) on the first pixel electrode.

Similarly, in this manner, the third data voltage VD3 is charged to the third pixel electrode on the (n + 2) -th gate line GLn + 2 and the third data voltage VD3 is applied to the fourth pixel And the fourth data voltage VD4 is charged to the electrode. The third and fourth data voltages VD3 and VD4 have the same positive polarity and the same luminance.

A time gap is required between each of the data voltages VD1 to VD4 to individually supply the respective data voltages VD1 to VD4 to the first data line. It is the SOE signal that creates this gap. The SOE signal has a high level between the data voltages VD1 and VD2 supplied in time and the data driver does not supply any data voltage to the first data line of the liquid crystal panel by such a high level width. Accordingly, the first and second data voltages VD1 and VD2, the second and third data voltages VD2 and VD3, and the third and fourth data voltages VD3 and VD4, No voltage is present between them.

The width of each high level in the conventional SOE signal is set to be constant.

In this case, the first pixel electrode is charged with the first data voltage VD1, and no data voltage is supplied from the data driver during the high level of the SOE signal. do. However, the first data voltage VD1 applied to the first pixel electrode is present on the first data line and gradually discharged during the high level of the SOE signal. Nevertheless, since the width of the high level of the SOE signal is very narrow, the first data voltage VD1 existing on the first data line is not completely discharged.

In this situation, when the second data voltage VD2 having the same polarity as the first data voltage VD1 is supplied to the first data line in the data driver, the first data voltage VD2, The second data voltage VD2 is combined with the first data voltage VD1 that is not fully discharged and the second pixel electrode is charged with a higher voltage than the first pixel electrode VD1. Therefore, the second pixel electrode of the (n + 1) -th gate line GLn + 1 is more charged than the charge of the first pixel electrode of the n-th gate line GLn, The amount of charge of the battery is increased. Since the charged amount determines the luminance, the charged amount charged in the second pixel electrode is greater than the charged amount in the first pixel electrode, so that a lower luminance is obtained in the second pixel electrode than in the first pixel electrode. In other words, lower brightness is obtained at the second pixel electrode than at the first pixel electrode.

Therefore, even though the first and second data voltages having the same luminance are supplied to the liquid crystal panel by the data driver, the first data voltage VD1 is applied to the first pixel electrode of the nth gate line GLn The luminance of the second pixel electrode of the (n + 1) -th gate line GLn + 1 to which the second data voltage VD2 is applied is higher than the luminance of the pixel electrode of the The pixel electrodes on the line become darker, resulting in line defects including bad defects or bad defects, resulting in deterioration of image quality.

Similarly, the third pixel electrode on the (n + 2) -th gate line GLn + 2 and the fourth pixel on the (n + 3) -th gate line GLn + 3 on which the third and fourth data voltages VD3 and VD4 are respectively applied, A luminance difference is generated between the electrodes, and the image quality is deteriorated due to the poor line property.

The present invention relatively reduces the width of the second data voltage having the same polarity as the first data voltage due to the relatively high level of the SOE signal having a relatively wide width, And to improve the image quality by preventing line defects and a method of driving the liquid crystal display device.

According to an embodiment of the present invention, a method of driving a liquid crystal display device having a liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged includes a plurality of positive and negative polarities Generating data voltages; And supplying each of the data voltages to dots on each of the gate lines, wherein a first supply delay period is located between adjacent data voltages having different polarities, and adjacent data voltages having the same polarity And the first and second supply delay sections have different intervals from each other.

According to another embodiment of the present invention, there is provided a method of driving a liquid crystal display having a liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged, ≪ / RTI > Generating a plurality of positive and negative data voltages; And supplying the respective data voltages to dots on each of the gate lines in accordance with the first and second SOE signals, wherein supply of the latter data voltage among adjacent data voltages having different polarities 1 SOE signal, and the supply of the latter data voltage among adjacent data voltages having the same polarity is controlled by the second SOE signal.

According to another embodiment of the present invention, a liquid crystal display includes: a liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged; Supplying a scan signal for driving the liquid crystal panel; And a data driver for supplying a plurality of positive and negative data voltages to the dots on each of the gate lines of the liquid crystal panel, wherein a first supply delay period is located between adjacent data voltages having different polarities, A second supply delay period is located between adjacent data voltages having the same polarity, and the first and second supply delay periods have different intervals from each other.

According to the present invention, since the data voltage of the same polarity is charged more than the data voltage of the former among the data of the same polarity, the present invention can prevent the line defect such as the bad or odd defect, have.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a view showing a liquid crystal panel according to the present invention. Referring to FIG. 3, the liquid crystal panel 10 includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first and second substrates. The liquid crystal layer includes a plurality of liquid crystal molecules. Each of the liquid crystal molecules is displaced by an electric field between the first and second substrates, and the transmittance of light is adjusted according to the amount of displacement to display an image.

The first substrate includes a plurality of gate lines GLn to GLn + 3 and a plurality of data lines DL. A plurality of dots are defined by the gate lines GLn to GLn + 3 and the data lines DL. Thus, the dots are arranged in a matrix on the first substrate. Each of the dots has the same meaning as a commonly used pixel region. Each of the dots may be any one of red dots, green dots, and blue dots, or any one of red dots, green dots, blue dots, and white dots. Typically, a pixel includes red dots, green dots, and blue dots, or may include red dots, green dots, blue dots, and white dots. A full color image can be displayed by the unit pixel thus defined. A plurality of thin film transistors 11 to 14 are disposed at intersections of the gate lines GLn to GLn + 3 and the data lines DL. The thin film transistors 11 to 14 are electrically connected to the gate lines GLn to GLn + 3 and the data lines DL. The pixel electrodes 15 to 18 are electrically connected to the thin film transistors 11 to 14. Accordingly, the dot includes one gate line, one data line, one thin film transistor, and one pixel electrode. In addition, if necessary, each dot may include at least one gate line, at least one data line, at least one thin film transistor, and at least one pixel electrode. A storage capacitor Cst may be formed in the pixel electrodes 15 to 19. [ The storage capacitor Cst may be formed by overlapping the pixel electrodes 15 to 19 and the gate line of the previous stage. This structure is called a SOC (Storage On Common) structure. The storage capacitor Cst may be formed by overlapping storage lines arranged in parallel with the pixel electrodes 15 to 18 and the gate lines GLn to GLn + 3. This structure is called a storage on gate (SOG) structure.

The thin film transistors 11 to 14 are turned on by the gate high voltage supplied to each of the gate lines GLn to GLn + 3, and the thin film transistors 11 to 14 are turned off by the gate low voltage. The scan signal includes the gate high voltage and the gate low voltage. A gate high voltage is supplied to each of the gate lines GLn to GLn + 3 in units of one horizontal period (1 H) in one frame, and the gate low voltage is supplied during the remaining period except for one horizontal period And supplied to the gate lines GLn to GLn + 3. The gate high voltage may be sequentially supplied to each of the gate lines GLn to GLn + 3. If necessary, a gate high voltage may be supplied to each of the gate lines GLn to GLn + 3 to overlap with each other. Alternatively, a gate high voltage may be supplied in units of the two gate lines, i.e., in units of two horizontal periods (2 H). A gate in panel structure is a structure in which a gate driver is formed on the liquid crystal panel by a semiconductor process. In such a gate-in-panel structure, a gate high voltage of a sufficient magnitude is difficult to be output from the gate driver due to the characteristic deterioration of the switching transistor incorporated in the gate driver formed on the liquid crystal panel. In such a gate-in-panel structure, a gate high voltage having a width of 2 horizontal intervals (2 H) is generated to prevent the output of the gate high signal from being degraded. Thus, the gate high voltage is outputted from the gate driver for two horizontal periods (2 H), so that the gate high voltage supplied to each gate line can have a sufficient size. Accordingly, it is possible to prevent the operation failure of the thin film transistor of the liquid crystal panel due to the output drop of the gate high voltage, thereby improving the quality.

A data voltage may be supplied to each of the data lines DL in units of one horizontal period (1 H). In order to prevent a driving error caused by deterioration of the liquid crystal molecules of the liquid crystal layer, a data voltage is supplied to each data line DL in an inversion manner. In this embodiment, the data voltages driven in the inversion mode are supplied with the same polarity in units of two gate lines, and the polarity can be inverted in units of two gate lines. The data voltage includes a positive data voltage and a negative data voltage. The positive polarity data voltage is at least higher than the common voltage (to be described later), and the negative polarity data voltage is at least lower than the common voltage. Therefore, the common voltage may be a reference voltage for distinguishing between the positive data voltage and the negative data voltage.

For example, a method of supplying a data voltage to the liquid crystal panel 10 will be described. For convenience of explanation, one data line (DL) among the plurality of data lines is described as an example. Further, the two same polarity data voltages may have the same luminance level with each other.

8, a first thin film transistor 11 electrically connected to the nth gate line GLn by a first gate high voltage VGH1 supplied to the nth gate line GLn Turn on. At this time, the first data voltage VD1 of positive polarity is supplied to the data line DL. The first data voltage VD1 is applied to the first pixel electrode 15 electrically connected to the first thin film transistor 11 via the first thin film transistor 11 turned on to be charged.

The second thin film transistor 12 electrically connected to the (n + 1) th gate line GLn + 1 is turned on by the second gate high voltage VGH2 supplied to the (n + 1) th gate line GLn + 1 . At this time, the second data voltage VD2 having the same polarity as the first data voltage VD1 is supplied to the data line DL. The second data voltage VD2 is applied to the second pixel electrode 16 electrically connected to the second thin film transistor 12 through the turned-on second thin film transistor 12 and charged.

The third thin film transistor 13 electrically connected to the (n + 2) th gate line GLn + 2 is turned on by the third gate high voltage VGH3 supplied to the (n + 2) th gate line GLn + 2 . At this time, the third data voltage VD3 having a negative polarity and inverted to the second data voltage VD2 is supplied to the data line DL. The third data voltage VD3 is applied to the third pixel electrode 17 electrically connected to the third thin film transistor 13 through the turned on third thin film transistor 13 to be charged.

The fourth thin film transistor 14 electrically connected to the (n + 3) th gate line GLn + 3 is turned on by the fourth gate high voltage VGH4 supplied to the (n + 3) th gate line GLn + 3 . At this time, the fourth data voltage VD4 having the same polarity as the third data voltage VD3 is supplied to the data line DL. The fourth data voltage VD4 is applied to the fourth pixel electrode 18 electrically connected to the fourth thin film transistor 14 via the fourth thin film transistor 14 turned on to be charged.

As described above, the first and second positive data voltages VD1 and VD2 are applied to the first and second pixel electrodes 15 and 16 on the nth and (n + 1) th gate lines GLn and GLn + 1 The third and fourth data voltages VD3 and VD4 of negative polarity are applied to the third and fourth pixel electrodes 17 and 18 on the (n + 1) th, (n + Can be applied. Of course, the pixel electrode on the (n-1) th gate line GLn-1 in the previous stage of the nth gate line GLn is applied with the negative polarity data voltage which is inverted to the positive first data voltage VD1 .

In the present embodiment, the second supply delay period defined by the data voltages of the same polarity, that is, between the first and second data voltages VD1 and VD2 or between the third and fourth data voltages VD3 and VD4 (Td2) is set to have a width relatively larger than a first supply delay period (Td1) defined by data voltages of different polarities, i.e., between the second and third data voltages (VD2, VD3) . Here, the supply delay periods Td1 and Td2 denote the times when the data voltages are not supplied to the data lines.

The second supply delay period Td2 may range from 2 to 5 times the first supply delay period Td1. The ratio of the relative widths of the first and second supply delay periods Td1 and Td2 is equal to the sum of the widths of the first and second data voltages VD1 and VD2 or the third and fourth data voltages VD3 And VD4 can be designed so that the former data voltage and the latter data voltage are charged to the respective pixel electrodes 15 through 18 at the same charge amount. The data voltage of the former may be the first and third data voltages VD1 and VD3 and the latter data voltage may be the second and fourth data voltages VD2 and VD4. In other words, the ratio of the relative widths of the first and second supply delay periods Td1 and Td2 may be adjusted so that the same amount of charge is applied to each of the pixel electrodes 15 to 18.

In this embodiment, the entire widths of the data voltages VD1 and VD2, VD3 and VD4 of the same polarity can be set to be equal to each other. That is, the total width of the first and second data voltages VD1 and VD2 and the total width of the third and fourth data voltages VD3 and VD4 may be set to be equal to each other. The width of the data voltages VD2 and VD4 of the former data voltages VD1 and VD3 is set to the width of the former data voltages VD1 and VD3 among the data voltages VD1 and VD2 and VD3 and VD4 of the same polarity by the second supply delay period Td2. The width can be set to be relatively narrow. For example, the width of the former data voltages VD1 and VD3 is set to be the same as the conventional one, but the width of the latter data voltages VD2 and VD4 by the second supply delay period Td2 is set to the data Can be set to be relatively narrow in comparison with the widths of the voltages VD1 and VD3. Therefore, after the former data voltages VD1 and VD3 are charged, the data voltages VD1 and VD3 of the electrons supplied to the data line DL during the second supply delay period Td2 are discharged. At this time, since the second supply delay period Td2 is set to a sufficiently wide width, the former data voltages VD1 and VD3 can be almost completely discharged. After the first supply delay period, the latter data voltages VD2, VD4 are charged through the data line DL. The former data voltages VD1 and VD3 do not exist in the data line DL so that the latter data voltages VD2 and VD4 are charged with the same charge amount as the former data voltages VD1 and VD3. Therefore, since the former data voltages VD1 and VD3 and the latter data voltages VD2 and V4 are charged at the same charge amount, it is possible to prevent a line defect such as a bad defect or an odd defect, Can be improved.

4 is a block diagram showing a liquid crystal display device having the liquid crystal panel of FIG. 2 and 8, the liquid crystal display 20 includes a liquid crystal panel 10, a timing controller 30, a gate driver 40, and a data driver 50.

Since the liquid crystal panel 10 has been described in detail above, further explanation is omitted.

The timing controller 30 receives vertical / horizontal synchronizing signals (Vsync, Hsync) and video data signals from an external device such as a video card. The video data signal is supplied from the video card to the timing controller (10). The timing controller 10 extracts red, green, and blue data signals or red, green, blue, and white data from the video data signal and arranges them in units of one frame. Then, the timing controller 10 outputs data signals of one frame to the data driver 50 ). The timing controller 30 generates a first control signal (GSP, GSC, GOE, etc.) for driving the gate driver 40 using the vertical / horizontal synchronizing signals Vsync and Hsync, And generates second control signals (SSP, SSC, SOE, POL, etc.) for driving the driver (50). The first control signal generated by the timing controller 30 is supplied to the gate driver 40, and the second control signal is supplied to the data driver 50.

The gate driver 40 sequentially generates the gate high voltages VGH1 to VGH4 using the first control signals GSP, GSC, GOE, and the like. The gate high voltages VGH1 to VGH4 are sequentially supplied to the gate lines GLn to GLn + 3 of the liquid crystal panel 10, respectively. The gate high voltages VGH1 to VGH4 supplied to the respective gate lines GLn to GLn + 3 of the liquid crystal panel 10 are not overlapped with each other between the gate high voltages VGH1 to VGH4 There may be a controlled gap. The gate high voltages VGH1 to VGH4 may be generated to overlap each other. In addition, each of the gate high voltages VGH1 to VGH4 may be generated to have a width of 2 horizontal periods (2 H). In this case, a gate high voltage generated during two horizontal periods (2 H) may be supplied to the liquid crystal panel 10. In the case where a gate driver is embedded on a liquid crystal panel as in a gate-in panel structure, a gate high voltage of a sufficient magnitude is difficult to output from the gate driver due to a characteristic deterioration of the switching transistor included in the gate driver. In such a gate-in-panel structure, a gate high voltage having a width of 2 horizontal intervals (2 H) is generated to prevent the output of the gate high signal from being degraded. Thus, the gate high voltage is outputted from the gate driver for two horizontal periods (2 H), so that the gate high voltage supplied to each gate line can have a sufficient size. Accordingly, it is possible to prevent the operation failure of the thin film transistor of the liquid crystal panel due to the output drop of the gate high voltage, thereby improving the quality.

Gate high voltages having a width of two horizontal periods (2 H) may be generated so as to overlap each other for at least one horizontal period (1 H). Therefore, two gate lines, e.g., the first and second gate lines, are simultaneously supplied with a gate high voltage for at least one horizontal period (1H) between each gate line. In such a case, the thin film transistors electrically connected to the first and second gate lines, for example, the first and second thin film transistors, may apply a gate high voltage at a gate high voltage having a width of 2 horizontal periods (2 H) (1 H), it can be turned on by the gate high voltage corresponding to the width of the latter. The gate of the thin film transistor is charged with the voltage of the threshold voltage level of the thin film transistor by the gate high voltage corresponding to the width of the electron and the voltage of the latter higher than the threshold voltage level of the thin film transistor is applied to the gate of the thin film transistor So that the thin film transistor is turned on.

The data driver 50 receives the red, green, and blue data signals or the red, green, blue, and white data and the second control signals SSP, SSC, SOE, and POL from the timing controller 30 .

5 is a block diagram showing a data driver in the liquid crystal display of FIG. 5, the data driver 50 includes a shift register 62, a latch unit 64, a digital analog converter (DAC) 66, a buffer unit 68, and an SOE signal control unit 60 .

The shift register 62 sequentially supplies a sampling signal to the latch unit 64 using the SSC and the SSP supplied from the timing controller 30.

The latch unit 64 sequentially latches the red, green, and blue data signals or the red, green, blue, and white data signals in response to the sampling signal supplied from the shift register 62, To the digital-to-analog converter (66).

The digital-to-analog converter 66 determines the polarity of each data signal based on the respective data signals supplied from the latch unit 64, selects two gamma voltages close to each data signal based on the determined polarity, , And converts the data signal into an analog data voltage corresponding to the data signal using the selected two gamma voltages.

The gamma voltage may be generated in a gamma voltage generator (not shown). The gamma voltage generator sets a middle voltage of a ground voltage to a maximum voltage (or a power supply voltage) as a reference voltage, connects a plurality of resistors in series between the ground voltage and the reference voltage, And a resistor string (R-string) that connects a plurality of resistors in series between the resistors and generates a plurality of gamma voltages having different levels from each other by voltage distribution from nodes between the resistors. The plurality of gamma voltages generated between the ground voltage and the reference voltage may be a negative gamma voltage, and the plurality of gamma voltages generated between the reference voltage and the maximum voltage may be a positive gamma voltage.

The digital-to-analog converter 66 can determine the polarity of each data signal using the POL. The digital-to-analog converter 66 selects two gamma voltages (positive gamma voltage or negative gamma voltage) close to each data signal based on the determined polarity. Since the gamma voltage is much smaller than the number of gradations (0 to 255 gradations) of each data signal, the number of gamma voltages generated by the gamma voltage generator can not coincide with the number of gradations of each data signal. Accordingly, an analog data voltage corresponding to the data signal may be calculated between the selected two gamma voltages.

The analog data voltage converted in the digital-to-analog converter 66 may be a data voltage having a polarity because it is generated from the gamma voltage according to the polarity determined by the POL.

The data voltage having the polarity is supplied to the buffer unit 68 to store data voltages that can be supplied to all the pixel regions on the gate line, that is, one line of data voltages, and collectively, May be supplied to the respective data lines of the panel (10).

The data voltages for one line can be supplied to the respective data lines of the liquid crystal panel 10 in units of one horizontal period (1 H).

According to the present invention, the supply time point of one line of data voltages supplied in units of one horizontal period (1 H) is different depending on whether the data voltage currently supplied has the same polarity as the previously supplied data voltage or has a different polarity do.

The supply timing of the data voltages for one line may be determined by the first SOE signal SOE1 and the second SOE signal SOE2 supplied from the SOE signal controller 60. [

FIG. 6 is a block diagram illustrating a SOE signal controller according to a first embodiment of the data driver of FIG. 5;

Referring to FIG. 6, the SOE signal controller 60 includes an SOE signal modulator 72 and a switch 74.

The SOE signal modulator 72 modulates the SOE to generate a first SOE signal and a second SOE signal. The first SOE signal includes data having a different polarity from each other, for example, a second data voltage VD2 of positive polarity applied to the second pixel electrode 16 of FIG. 3 and a second data voltage VD2 applied to the third pixel electrode 17. [ And the interval between the third data voltages VD3 of the polarity, that is, the first supply delay period Td1. The second SOE signal is applied to data having the same polarity, for example, a first data voltage VD1 of positive polarity applied to the first pixel electrode 15 of FIG. 3 and a first data voltage VD1 applied to the second pixel electrode 16, The third data voltage VD3 of the negative polarity applied to the third pixel electrode 17 and the fourth data voltage VD4 of the negative polarity applied to the fourth pixel electrode 18, I.e., the second supply delay period Td2. Therefore, the high-level width of the first SOE signal is equal to the first supply delay period Td1, and the high-level width of the second SOE signal may be equal to the second supply delay period Td2 have.

The SOE signal may have a high level of a predetermined width. The width of the high level of the SOE signal may vary according to the resolution of the liquid crystal panel 10. Normally, the liquid crystal panel is driven at 60 Hz. That is, the liquid crystal panel displays data of one frame on the liquid crystal panel at 60 Hz. Accordingly, when the resolution of the liquid crystal panel is increased, the number of dots to be displayed on the liquid crystal panel increases, which means an increase in the gate line and the data line. Therefore, in order to supply one frame of data to the gate line and the data line, which are further increased to a fixed frequency of 60 Hz, the interval between the signals supplied to each gate line and each data line must be narrowed. Accordingly, as the resolution of the liquid crystal panel 10 increases, the width of the high level of the SOE signal becomes narrower. As the resolution of the liquid crystal panel 10 becomes lower, the width of the high level of the SOE signal becomes wider .

The first SOE signal may be used as it is. That is, the first SOE signal may have the same high level width as the SOE signal.

The second SOE signal may have a width of a high level expanded to a range of 2 to 5 times the width of the high level of the SOE signal using the SOE signal.

The switch 74 selects any one of the first and second SOE signals supplied from the SOE signal modulating unit 72 according to the SOE control signal and outputs the selected signal to the buffer unit 68 of the data driver 50. [ . The buffer unit 68 may supply the positive polarity data voltage or the negative polarity data voltage to the liquid crystal panel 10 according to the first SOE signal or the second SOE signal.

Accordingly, the SOE signal controller 60 can supply the first SOE signal and the second SOE signal to the buffer unit 68 alternately.

7 is a block diagram illustrating a second embodiment of the SOE signal controller in the data driver of FIG.

Referring to FIG. 7, the SOE signal controller 60 includes an SOE signal modulator 72 and a multiplexer 84. Since the SOE signal modulating unit 72 has already been described with reference to FIG. 6, further description is omitted.

The multiplexer 84 selects any one of the first and second SOE signals supplied from the SOE signal modulator 72 according to the SOE control signal and outputs the selected signal to the buffer unit 68 of the data driver 50. [ . The buffer unit 68 may supply the positive polarity data voltage or the negative polarity data voltage to the liquid crystal panel 10 according to the first SOE signal or the second SOE signal.

3 and 8, after the data voltage of negative polarity is supplied to the liquid crystal panel 10, the SOE signal controller 60 supplies the first SOE signal to the buffer unit (not shown) of the data driver 50 68). The buffer unit 68 outputs the positive first data voltage VD1 supplied from the digital-to-analog converter 66 to the liquid crystal panel 10 ). The first data voltage VD1 supplied to the liquid crystal panel 10 is applied to the first pixel electrode 15 via the data line DL and the first thin film transistor 11.

The SOE signal controller 60 supplies the second SOE signal to the buffer unit 68 of the data driver 50. The buffer unit 68 outputs the second data voltage VD2 of positive polarity supplied from the digital-analog converter 66 to the liquid crystal panel 70 after the second supply delay time Td2 has elapsed in accordance with the second SOE signal. (10). The second data voltage VD2 supplied to the liquid crystal panel 10 is applied to the second pixel electrode 16 via the data line DL and the second thin film transistor 12.

The second supply delay period Td2 is set to a sufficient period to sufficiently discharge any data voltage remaining in the data line DL so that the second supply delay period Td2 is maintained at the data line DL during the second supply delay period Td2, The first data voltage VD1 can be completely discharged. The second data voltage VD2 supplied to the data line DL and applied to the second pixel electrode 16 after the second supply delay time Td2 passes the first data line DL is supplied to the data line DL, The second data voltage VD2 applied to the second pixel electrode 16 is supplied to the data line DL in a state that the voltage VD1 is completely discharged to the second data voltage VD2 The first pixel electrode 15 has the same charge amount as the first data voltage VD1 charged.

The SOE signal controller 60 supplies the first SOE signal to the buffer unit 68 of the data driver 50. The buffer unit 68 supplies the third data voltage VD3 of the negative polarity supplied from the digital-analog converter 66 to the liquid crystal panel 70 after the first supply delay period Td1 has elapsed in accordance with the first SOE signal. (10). The third data voltage VD3 supplied to the liquid crystal panel 10 is applied to the third pixel electrode 17 via the data line DL and the third thin film transistor 13.

The SOE signal controller 60 supplies the second SOE signal to the buffer unit 68 of the data driver 50. The buffer 68 stores the fourth data voltage VD4 of the negative polarity supplied from the digital-to-analog converter 66 in accordance with the second SOE signal after the second supply delay period Td2, To the panel (10). The fourth data voltage VD4 supplied to the liquid crystal panel 10 is applied to the fourth pixel electrode 18 via the data line DL and the fourth thin film transistor 14.

The second supply delay period Td2 is set to a sufficient period to sufficiently discharge any data voltage remaining in the data line DL so that the second supply delay period Td2 is maintained at the data line DL during the second supply delay period Td2, The third data voltage VD3 can be completely discharged. Accordingly, the fourth data voltage VD4 supplied to the data line DL and applied to the fourth pixel electrode 18 after the second supply delay time Td2 elapses is transferred from the data line DL to the third data The fourth data voltage VD4 applied to the fourth pixel electrode 18 is supplied to the data line DL in a state that the voltage VD3 is completely discharged, The third pixel electrode 17 has the same charge amount as that of the third data voltage VD3.

Accordingly, in this embodiment, the first data voltage VD1 of the positive polarity charged in the first pixel electrode 15 on the first gate line GLn and the second data voltage VD1 on the second gate line GLn + The second data voltage VD2 of the positive polarity charged in the first and second data lines 16 and 16 has the same charge amount, thereby preventing a line defect such as a bad defect or an odd defect, thereby improving the image quality. Likewise, this embodiment is different from the third embodiment in that the third data voltage VD3 of the negative polarity charged in the third pixel electrode 17 on the third gate line GLn + 2 and the fourth data voltage VD3 on the fourth gate line GLn + Since the negative fourth data voltage VD4 charged in the electrode 18 has the same charge amount, it is possible to prevent the line defect such as the bad defect or the bad defect and improve the image quality.

1 is a view for explaining a general vertical 2-dot method;

2 is a waveform diagram for the vertical 2-dot scheme of FIG.

3 is a view showing a liquid crystal panel according to the present invention.

FIG. 4 is a block diagram showing a liquid crystal display device including the liquid crystal panel of FIG. 3;

5 is a block diagram showing a data driver in the liquid crystal display device of FIG.

FIG. 6 is a block diagram showing the SOE signal control unit according to the first embodiment in the data driver of FIG. 5;

FIG. 7 is a block diagram illustrating a second embodiment of the SOE signal control unit in the data driver of FIG. 5;

8 is a waveform diagram for driving the liquid crystal panel of Fig. 3;

Description of the Related Art

10: liquid crystal panels 11 to 14: thin film transistors

15 to 18: pixel electrode 20: liquid crystal display

30: timing controller 40: gate driver

50: Data driver 60: SOE signal control section

62: shift register 64: latch portion

66: digital-to-analog converter 68: buffer unit

72: SOE signal modulating section 74: switch

84: Multiplexer

Claims (20)

1. A liquid crystal display comprising a liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged, Generating a plurality of positive and negative data voltages; And And supplying each of the data voltages to dots on each of the gate lines, A first supply delay period is located between adjacent data voltages having different polarities, a second supply delay period is located between adjacent data voltages having the same polarity, and the first and second supply delay periods are different from each other And is formed so as to have an interval, Wherein the second supply delay section has an interval in the range of 2 to 5 times the first supply delay section and the second supply delay section is a section for completely discharging the remaining data voltage. A method of driving a device. 2. The method of claim 1, wherein the adjacent data voltages having the different polarity and the adjacent data voltages having the same polarity are supplied for the same time. 2. The method of claim 1, wherein the second data voltage of the adjacent data voltages having different polarities is supplied after the first supply delay period. 2. The method of claim 1, wherein the second data voltage among the adjacent data voltages having the same polarity is supplied after the second supply delay period. delete 1. A liquid crystal display comprising a liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged, Generating first and second SOE signals; Generating a plurality of positive and negative data voltages; And And supplying each of the data voltages to dots on each of the gate lines in accordance with the first and second SOE signals, The supply of the latter data voltage among the adjacent data voltages having different polarities is controlled by the first SOE signal and the supply of the latter data voltage among the adjacent data voltages having the same polarity is applied to the second SOE signal Lt; / RTI > Wherein the second SOE signal has a high level width in a range of 2 to 5 times that of the first SOE signal and the second SOE signal is a signal for completely discharging the remaining data voltage. A method of driving a device. 7. The method of claim 6, wherein adjacent data voltages having the same polarity and adjacent data voltages having the same polarity are supplied for the same time. 7. The method as claimed in claim 6, wherein the latter data voltage among the adjacent data voltages having different polarities is supplied after a high level of the first SOE signal. 7. The method of claim 6, wherein the second data voltage among the adjacent data voltages having the same polarity is supplied after a high level of the second SOE signal. delete A liquid crystal panel in which a plurality of dots defined by a plurality of gate lines and a plurality of data lines are arranged; Supplying a scan signal for driving the liquid crystal panel; And And a data driver for supplying a plurality of positive and negative data voltages to the dots on each of the gate lines of the liquid crystal panel, A first supply delay period is located between adjacent data voltages having different polarities, a second supply delay period is located between adjacent data voltages having the same polarity, and the first and second supply delay periods are different from each other And is formed so as to have an interval, Wherein the second supply delay section has an interval in the range of 2 to 5 times the first supply delay section and the second supply delay section is a section for completely discharging the remaining data voltage. Device. 12. The data driver of claim 11, wherein the data driver comprises an SOE signal controller for supplying first and second SOE signals, The supply of the latter data voltage among adjacent data voltages having different polarities is controlled by the first SOE signal, and supply of the latter data voltage among adjacent data voltages having the same polarity is controlled by the second SOE Wherein the control signal is controlled by a signal. 13. The apparatus of claim 12, wherein the SOE signal controller comprises: An SOE signal modulator for generating the first and second SOE signals from the SOE signal; And And selecting means for selecting any one of the first and second SOE signals. 14. The liquid crystal display device according to claim 13, wherein the selecting means is any one of a switch and a multiplexer. 13. The liquid crystal display of claim 12, wherein the latter data voltage among adjacent data voltages having different polarities is supplied after a high level of the first SOE signal. 13. The liquid crystal display of claim 12, wherein the latter data voltage among the adjacent data voltages having the same polarity is supplied after a high level of the second SOE signal. 13. The liquid crystal display of claim 12, wherein the second SOE signal has a high level width ranging from 2 to 5 times that of the first SOE signal. 12. The liquid crystal display of claim 11, wherein the adjacent data voltages having the different polarity and the adjacent data voltages having the same polarity are supplied for the same time. delete delete

Images