KR20080062454A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to prevent luminance difference between odd and even horizontal lines by compensating for charge amount difference between vertically adjacent pixel electrodes. An LCD(Liquid Crystal Display) device includes an LCD panel(102), and gate and data drivers(106,104). The gate driver drives gate lines of the LCD panel. The data driver responds at a first source output enable signal during a horizontal period when the polarity of pixel voltage signal in a previous horizontal period is inverted, responds at a second source output enable signal having a high logical period different from the first source output enable signal during a horizontal period having the same polarity of pixel voltage signal as the previous horizontal period, and supplies the pixel voltage signal to data lines of the LCD panel. At least one of the first and second source output enable signals is varied according to a frame frequency.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

FIG. 1 is a view illustrating polarities of pixel voltage signals charged in a 2-dot inversion method in a conventional liquid crystal panel for each liquid crystal cell.

FIG. 2 is a charging characteristic diagram of pixel voltage signals of liquid crystal cells of the N−1 th to N + 2 th lines shown in FIG. 1.

3 is a block diagram illustrating a liquid crystal display according to the present invention.

FIG. 4 is a detailed block diagram illustrating the source output enable signal generator illustrated in FIG. 3.

FIG. 5 is a driving waveform diagram of the liquid crystal display shown in FIG. 3.

<Explanation of symbols for main parts of drawing>

102 liquid crystal display panel 104 data driver

106: gate driver 108: timing controller

110: source output enable generation unit 112: counter

114: logical sum operation unit 116: input frequency detection unit

118: external clock signal generation unit

120: first source output enable generation unit

122,124,132,134,142,144

126,136,146: logical product operation unit 128: frequency comparator

130: second source output enable generator 138: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display and a driving method thereof capable of preventing a horizontal line phenomenon caused by vertical 2-dot inversion driving.

A liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

Meanwhile, the liquid crystal display uses an inversion driving method that periodically inverts the polarity of the voltage charged in the liquid crystal cell in order to prevent degradation of the liquid crystal and to improve image quality. In particular, the liquid crystal display device provides a higher image quality than other inversion methods, but uses a vertical 2-dot inversion driving method to compensate for the dot inversion method, which consumes more power and causes flicker in a specific pattern. However, the vertical 2-dot inversion driving method has a problem in that a horizontal line problem occurs due to a luminance difference. 1 and 2, the problem of the vertical two-dot inversion driving method is described in detail as follows.

FIG. 1 illustrates polarities of liquid crystal cells driven by a vertical 2-dot inversion method.

The vertical 2-dot inversion method drives the liquid crystal cell such that the polarity of the liquid crystal cell is inverted by 2 dots in the vertical direction and inverted by dots in the horizontal direction. In other words, in the vertical two-dot inversion method, as shown in FIG. 1, the N−1 th horizontal line is driven such that adjacent liquid crystal cells in the horizontal direction have opposite polarities, and the N th horizontal line is the N−1 th horizontal line. It is driven to have the same polarity as the liquid crystal cell of. The N + 1th horizontal line is driven to have a polarity opposite to the liquid crystal cell of the Nth horizontal line, and the N + 2th horizontal line is driven to have the same polarity as the liquid crystal cell of the N + 1th horizontal line.

While the vertical two-dot inversion method can solve the flicker problem of the dot inversion method, there is a problem in that horizontal lines are generated due to luminance differences between horizontal lines. Specifically, as illustrated in FIG. 2, the N−1 th to N + 2 th horizontal lines are driven in response to the horizontal synchronization signal Hsync. The positive data signal, which is charged through the data line in the low section of the source output enable (SOE) signal when the N-1th horizontal line is driven, has the same polarity as that of the previous horizontal line, so that the rising time On the other hand, the positive data signal of the Nth horizontal line has the same polarity as the data signal of the N−1th horizontal line and thus has no rising time or a shorter rising time. The negative data signal charged to the N + 1th horizontal line is opposite in polarity to the N-1th horizontal line, resulting in a long falling time, whereas the negative data signal charged to the N + 2th horizontal line is negative. The polarity (-) data signal has the same polarity as the N + 1th horizontal line and thus has no or short polling time.

As a result, the N-1 and N + 1th horizontal lines whose polarities are inverted from the previous horizontal lines, that is, the Nth and N + 2th horizontal lines having the same amount of data charges as the previous lines, That is, it becomes smaller than the data filling amount of the even horizontal line. As a result, in the case of the normal white mode, as shown in FIG. 1, a horizontal line phenomenon in which an odd horizontal line is brighter than an even horizontal line occurs, thereby deteriorating image quality.

Accordingly, an aspect of the present invention is to provide a liquid crystal display and a driving method thereof capable of preventing a horizontal line phenomenon caused by vertical two-dot inversion driving.

In order to achieve the above technical problem, the liquid crystal display device according to the present invention includes a liquid crystal display panel; A gate driver driving the gate line of the liquid crystal display panel; The first source output enable signal is responsive to a first source output enable signal in a horizontal period in which a polarity of a previous horizontal period and a pixel voltage signal are inverted, and the first source output enable signal is in a horizontal period in which the polarity of the previous horizontal period and a pixel voltage signal are the same. A data driver configured to supply the pixel voltage signal to a data line of the liquid crystal display panel in response to a second source output enable signal having a different high logic period, wherein at least one of the first and second source output enable signals is provided; One is characterized in that it varies according to the frame frequency.

In order to achieve the above technical problem, the driving method of the liquid crystal display according to the present invention includes a horizontal period in which the polarity of the previous horizontal period and the pixel voltage signal are reversed, and a horizontal period in which the polarity of the previous horizontal period and the pixel voltage signal are the same. Generating first and second source output enable signals having different high logic periods; Generating a pixel voltage signal so that the polarity of the input pixel data is inverted by 2 dots in a vertical direction; Supplying the pixel voltage signal to liquid crystal cells in a low logic period of the first and second source output enable signals, wherein at least one of the first and second source output enable signals is a frame frequency. It is characterized by varying according to.

Other technical problems and features of the present invention in addition to the above technical problem will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5.

3 is a block diagram illustrating a liquid crystal display according to the present invention.

3 includes a liquid crystal display panel 102, a gate driver 106 for driving a gate line GL of the liquid crystal display panel 102; A data driver 104 for driving the data line DL of the liquid crystal display panel 102 and a timing controller 108 for controlling the gate driver 106 and the data driver 104 are provided.

The liquid crystal display panel 102 includes a plurality of liquid crystal cells Clc disposed in a matrix at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each of the thin film transistors TFT formed in the liquid crystal cell Clc supplies a pixel voltage signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. .

The gate driver 106 sequentially supplies the scan signals to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 108. Accordingly, the gate driver 106 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

The data driver 104 converts the digital pixel data R, G, and B into analog pixel voltage signals in response to the data control signal DCS from the timing controller 108 to the gate line GL. The pixel voltage signal of one horizontal line is supplied to the data lines DL1 through DLm every time the gate high voltage of the scan signal is supplied. In this case, the data driver 104 converts the data driver 104 into an analog data signal using a gamma voltage from a gamma voltage generator (not shown). In particular, the data driver 104 converts the positive and negative pixel voltage signals in response to the polarity control signal POL. For example, the data driver 104 causes the pixel voltage signal to be polarized in a vertical two-dot inversion scheme in response to the polarity control signal POL inverted in two horizontal periods.

The timing controller 108 rearranges the digital pixel data R, G, and B input from the graphic controller (not shown) of the system to be suitable for driving the data driver 104 and supplies the data to the data driver 104. do. The timing controller 108 may further include a gate for controlling the gate driver 106 using a reference clock signal CLK, a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and the like. A control signal GCS and a data control signal DCS for controlling the data driver 104 are generated. In particular, the timing controller 108 includes a source enable signal generator 110 for generating first and second source output enable signals SOE1 and SOE2.

As shown in FIG. 4, the source output enable signal generator 110 includes a counter 112, first and second source output enable signal generators 120 and 130, an input frequency detector 116, and an AND operation unit 114. ).

The counter 112 counts the reference clock signal CLK during the high logic period of the data enable signal DE and is initialized during the low logic period of the data enable signal DE. Specifically, the counter 112 counts the reference clock signal CLK during the odd horizontal periods H1, H3, ..., and outputs the counted first counting signal CS1. The counter 112 counts the reference clock signal CLK during the even-numbered horizontal periods H2, H4, ..., and outputs the counted second counting signal CS2.

The first source enable signal generator 120 generates a first source enable signal SOE1 supplied to the data driver 104 during the odd horizontal periods H1, H3,... To this end, the first source enable signal generator 120 includes a first rising comparator 122, a first falling comparator 124, and a first AND product 126.

The first rising comparator 122 compares the first rising signal RS1 and the first counting signal CS1 which are set in advance to generate a high logic at the same time that the first rising signal RS1 and the first counting signal CS1 are equal to each other. Generates a first comparison signal (HC1).

The first falling comparator 124 compares the first falling signal FS1 and the first counting signal CS1 which are set in advance, and the low logic at the time when the first falling signal FS1 is equal to the first counting signal CS1. Generate a first comparison signal LC1 of.

The first AND operation unit 126 performs an AND operation on the first comparison signal HC1 having a high logic and the first comparison signal LC1 having a low logic to perform the first source output enable signal SOE1 shown in FIG. 5. Create

The frame frequency detector 116 includes an external clock signal generator 118 and a frequency comparator 128.

The external clock signal generator 118 generates an external clock signal OCLK that can reduce the deviation from the reference clock signal CLK. The external clock signal generator 118 may be embedded in the timing controller 108 or formed separately from the timing controller 108.

The frequency comparator 128 detects the frame frequency, that is, the frequency of the vertical synchronization signal Vsync, using the external clock signal OCLK, and compares the detected frame frequency Vsync with a preset reference frequency RF. As a result of the comparison, when the frame frequency Vsync is greater than the reference frequency RF, the frequency comparator 128 generates a high logic selection signal SS as shown in FIG. 5, and the frame frequency Vsync is the reference frequency RF. If less than), the frequency comparator 128 generates a selection logic (SS) of low logic.

The second source output enable signal generator 130 generates a second source output enable signal SOE2 supplied to the data driver 104 during the even-th horizontal period H2, H4,... The high logic period HP2 of the second source output enable signal SOE2 is a multiple of A of the high logic period HP1 of the first source output enable signal SOE1 as shown in FIGS. 5 and 1. Will increase.

HP2 = A × HP1

In this case, A has a different value depending on the frame frequency of the liquid crystal display. This is because, as the frame frequency increases, the horizontal line phenomenon becomes more serious due to differences in charging characteristics.

To this end, the second source enable signal generator 130 may use the second and third rising comparators 132 and 142, the second and third falling comparators 134 and 144, and the second and third AND products 136 and 146. Include.

The second rising comparator 132 compares the second rising signal RS2 and the second counting signal CS2 which are preset to correspond to the frame frequency Vsync, and thus the second rising signal RS2 and the second counting signal CS2. At the same time when) is the same, the second comparison signal HC2 of high logic is generated.

The second falling comparator 134 compares the second falling signal FS2 and the second counting signal CS2 which are preset to correspond to the frame frequency Vsync, and thus the second falling signal FS2 and the second counting signal CS2. At the same time, the second comparison signal LC2 of low logic is generated.

The second AND operation unit 136 performs an AND operation on the second comparison signal HC2 of the high logic and the second comparison signal LC2 of the low logic, and thus has a higher logic period than the first source output enable signal SOE1. The long second source output enable signal AND2_SOE2 is generated.

The third rising comparator 142 compares the third rising signal RS3 and the second counting signal CS2 which are preset to correspond to the reference frequency RF, and thus the third rising signal RS3 and the second counting signal CS2. At the same time when 3) is equal, the third comparison signal HC3 having a high logic is generated.

The third falling comparator 144 compares the third falling signal FS3 and the second counting signal CS2 preset to correspond to the reference frequency RF, and thus the third falling signal FS3 and the second counting signal CS2. A third comparison signal LC3 of low logic is generated at the same time that is the same.

The third AND operation unit 146 performs an AND operation on the third comparison signal HC3 having a high logic and the third comparison signal LC3 having a low logic to output a second source output from the second AND operation unit 136. A second source output enable signal AND3_SOE2 different from the enable signal AND2_SOE2 is generated. Here, the second source output enable signal AND3_SOE2 from the third AND operation unit 146 has a higher logic period than the first source output enable signal SOE1, and the second AND output enable signal AND3_SOE2 is longer from the second AND operation unit 136. It has a high logic period different from the second source output enable signal AND2_SOE2.

The multiplexer (MUX) 138 responds to the selection signal SS from the frequency comparator 128 to output the second source output enable signal AND2_SOE2 or the third AND from the second AND product 136. The second source output enable signal AND3_SOE2 from the calculator 146 is selected.

The OR operation 114 may include the first source output enable signal SOE1 from the first source output enable signal generator 120 and the second source output in from the second source output enable signal generator 130. The OR signal SOE2 is ORed. Accordingly, the OR operation unit 114 supplies the first source output enable signal SOE1 to the data driver 104 during the odd horizontal periods H1, H3, H5,... The second source output enable signal SOE2, which is variable according to the frame frequency Vsync, is supplied to the data driver 104 during H2, H4, H6,.

As such, the low period LP1 of the first source output enable signal SOE1 supplied to the odd horizontal periods H1, H3, H5, ... is the even horizontal periods H2, H4, H6, ... Is set longer than the row period LP2 of the second source output enable signal supplied to. Accordingly, the charging time of the pixel voltage signal supplied through the data line DL in the odd horizontal periods H1, H3, H5,... The charging time of the pixel voltage signal supplied through the data line DL is longer. As a result, the difference in charge amount between the odd horizontal lines to which the pixel voltage signals of the polarity opposite to the previous horizontal period are supplied and the even horizontal lines to which the pixel voltage signals of the same polarity to the previous horizontal period are supplied are compensated. Accordingly, the luminance difference between the odd horizontal line and the even horizontal line can be prevented.

In the meantime, the liquid crystal display according to the present invention has been described as an example of distinguishing two input frame frequencies (Vsync, RF), but the present invention is not limited thereto. That is, the liquid crystal display according to the present invention increases the number of rising comparator and falling comparator and multiplexer such as the second source output enable signal generator to generate a second source output enable signal for an input frame frequency of a larger area. Can be generated.

In addition, although the liquid crystal display according to the present invention has been described using the second source output enable signal varying according to the frame frequency as an example, the first source output enable signal may also vary according to the frame frequency.

As described above, the vertical two-dot inversion type liquid crystal display device and the driving method thereof generate a second source output enable signal that varies according to the frame frequency. Pixel electrodes vertically adjacent to the odd horizontal line to which the pixel voltage signal having a polarity opposite to the previous horizontal period are supplied by the second source output enable signal and to the even horizontal line to which the pixel voltage signal having the same polarity as the previous horizontal period are supplied. The amount of charge difference between them is compensated. Accordingly, the luminance difference between the odd horizontal line and the even horizontal line can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A liquid crystal display panel; A gate driver driving the gate line of the liquid crystal display panel; The first source output enable signal is responsive to a first source output enable signal in a horizontal period in which a polarity of a previous horizontal period and a pixel voltage signal are inverted, and the first source output enable signal is in a horizontal period in which the polarity of the previous horizontal period and a pixel voltage signal are the same. A data driver configured to supply the pixel voltage signal to a data line of the liquid crystal display panel in response to a second source output enable signal having a different high logic period; And at least one of the first and second source output enable signals varies according to a frame frequency. The method of claim 1, And the high logic period of the second source output enable signal varies according to the frame frequency. The method of claim 1, And the second source output enable signal has a higher logic period longer than the first source output enable signal. The method of claim 1, And a timing controller including a source output enable signal generator for generating the first and second source output enable signals. The method of claim 4, wherein The source output enable signal generator The first clock signal is generated by counting a reference clock signal at every horizontal period in which the polarity of the previous horizontal period and the pixel voltage signal are inverted, and counting the reference clock signal at every horizontal period in which the polarity of the pixel voltage signal is the same as the previous horizontal period. A counter for generating a second counting signal; A first source enable signal generator configured to generate a first source output enable signal using the first counting signal; An input frequency detector for generating a selection signal by comparing the frame frequency with a reference frequency; A second source output enable signal for generating a plurality of second source output enable signals using the second counting signal, and selecting one of a plurality of second source output enable signals using the selection signal; A generating unit; And a logical sum operation unit configured to output any one of the first and second source output enable signals. The method of claim 5, wherein The first source output enable generator A first rising comparator comparing the first counting signal with a preset first rising signal to generate a first high comparison logic signal when the two input signals are the same; A first falling comparator for comparing the first counting signal with a preset first falling signal and generating a first comparison signal having a low logic when the two input signals are the same; And a first AND operation unit configured to perform an AND operation on the first comparison signal of the high logic and the first comparison signal of the low logic. The method of claim 5, wherein The second source output enable generator A rising comparator comparing the second counting signal with a plurality of preset rising signals and generating a plurality of high logic comparison signals when the two input signals are the same; A falling comparator comparing the second counting signal with a plurality of preset falling signals to generate a plurality of low logic comparison signals when the two input signals are the same; A plurality of AND products configured to perform an AND operation on the comparison signal of the high logic and the comparison signal of the low logic to generate a plurality of the second output enable signals having different high logic periods; And a multiplexer for selecting any one of the plurality of second output enable signals using the selection signal. The method of claim 7, wherein The second source output enable generator A second rising comparator for comparing the second counting signal with a preset second rising signal to generate a high comparison second comparison signal when the two input signals are the same; A second falling comparator for comparing the second counting signal with a preset second falling signal to generate a second comparison signal of low logic when the two input signals are the same; A second AND operation unit configured to OR the second comparison signal of the high logic and the second comparison signal of the low logic to generate the second source output enable signal; A third rising comparator for comparing the second counting signal with a preset third rising signal and generating a third high comparison logic signal when two input signals are the same; A third falling comparator for comparing the second counting signal with a preset third falling signal to generate a third comparison signal having a low logic when the two input signals are the same; The second output enable signal having a different high logic period from the second output enable signal of the second AND product is generated by performing an AND operation on the third comparison signal of the high logic and the third comparison signal of the low logic. A third logical product operator; And a multiplexer configured to select a second output enable signal of any one of the second and third AND products using the selection signal. The method of claim 8, And the second rising signal and the falling signal correspond to frame frequencies different from the third rising signal and the falling signal. Generating first and second source output enable signals having different high logic periods in a horizontal period in which the polarity of the previous horizontal period and the pixel voltage signal are inverted; Steps; Generating a pixel voltage signal so that the polarity of the input pixel data is inverted by 2 dots in a vertical direction; Supplying the pixel voltage signal to liquid crystal cells in a low logic period of the first and second source output enable signals, At least one of the first and second source output enable signals varies according to a frame frequency. The method of claim 10, And wherein the second source output enable signal has a high logic period longer than the first source output enable signal. The method of claim 10, Generating the first and second source output enable signals The first clock signal is generated by counting a reference clock signal at every horizontal period in which the polarity of the previous horizontal period and the pixel voltage signal are inverted, and counting the reference clock signal at every horizontal period in which the polarity of the pixel voltage signal is the same as the previous horizontal period. Generating a second counting signal; Generating a first source output enable signal using the first counting signal; Generating a selection signal by comparing the frame frequency with a reference frequency; Generating a plurality of second source output enable signals using the second counting signal, and selecting one of a plurality of second source output enable signals using the selection signal; And performing a logical OR operation on the first and second source output enable signals. The method of claim 12, Generating the first source output enable signal Comparing the first counting signal with a preset first rising signal to generate a first high comparison logic signal when the two input signals are the same; Comparing the first counting signal with a preset first falling signal to generate a first comparison signal having a low logic when two input signals are the same; And performing a logical AND operation on the first comparison signal of the high logic and the first comparison signal of the low logic. The method of claim 12, Generating the second source output enable signal Comparing the second counting signal with a plurality of preset rising signals and generating a plurality of high logic comparison signals when the two input signals are the same; Comparing the second counting signal with a plurality of preset falling signals to generate a plurality of low logic comparison signals when the two input signals are the same; Generating a plurality of second output enable signals having different high logic periods by performing an AND operation on the comparison signal of the high logic and the comparison signal of the low logic; And selecting one of the plurality of second output enable signals using the selection signal. The method of claim 14, And the plurality of rising signals and falling signals correspond to different frame frequencies.

Images