KR100864980B1 - Apparatus for preventing afterimage in liquid crystal display - Google Patents

Abstract

The present invention relates to an afterimage preventing device of a liquid crystal display device capable of preventing an afterimage.

An afterimage prevention apparatus of the liquid crystal display device of the present invention includes a liquid crystal panel on which an image is displayed; A thin film transistor arranged in a matrix form on the liquid crystal panel; A pixel electrode connected to the thin film transistor; A common electrode disposed to face the pixel electrode with the liquid crystal interposed therebetween; A pulse generator for receiving a data enable signal from an external system and generating a pulse signal using the supplied data enable signal; A power supply unit for supplying power to the pulse generator; And a common voltage generator for generating a common voltage to be supplied to the common electrode by using the first voltage supplied from the power supply unit and the pulse signal.

Description

Afterimage prevention device for liquid crystal display {APPARATUS FOR PREVENTING AFTERIMAGE IN LIQUID CRYSTAL DISPLAY}

1 is a block diagram showing the configuration of a conventional liquid crystal display device.

FIG. 2 is a circuit diagram illustrating a gamma circuit shown in FIG. 1. FIG.

3 is a circuit diagram illustrating a common voltage generator illustrated in FIG. 1.

4 is a waveform diagram showing a leakage current generated in a liquid crystal cell.

5 is a block diagram showing the configuration of a liquid crystal display according to an embodiment of the present invention.

6 is a waveform diagram showing a common voltage according to the first embodiment of the present invention.

7 is a circuit diagram illustrating a common voltage generator according to an exemplary embodiment of the present invention.

8 is a waveform diagram showing a common voltage according to a second embodiment of the present invention.

9 is a waveform diagram showing a common voltage according to a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,20 LCD panel 4,22 Data driver

6,24 gate driver 8,26 timing controller

10,28: power supply unit 12,30: gamma circuit                 

14,32: common voltage generator 34: pulse generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an afterimage preventing device and a method of a liquid crystal display device, and more particularly, to an afterimage preventing device of a liquid crystal display device capable of preventing an afterimage.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, and a liquid crystal panel 2. A gate driver 6 for driving the gate lines GL0 to GLn, a timing controller 8 for controlling driving timing of the data and gate drivers 4 and 6, and a power supply unit 10 for supplying power ), A gamma circuit 12 for supplying a gamma voltage to the data driver 4, and a common voltage supply unit 14 for supplying a common voltage Vcom to the liquid crystal cell.

The power supply unit 10 uses driving voltages (base driving voltage (Vcc), gate high voltage (Vgh), gate low voltage (Vgl), gamma reference voltage, and common driving voltages) that are input from an external system (not shown). Voltage source) and supplies it to the timing controller 8, the data driver 4, the gate driver 6, the gamma circuit 12, and the common voltage generator 14.

The timing controller 8 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 8 that receives the data relays the data and supplies the data to the data driver 4. The timing controller 8, which receives the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable, generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and gate drivers 4 and 6. Done.

The liquid crystal panel 2 is connected to the thin film transistor TFT formed at the intersection of the n gate lines GL1 to GLn and the m data lines DL1 to DLm, and is formed in a matrix form. The liquid crystal cells are arranged as.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line in order to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The gate driver 6 sequentially supplies gate signals to the gate lines GL1 to GLn according to a control signal from the timing controller 8. The data driver 4 converts the data R, G, and B supplied from the timing controller 8 into a video signal, which is an analog signal, and converts the data signal 4 into one video signal every 1 horizontal period in which the gate signals are supplied to the gate lines GL1 to GLn. The video signal for the horizontal line is supplied to the data lines DL1 to DLm.

The gamma circuit 12 supplies the data driver 4 with a gamma voltage which is preset to have a different voltage level according to the voltage level of the video signal. Accordingly, the data driver 4 converts the data R, G, and B into a video signal by using the gamma voltage from the gamma circuit 12.

In practice, the gamma circuit 12 includes a plurality of voltage dividers R1 to Rj for dividing the gamma voltage Vr as shown in FIG. 2. At this time, the first gamma voltage Gamma1 applied to the output terminal between the zeroth resistor R0 and the first resistor R0 has the highest voltage value, and the j-1 resistor Rj-1 (not shown). And the j-th gamma voltage Gammaj applied to the output terminal between the j-th resistor Rj has the lowest voltage value.

The data driver 4 selects a gamma voltage having a predetermined DC level according to the luminance values of the data R, G, and B, and supplies the selected gamma voltage to the data lines DL1 to DLm. In practice, the data driver 4 selects a gamma voltage of any one of the first gamma voltage Gamma1 and the jth gamma voltage Gammaj according to the luminance values of the data R, G, and B.

The common voltage generator 14 generates a common voltage Vcom and supplies the generated common voltage Vcom to a common electrode which is one side of the liquid crystal capacitor Clc. The common voltage generator 14 may include third and fourth resistors R3 and R4 and a third resistor R3 for dividing the voltage of the common voltage source Vc supplied from the power supply unit 10 as shown in FIG. 3. ) And the variable resistor Rv provided between the common voltage source Vc.

The common voltage Vcom is applied to an output terminal between the third and fourth resistors R3 and R4. The resistance value of the variable resistor Rv is set such that a desired common voltage Vcom can be applied to the fourth resistor R4.

The conventional liquid crystal display device has a problem in that an afterimage is displayed on the screen when the fixed pattern is displayed on the screen for a long time, that is, when a predetermined voltage is applied for a long time. This problem will be described in detail with reference to FIG. 4.

Referring to FIG. 4, since the liquid crystal display is generally driven in an inversion method, the video signal supplied to the data lines DL1 to DLm is divided into a positive video signal and a sub video signal. That is, when the gate signal is sequentially supplied to the gate lines GL1 to GLn, the positive or negative video signal is commonly supplied to the data lines DL1 to DLm.

The video signals supplied to the data lines DL1 to DLm are charged in the liquid crystal cell until the next video signals are supplied. At this time, the video signals charged in the liquid crystal cell leak by a predetermined current, and at this time, the amount of leakage current I1 of the positive video signal and the amount of leakage current I2 of the sub video signal are different.

Therefore, when the fixed pattern is displayed on the screen for a long time, the liquid crystal cell is generated with a DC voltage due to the difference in leakage current in the liquid crystal cell, and the afterimage is displayed on the screen by this DC voltage. Conventionally, the gamma voltage Gamma and the common voltage Vcom are adjusted to minimize such afterimages. However, the adjustment of the gamma voltage Gamma and the common voltage Vcom cannot fundamentally prevent the afterimage from being displayed on the screen.

Accordingly, an object of the present invention is to provide an afterimage preventing device of a liquid crystal display device capable of preventing an afterimage.

In order to achieve the above object, the afterimage preventing device of the liquid crystal display device of the present invention includes a liquid crystal panel displaying an image; A thin film transistor arranged in a matrix form on the liquid crystal panel; A pixel electrode connected to the thin film transistor; A common electrode disposed to face the pixel electrode with the liquid crystal interposed therebetween; A pulse generator for receiving a data enable signal from an external system and generating a pulse signal using the supplied data enable signal; A power supply unit for supplying power to the pulse generator; And a common voltage generator for generating a common voltage to be supplied to the common electrode by using the first voltage supplied from the power supply unit and the pulse signal.

The common voltage generator generates a common voltage having at least two voltage values.                     

The pulse generator generates a pulse signal having at least one voltage value among a third voltage lower than the second voltage or a fourth voltage higher than the second voltage, which is a reference to be synchronized with a low section of the data enable signal.

The common voltage generator divides the first voltage to generate a fifth voltage, and adds the voltage value of the pulse signal to the fifth voltage to supply the common electrode.

The fifth voltage is supplied to the common electrode in the high section of the data enable signal, and the voltage value obtained by adding the voltage value of the pulse signal to the common electrode in the low section of the data enable signal is supplied to the common electrode.

The pulse signal having the third voltage value and the pulse signal having the fourth voltage value are alternately generated in line units.

The pulse signal having the third voltage value and the pulse signal having the fourth voltage value are alternately generated in units of frames.

An afterimage preventing method of a liquid crystal display of the present invention includes generating a pulse signal synchronized with a low section of a data enable signal in a pulse generator receiving a voltage from the power supply unit, and supplying from the power supply unit in a common voltage generator. And generating a common voltage supplied to the common electrode in each pixel by using the reference voltage and the pulse signal supplied from the pulse generator.

The common voltage may include a second voltage generated by dividing a reference voltage to be supplied to a high section of the data enable signal, and a third voltage generated by adding a pulse signal and a second voltage to be supplied to a low section of the data enable signal. It includes.

The pulse signal has at least one voltage value among a fourth voltage having a voltage value higher than a predetermined voltage and a fifth voltage having a voltage value lower than the predetermined voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 9.

5 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 20, a data driver 22 for driving data lines DL1 to DLm of the liquid crystal panel 20, and a liquid crystal display. Supply a gate driver 24 for driving the gate lines GL0 to GLn of the panel 20, a timing controller 26 for controlling the driving timing of the data and gate drivers 22 and 24, and a power supply. A power supply 28 for supplying a gamma circuit 30 to supply a gamma voltage to the data driver 22, a pulse generator 34 for generating a pulse signal by receiving a data enable (DE) signal; And a common voltage supply unit 32 for supplying a common voltage Vcom to the liquid crystal cell.

The power supply unit 28 uses driving voltages (base driving voltage (Vcc), gate high voltage (Vgh), gate low voltage (Vgl), gamma reference voltage, and common driving voltages) that are input from an external system (not shown). Voltage source) is supplied to the timing controller 26, the data driver 22, the gate driver 24, the gamma circuit 30, the common voltage generator 32, and the pulse generator 34.

The timing controller 26 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 26 receiving the data relays the data and supplies the data to the data driver 22. The timing controller 26 receiving the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and gate drivers 22 and 24. Done.

The liquid crystal panel 20 is connected to the thin film transistor TFT formed at the intersection of the n gate lines GL1 to GLn and the m data lines DL1 to DLm, and is formed in a matrix form. The liquid crystal cells are arranged as.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The gate driver 24 sequentially supplies gate signals to the gate lines GL1 to GLn according to a control signal from the timing controller 26. The data driver 22 converts the data R, G, and B supplied from the timing controller 26 into a video signal, which is an analog signal, every horizontal period in which the gate signal is supplied to the gate lines GL1 through GLn. The video signal for one horizontal line is supplied to the data lines DL1 to DLm.

The gamma circuit 30 supplies a gamma voltage preset to the data driver 22 to have different voltage levels according to the voltage level of the video signal. Accordingly, the data driver 22 converts the data R, G, and B into a video signal by using the gamma voltage from the gamma circuit 30.

The pulse generator 34 receives a data enable signal from an external system and generates a pulse of a predetermined period using the received data enable signal. In practice, the pulse generator 34 generates a pulse so as to be synchronized with a low period of the data enable DE signal, that is, a data blanking period, as shown in FIG. 6. In other words, the pulse generator 34 generates a pulse so that data is synchronized with a data blanking period in which data is not supplied to the liquid crystal panel 20, and generates the generated pulse in the common voltage generator 32. To supply.

The common voltage generator 32 generates a common voltage Vcom of AC using the pulse signal Pulse supplied from the pulse generator 34, and converts the generated common voltage Vcom into a liquid crystal capacitor Clc. Supply to the common electrode which is one side electrode. The common voltage generator 32 includes the first and second resistors R1 and R2 and the first resistor R1 for dividing the voltage of the common voltage source Vc supplied from the power supply unit 28 as shown in FIG. 7. ) And the variable resistor Rv provided between the common voltage source Vc.

The common voltage Vcom is extracted from the output terminal between the first and second resistors R1 and R2, and the extracted common voltage Vcom is supplied to the common electrode. The variable resistor Rv has its resistance set so that the voltage value of the common voltage Vcom can be a constant value. The pulse signal Pulse supplied from the pulse generator 34 is supplied to the first resistor R1.

Accordingly, the common voltage Vcom supplied to the common electrode maintains the first voltage in the data enable period and maintains the second voltage higher than the first voltage in the data blanking period as shown in FIG. 6. In other words, the common voltage Vcom is supplied in alternating current so as to have a high voltage in the data blanking period.

As such, when the common voltage Vcom is supplied in an alternating current state, afterimages may be prevented from being displayed on the screen. That is, the afterimage of the screen is generated by the DC voltage generated in the liquid crystal cell when the fixed pattern is displayed for a long time. However, in the present invention, since the common voltage Vcom is supplied in alternating current, a certain pattern cannot be displayed on the screen for a long time.

In other words, when the fixed pattern is displayed for a long time, the common voltage Vcom of the AC is supplied (that is, has a pattern shape different from that of the fixed pattern), thereby preventing the generation of the DC voltage in the liquid crystal cell. . In particular, the present invention does not affect image quality because the common voltage Vcom has a high voltage in the data blanking period.

Meanwhile, in the present invention, as shown in FIG. 8, the pulse generator 34 may generate a pulse lowered from a specific voltage and supply the generated pulse to the common voltage generator 32. In this case, the pulse generated by the common voltage generator 32 is generated to overlap the data blanking period.

On the other hand, when a pulse lowered from a specific voltage is supplied to the pulse common voltage generator 32, the common voltage Vcom generated by the common voltage generator 32 maintains the first voltage in the data enable period. The third voltage lower than the first voltage is maintained in the data blanking period. Therefore, the common voltage Vcom is supplied in an alternating current form, thereby preventing the afterimage from being displayed on the screen.

In addition, in the present invention, the common voltage Vcom illustrated in FIGS. 6 and 8 may be alternately supplied to the common electrode in frame units. For example, a common voltage Vcom having first and second voltage values is supplied to the common electrode in an odd praim as shown in FIG. 6, and a common voltage having first and third voltage values as shown in FIG. 8 in an even frame. The voltage Vcom may be supplied to the common electrode.

Similarly, in the present invention, as shown in FIG. 9, the common voltage Vcom of which the voltage value changes in units of lines may be supplied to the common electrode.

In detail, first, the pulse generator 34 alternately generates the first pulse P1 lowered from the specific voltage and the second pulse P2 highered from the specific voltage. In this case, the first pulse P1 and the second pulse P2 are generated to be synchronized with the data blanking period. The first pulse P1 and the second pulse P2 generated by the pulse generator 34 are supplied to the common voltage generator 32.

The common voltage generator 32 generates the common voltage Vcom by adding the first pulse P1 and the second pulse P2 supplied from the pulse generator 34 to a specific voltage generated by the common pulse generator 34. The common voltage is supplied to the common electrode. Therefore, the common voltage Vcom is supplied in an alternating current form, thereby preventing the afterimage from being displayed on the screen.

As described above, in the afterimage preventing apparatus of the liquid crystal display according to the present invention, the common voltage of an alternating current type is supplied to the common electrode, thereby preventing the afterimage from being displayed on the screen.

In other words, the common voltage in the present invention maintains a constant voltage during the data enable period, and supplies a fixed voltage by supplying a first voltage lower than the constant voltage value and / or a second voltage higher than the constant voltage value during the data blanking period. It is possible to prevent the display for a long time, thereby preventing the afterimage from being displayed on the screen. In addition, the present invention does not affect the image quality by supplying the first voltage and / or the second voltage in the data blanking period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A liquid crystal panel in which a plurality of pixels are formed and a common electrode and a pixel electrode are disposed to face each other in the pixel; A pulse generator for generating a pulse signal by using a data enable signal input from an external system; A power supply unit for supplying power to the pulse generator; And a common voltage generator for generating a common voltage using the first voltage and the pulse signal from the power supply unit and supplying the common voltage to the common electrode. The method of claim 1, And wherein the common voltage generated from the common voltage generator has at least two voltage values. The method of claim 1, The pulse generator, And generating a pulse signal having a voltage value of at least one of a third voltage lower than a second voltage or a fourth voltage higher than the second voltage to be synchronized with a low period of the data enable signal. Afterimage prevention device of display device. The method of claim 3, wherein The common voltage generator divides the first voltage to generate a fifth voltage, and adds the voltage value of the fifth voltage and the pulse signal to the common electrode to supply the common electrode to the common electrode. The method of claim 4, wherein The fifth voltage is supplied to the common electrode in the high section of the data enable signal, and the voltage value obtained by adding the voltage value of the fifth voltage and the pulse signal to the common electrode in the low section of the data enable signal. Afterimage preventing device of the liquid crystal display device, characterized in that supplied. The method of claim 3, wherein The pulse signal having the third voltage value and the pulse signal having the fourth voltage value are generated alternately in units of lines. The method of claim 3, wherein The pulse signal having the third voltage value and the pulse signal having the fourth voltage value are generated alternately in units of frames. delete delete delete delete

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