JPH10301541A - Liquid crystal driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operational efficiency in a circuit generating a gradated voltage and to realize low power consumption in a whole liquid crystal display device. SOLUTION: This liquid crystal drive circuit having a gradated voltage selective system converts a digital video signal to 16 gradated levels RG1-RG16, GG1-GG16, BG1-BG16 by decoders 31R, 31G, 31B, and inputs decoded outputs of respective colors to counters 33-1 to 33-16 through OR gates 32-1 to 32-16 at every gradated level, and counts the number of times that respective gradated levels are written in for a horizontal scanning period. Then, the drive circuit selects one among current sources I1, I2, I3 by selection switches SW1, SW2, SW3 according to the number of times, and supplies it to gradation voltage output buffers 34-1 to 34-16 as a bias current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving circuit, and more particularly to an amorphous silicon (a-Si) TFT (Th
The present invention relates to a gradation voltage selection type liquid crystal driving circuit in a liquid crystal display device using a liquid crystal driving element such as an in-film transistor (thin film transistor).

[0002]

2. Description of the Related Art Conventionally, a line-sequential driving circuit having the structure shown in FIG. 6 has been known as this type of liquid crystal driving circuit. In FIG. 6, analog image signals of R (red), G (green), and B (blue) input via an analog I / F (interface) 101 are converted by an A / D converter 102 into R, G, B
After being converted into each 4-bit digital video signal, it is supplied to the column driver 103.

[0003] In the column driver 103, the input digital video signal to be displayed is transmitted to the data transfer circuit 10.
After the data is transferred to the latch circuit 105 through the latch circuit 4 and latched for one line, the data is decoded by the decoder 106 to a gray level. The decoded value of decoder 106 is applied to gradation voltage selection circuit 107. Gradation voltage selection circuit 107
Selects a gray scale voltage corresponding to the decode value of the decoder 106 from, for example, 16 gray scale voltages generated by the gray scale voltage generator 108, and selects an amorphous silicon TFT.
Output to a liquid crystal panel (liquid crystal display device) 109.

A horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC input via an analog I / F 101
Are both supplied to the timing pulse generator 110. The timing pulse generator 110 outputs the horizontal synchronizing signal HSYN.
A column driver drive pulse and a row driver drive pulse are generated based on C and the vertical synchronization signal VSYNC, and these drive pulses are supplied to the column driver 103 and the row driver 111, respectively. From the power supply unit 112, a column driver power supply and a row driver power supply are supplied to the column driver 103 and the row driver 111, respectively, and a backlight power supply is further supplied to the backlight 114 via the backlight inverter 113.

In the gradation voltage selection type liquid crystal driving circuit having the above-mentioned structure, since a gradation voltage is directly inputted from the outside, a D / A converter or the like for converting into a voltage corresponding to the gradation level is provided. Is not required to be built in the column driver 103, so that there is an advantage that the circuit configuration can be simplified and the cost can be reduced.

[0006]

However, with the development of a reflection type liquid crystal display device which does not require a backlight, a demand for lowering the power consumption of a liquid crystal drive circuit has been raised. In the liquid crystal drive circuit of the type, it is difficult to reduce power consumption. This is because the liquid crystal drive circuit is designed in consideration of the case where any gray level is written to all the pixels in one horizontal scanning period, so that a certain gray level is not displayed in the horizontal scanning period. This is because the bias current of the grayscale voltage generator 108 must be supplied, which is inefficient.

As a method for saving power, the AC inversion cycle of the voltage applied to the liquid crystal display device is extended from one horizontal scanning period to one vertical scanning period. The load capacity of the liquid crystal panel 109 is reduced. The following two methods can be considered. However, in the case of the method, the image quality is deteriorated due to the occurrence of flicker. In the case of the method, a limit design of the liquid crystal display device is required, and it is difficult to adopt the method in terms of reliability and yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to improve the efficiency of a circuit for generating a gray scale voltage in actual operation and reduce the power consumption of the entire liquid crystal display device. It is an object of the present invention to provide a liquid crystal driving circuit aiming at realization of a liquid crystal display.

[0009]

A liquid crystal drive circuit according to the present invention is a liquid crystal drive circuit of a gradation voltage selection type, which decodes an input video signal into a plurality of gradation levels,
Detecting means for detecting the frequency at which each of the plurality of gray levels is written to the liquid crystal display device during one horizontal scanning period, and a bias current corresponding to the frequency detected by the detecting means is set for each gray level. And a gradation voltage output means for outputting a plurality of gradation voltages corresponding to a plurality of gradation levels.

In the liquid crystal driving circuit having the above configuration, the detecting means detects how many dots are output at each gradation level in one horizontal scanning period. From this frequency, it is possible to know in advance how many dots are to be written simultaneously with each gradation voltage when each gradation voltage is output, that is, how much the gradation voltage load will be. Then, the bias current of the gradation voltage output means is set based on the detected frequency. As a result, only the necessary minimum drive current corresponding to the input video signal can be supplied each time for each gray level in one horizontal scanning period.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of a gradation voltage selection type line sequential driving circuit in a liquid crystal display device using, for example, an amorphous silicon TFT as a liquid crystal driving element to which the present invention is applied.

In FIG. 1, R, G, B analog video signals input via an analog I / F 11 are A / D
After being converted into R, G, and B 4-bit digital video signals by the converter 12, the digital video signals are supplied to the column driver 13. The column driver 13 includes a data transfer circuit 14, a latch circuit 15, a decoder 16, and a gray scale voltage selection circuit 17.
It is composed of

The data transfer circuit 14 is composed of a shift register and the like, and sequentially transfers the inputted R, G, B digital video signals of 4 bits to the latch circuit 15. The latch circuit 15 is composed of, for example, a line memory, and latches the digital video signals sequentially transferred from the data transfer circuit 14 for one line. The digital video signal for one line is decoded to a gradation level by the decoder 16. This decode value is given to the gradation voltage selection circuit 17.

The gray scale voltage selection circuit 17 selects a gray scale voltage corresponding to a decode value given from the decoder 16 from, for example, 16 level gray scale voltages supplied from the gray scale voltage generation circuit 18 and selects an amorphous silicon TFT. Output to a liquid crystal panel (liquid crystal display) 19. FIG. 2 shows an example of the specific circuit configuration. As shown in the drawing, a gray scale voltage corresponding to a decode value given from the decoder 16 is selected from 16 gray scale voltages V1 to V16 and supplied to the column signal lines of the liquid crystal panel 19. The configuration is such that selection switches S1 to S16 are provided for each column.

The gradation voltage generating circuit 18 is a feature of the present invention, and its specific configuration will be described later in detail. The gradation voltage generation circuit 18 includes R, G,
B. A 4-bit digital video signal is supplied. Then, from the grayscale voltage generation circuit 18, for example, 16
Level gradation voltages V1 to V16 are output. These gradation voltages V1 to V16 are supplied to the gradation voltage selection circuit 17.

The horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC input via the analog I / F 11 are both supplied to the timing pulse generator 20. The timing pulse generator 20 generates a column driver driving pulse and a row driver driving pulse based on the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC, and supplies these driving pulses to the column driver 13 and the row driver 21, respectively. A column driver power supply and a row driver power supply are supplied from the power supply unit 22 to the column driver 1.
3 and a row driver 21, and backlight power is further supplied to a backlight 24 via a backlight inverter 23.

FIG. 3 is a block diagram showing a first embodiment of the present invention applied to a liquid crystal display device which performs 16-gradation display using, for example, 4 bits for each of R, G, and B. 3 shows an example of a specific circuit configuration of the adjustment voltage generating circuit 18.

In FIG. 3, decoders 31R, 31G,
To 31B, digital video signals R0 to R3, G0 to G3, and B0 to B3 of 4 bits each for R, G, and B are input. The decoder 31R decodes the digital video signals R0 to R3 into 16 gradation levels RG1 to RG16. Similarly, the decoder 31G decodes to 16 gray levels GG1 to GG16, and the decoder 31B decodes to 16 gray levels BG1 to BG16.

Each of the 16 decoders 31R, 31G, 31B
Gray level RG1 to RG16, GG1 to GG16, BG
1 to BG16 are inputted to OR gates 32-1 to 32-16 for 16 gradations with the same gradation level as a set. That is, the OR gate 32-1 has the gradation levels RG1, GG1,
BG1 is input in the same set, and the grayscale levels RG2, G
A set of G2, BG2,..., Gradation levels RG16, GG1
6 and BG16 are input to the OR gates 32-2,...,.

Each output of the OR gates 32-1 to 32-16 is
Each clock (CK) input to the counters 33-1 to 33-16 for 16 gradations. These counters 33-1 to 33-16
Is a reset (RST) input of the horizontal synchronizing signal HSYNC, and counts up one by one each time the decoder 31R, 31G, 31B outputs each gradation level in one horizontal scanning period. R, G,
Count how many dots are output in total B,
According to the frequency, for example, three control signals CS
1, CS2 and CS3 are output.

These control signals CS1, CS2,
CS3 is a current source of 16 gray scale voltage output buffers 34-1 to 34-16 having, for example, three current sources I1, I2 and I3 (I1>I2> I3) having different current values. It is a signal for selection. That is, when looking at the gray scale level 1, between the power supply VDD and the output buffer 34-1, the current sources I1, I2, I3 and the selection switch SW1,
SW2 and SW3 are connected in series, respectively, and the counter 3
3-1, the control signals CS1, CS2,
CS3 controls ON (closed) / OFF (open) control of the selection switches SW1, SW2, and SW3.

The gradation levels 2 to 16 have the same configuration as the gradation level 1. The gray scale voltage output buffers 34-1 to 34-16 are driven by a bias current supplied from one of the three current sources I1, I2 and I3, and have 16 levels provided by the gray scale voltage generator 35. The gray scale voltages V1 'to V16' are supplied as gray scale voltages V1 to V16 to the gray scale voltage selection circuit 17 shown in FIG.
That is, in the case of this example, the gradation voltage output buffer 34
The driving capability of -1 to 34-16 is variable in three stages.
Since these gray scale voltage output buffers 34-1 to 34-16 are interposed between the gray scale voltage selection circuit 17, the gray scale voltage generator 35 may have a small driving ability.

In the grayscale voltage generating circuit 18 according to the first embodiment having the above configuration, the counters 33-1 to 33-16 have
By resetting with the horizontal synchronizing signal HSYNC, the number of R, G, and B total dots output at each gradation level in one horizontal scanning period is counted. From this frequency, it is possible to know in advance how many dots of the gradation voltage are to be written at the time of outputting each of the gradation voltages V1 to V16, that is, how much the gradation voltage load will be.

These counters 33-1 to 33-16
Output three control signals CS1, CS2 and CS3 according to the counted frequency. The control signal CS1 selects the current source I1 by turning on the selection switch SW1. Similarly, the control signal CS2 controls the current source I2 and the control signal CS2.
3 selects the current source I3.

As a result, the output current of the gray scale voltage generation circuit 18 changes according to the number of times (frequency) written to the liquid crystal panel 19 during one horizontal scanning period for each gray scale voltage, that is, the load of the gray scale voltage. Become. That is, in FIG.
Focusing on the gradation level 5 as an example, since the frequency is A on the 1st line, the current source I1 (large current mode) is selected and m
Since the frequency is B at the line, current source I2 (current mode)
Is selected and the current source I3 (small current mode) is selected because the frequency is C in the n-th line, so that the liquid crystal panel 19 can be driven with the minimum driving capability according to the video signal.

In FIG. 4, when the number of dots in one line is, for example, 960, the frequency A is, for example, 1% of the 960 dots occupied by the gradation level 5.
00%, frequency B represents 40%, and frequency C represents 5%. Another gradation level, that is, gradation level 1
Also for the gradation level 4 and the gradation levels 6 to 16, the output current of the gradation voltage generation circuit 18 is set according to the gradation voltage load in the same manner as in the case of the gradation level 5.

As described above, the frequency (frequency) selected for each gradation voltage from the input video signal for one horizontal scanning period is obtained in advance, and the current source I1, I2, or I3 corresponding to the frequency is selected from the current sources I1, I2, and I3. Is selected, and the current is supplied as a bias current to the gradation voltage output buffers 34-1 to 34-16, so that only the necessary minimum drive current according to the input video signal flows each time. Therefore, the efficiency of the grayscale voltage generation circuit 18 in actual operation can be improved.

To determine the frequency of writing to the liquid crystal panel 19 during one horizontal scanning period for each gradation voltage, a 4-bit digital signal R for each of R, G, and B is used.
0 to R3, G0 to G3, B0 to B3 are connected to the decoder 31R,
31G, 31B, 16 gradation levels RG1 to RG16, G
G1 to GG16 and BG1 to BG16 are decoded, and the same gradation level is set as a set, and the OR gates 32-1 to 16-1 for 16 gradations are decoded.
32-16 and 16 counters 33-1 to 33-16
, And the arithmetic processing is not performed, so the time delay associated with the processing is extremely small.
Processing can be performed in parallel with the latch operation in the latch circuit 15 of FIGS.

FIG. 5 is a block diagram showing a second embodiment of the present invention applied to a liquid crystal display device which performs 16 gradation display using, for example, 4 bits for each of R, G and B. 9 shows another example of a specific circuit configuration of the adjustment voltage generation circuit 18.

In FIG. 5, decoders 41R, 41G,
To 41B, digital video signals R0 to R3, G0 to G3, and B0 to B3 of 4 bits each for R, G, and B are input. The decoder 41R decodes the digital video signals R0 to R3 into 16 gradation levels RG1 to RG16. Similarly, the decoder 41G decodes to 16 gray levels GG1 to GG16, and the decoder 41B decodes to 16 gray levels BG1 to BG16.

Each of the 16 decoders 41R, 41G, 41B
Gray level RG1 to RG16, GG1 to GG16, BG
1 to BG16 are input to the OR gates 42-1 to 42-16 for 16 gradations with the same gradation level as a set. That is, the OR gate 42-1 has the gradation levels RG1, GG1,
BG1 is input in the same set, and the grayscale levels RG2, G
A set of G2, BG2,..., Gradation levels RG16, GG1
6 and BG16 are input to the OR gates 42-2,...,.

Each output of the OR gates 42-1 to 42-16 is
Each clock (CK) is input to the counters 43-1 to 43-16 for 16 gradations. These counters 43-1 to 43-16
Sets the horizontal synchronizing signal HSYNC to a reset (RST) input, and counts up one by one each time the decoder 41R, 41G, 41B outputs each gray level in one horizontal scanning period. R, G,
Count how many dots are output in total B,
According to the frequency, for example, three control signals CS
1, CS2 and CS3 are output.

On the other hand, for example, three gradation voltage circuits 51-1 to 51-16, 52-1 to 52-16, 53-1 to 53-16 having different circuit configurations and driving capacities for each gradation level. -1
6 are provided. Here, when looking at the gray scale level 1, the selection switches SW1, SW2, and SW3 are connected to the respective output sides of the gray scale voltage circuits 51-1, 52-1 and 53-1. The three control signals CS1, CS2, and CS3 output from the counter 43-1 control ON / OFF of the selection switches SW1, SW2, and SW3.

The selection switches SW1, SW2, SW3 are
When one of them is turned on based on the control signals CS1, CS2, and CS3, one of the output voltages of the gradation voltage circuits 51-1, 52-1 and 53-1 having different driving capabilities is turned on.
One of them is supplied as the gradation voltage V1 to the gradation voltage selection circuit 17 shown in FIG. The gradation levels 2 to 16 have the same configuration as the gradation level 1.

In the grayscale voltage generating circuit 18 according to the second embodiment having the above configuration, the counters 43-1 to 43-16 have
By resetting with the horizontal synchronizing signal HSYNC, the number of R, G, and B total dots output at each gradation level in one horizontal scanning period is counted. From this frequency, it is possible to know in advance how many dots of the gradation voltage are to be written at the time of outputting each of the gradation voltages V1 to V16, that is, how much the gradation voltage load will be.

Then, these counters 43-1 to 43-16
Output three control signals CS1, CS2 and CS3 according to the counted frequency. The control signal CS1 selects the output voltages of the gradation voltage circuits 51-1 to 51-16 by turning on the selection switch SW1. Similarly, the control signal CS2 selects the output voltages of the gradation voltage circuits 52-1 to 52-16, and the control signal CS3 selects the output voltages of the gradation voltage circuits 53-1 to 53-16.

As a result, the driving capability of the gradation voltage generation circuit 18 changes according to the number of times (frequency) of writing to the liquid crystal panel 19 during one horizontal scanning period for each gradation voltage, that is, the load of the gradation voltage. Become. That is, in FIG.
Focusing on the gradation level 5 as an example, since the frequency is A on the first line, the gradation voltage circuit 51-5 (large current mode) is turned on, and the other gradation voltage circuits 52-5 and 53-5 are turned off. m
Since the frequency is B at the line, the gray scale voltage circuit 52-5 (current mode) is turned on and the other gray scale voltage circuits 51-5 and 53-5 are turned on.
Is turned off, and the frequency is C at the n-th line.
3-5 (small current mode) is turned on and other gradation voltage circuits 5
The liquid crystal panel 19 can be driven with the minimum driving capability according to the video signal, such as turning off 1-5 and 52-5.

As described above, the frequency (number of times) selected for each gradation voltage from the input video signal for one horizontal scanning period is obtained in advance, and the gradation voltage circuits 51-1 to 51-16, 52-1 to 52-1 are selected.
52-16 and 53-1 to 53-16, for each gradation, a gradation voltage circuit having a driving capability corresponding to the obtained frequency is selected, so that the necessary minimum voltage corresponding to the input video signal is minimized. Since only the drive current described above can flow each time, the efficiency of the grayscale voltage generation circuit 18 in actual operation can be improved.

In calculating the frequency to be written to the liquid crystal panel 19 during one horizontal scanning period for each gradation voltage, the same processing as in the first embodiment is performed, and the arithmetic processing is not performed. The accompanying time delay is extremely small, and the processing can be performed in parallel with the latch operation in the latch circuit 15 of FIGS. 1 and 2 as in the case of the first embodiment.

In the above embodiments, the case where the present invention is applied to the drive circuit of the backlight type liquid crystal display device has been described, but the present invention is not limited to this. In particular, with the development of a reflective liquid crystal display device that does not require a backlight, it is desired to reduce the power consumption of the driving device. It is suitable for a driving circuit of a reflection type liquid crystal display device which does not require a backlight because the current consumption of the device can be reduced and the power consumption can be significantly reduced.

[0041]

As described above, according to the present invention,
In the gradation voltage selection type liquid crystal driving circuit, a frequency selected for each gradation voltage from an input video signal for one horizontal scanning period is obtained in advance, and a bias current (driving capability) of the gradation voltage generation circuit is determined according to the frequency. ), Only the minimum necessary drive current according to the input video signal can be supplied for each gray level in each horizontal scanning period. Operational efficiency can be improved, and low power consumption of the entire liquid crystal display device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a gradation voltage selection type line sequential drive circuit according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of a column driver.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of the number of times of writing a gradation.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a gradation voltage selection type line sequential drive circuit according to a conventional example.

[Description of Signs] 13 Column Driver 14 Data Transfer Circuit 1
5 Latch circuit 16 Decoder 17 Gradation voltage selection circuit 18
Gray scale voltage generation circuit 19 TFT liquid crystal panel 21 Row driver 2
4 Backlights 33-1 to 33-16, 43-1 to 43-16 Counters 34-1 to 34-16 Grayscale voltage output buffer 35 Grayscale voltage generators 51-1 to 51-16, 52-1 to 52 -16, 53-1 to 53-1
6 Gradation voltage circuit I1, I2, I3 Current source SW1-SW3 selection switch

Claims (4)

[Claims] 1. A gradation voltage selection type liquid crystal driving circuit, comprising: decoding means for converting an input video signal into a plurality of gradation levels; and wherein each of the plurality of gradation levels is a liquid crystal display during one horizontal scanning period. Detecting means for detecting a frequency to be written into the device; and a plurality of grayscale voltages corresponding to the plurality of grayscale levels, wherein a bias current is set for each grayscale level in accordance with the frequency detected by the detecting means. And a grayscale voltage output means for outputting a gray scale voltage. 2. The grayscale voltage output means includes: a grayscale voltage generator configured to generate a plurality of grayscale voltages corresponding to the plurality of grayscale levels; and the plurality of grayscale voltage generators generated by the grayscale voltage generator. A plurality of buffers each outputting a gradation voltage; a plurality of current sources provided for each of the plurality of gradation levels; a plurality of current sources having different magnitudes of the current values; and the plurality of current sources according to frequencies detected by the detection means. 2. The liquid crystal driving circuit according to claim 1, further comprising switch means for selecting one of the current sources and supplying the selected current source to said plurality of buffers as a bias current. 3. The gradation voltage output means is provided for each of the plurality of gradation levels, and generates a plurality of gradation voltage circuits for generating the same gradation voltage with different bias currents. 2. A liquid crystal driving circuit according to claim 1, further comprising: switch means for selecting one of said plurality of gradation voltage circuits according to the frequency and outputting the gradation voltage. 4. The switch means turns off a grayscale voltage circuit with a large bias current if the frequency detected by the detection means is small, and turns off a grayscale voltage circuit with a small bias current if the frequency detected is high. The liquid crystal drive circuit according to claim 3, wherein: