KR100892351B1 - Source Driver and Method For Driving the Same, and Liquid Crystal Display Device Using the Source Driver - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a configuration of a source driver that can flexibly cope with a compact design of a chip while using a small current consumption.

In order to achieve the above object, the source driver according to the present invention,

A data comparator for performing a comparison operation on the digital image data input from the outside and outputting a control signal, a decoder controller receiving the control signal and outputting a decoder control signal, and a plurality of decoders controlled by the decoder control signal A decoder unit comprising a plurality of decoder blocks having a decoder and converting and outputting the digital image data into an analog image signal by using any one decoder in each decoder block, and controlled by the control signal and the analog image signal. It characterized in that it comprises a secondary amplifier unit for supplying a common to a plurality of data lines.

Source driver, auxiliary amplifier section, data comparison section

Description

Source Driver and Method for Driving the Same, and Liquid Crystal Display Device Using the Source Driver}

1 is a block diagram showing a configuration of a source driver according to an embodiment of the present invention.

2 is a block diagram showing the configuration of a control unit in a source driver according to an embodiment of the present invention;

3 is a block diagram showing a configuration of a data path unit in a source driver according to an embodiment of the present invention;

4 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

5 is a flowchart illustrating a method of driving a source driver according to an embodiment of the present invention.

6 is a configuration diagram showing an amplifier unit in a conventional source driver.

Fig. 7 is a block diagram showing the structure of a conventional source driver.

The present invention relates to a source driver applied to a small liquid crystal display device, and an object of the present invention is to provide a source driver connected to a plurality of channels without increasing the area of the source driver or reducing the driving force.

In addition, an object of the present invention is to provide a liquid crystal display device capable of realizing a high resolution without increasing the area of the source driver or lowering the driving force.

With the development of the information society, new video display devices have been developed that improve the disadvantages such as heavy weight and large volume of the conventional CRT (Cathode Ray Tube).

Accordingly, various types of liquid crystal display devices (LCDs), organic light emitting diodes (OLEDs), plasma panel display devices (PDPs), surface-conduction electron-emitter display devices (SEDs), etc. Flat panel displays are attracting attention.

Among the various flat panel displays, such liquid crystal displays are widely used, ranging from small screens such as mobile phones or portable multimedia players (PMPs) to large screens such as TV displays. It may be referred to as a flat panel display device.

A liquid crystal display device is a display device that implements a desired image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant interposed between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field.

Such a liquid crystal display includes a liquid crystal display panel for displaying an image, a source driver and a gate driver for applying a signal for driving the liquid crystal display panel, and a backlight unit for applying predetermined light to the liquid crystal display panel. It is configured to include).

The source driver includes a plurality of source drivers, and the source driver sequentially receives data from the outside and outputs digital image data, and converts the digital image data into an analog image signal. And a decoder for outputting, and an amplifier for amplifying and outputting the analog image signal to each output channel.

In particular, the amplifier unit is composed of amplifiers provided for each output channel as shown in FIG. 7. As a result, amplifiers are provided for each output channel.

In addition, an increase in the area occupied by the amplifier unit in the source driver has a problem of being a limiting factor in the miniaturization of the chip.

Accordingly, there is a demand for a source driver that uses less current consumption and can flexibly cope with miniaturization of chips.

An object of the present invention is to solve the above problems, and to provide a configuration of a source driver that can more flexibly respond to the miniaturized design of the chip while using a small current consumption.

In order to achieve the above object, the source driver according to the present invention,

A data comparator for performing a comparison operation on the digital image data input from the outside and outputting a control signal, a decoder controller receiving the control signal and outputting a decoder control signal, and a plurality of decoders controlled by the decoder control signal A decoder unit comprising a plurality of decoder blocks having a decoder and converting and outputting the digital image data into an analog image signal by using any one decoder in each decoder block, and controlled by the control signal and the analog image signal. It characterized in that it comprises a secondary amplifier unit for supplying a common to a plurality of data lines.

In addition, the method of driving a source driver according to the present invention comprises the steps of outputting the digital image data to the data comparison unit in sequence, performing a comparison operation on the digital image data sequentially input from the data comparison unit, and Outputting a control signal according to a comparison operation result to a decoder controller and an auxiliary amplifier unit, outputting a decoder control signal from the decoder controller to a decoder unit including a plurality of decoder blocks, and at each decoder block according to the decoder control signal And converting the digital image data into an analog image signal and outputting the analog image signal to a plurality of data lines through an auxiliary amplifier unit by using any one of the decoders. do.

Next, a source driver according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a source driver according to an embodiment of the present invention.

In the drawings below, like reference numerals refer to like elements.

As can be seen in Figure 1, the source driver according to an embodiment of the present invention,

The data register unit 900 receives the memory data signal MEM_DATA and the shift clock SCK and outputs the digital image data RGB, and performs a comparison operation on the digital image data RGB to control the signal. A data comparator 400 for outputting an AEN, a decoder controller 450 for receiving a decoder enable signal DEN from the control signal AEN and an external device, and outputting a decoder control signal DIS; A decoder which is composed of a plurality of decoder blocks having a plurality of decoders controlled by a control signal DIS, and converts the digital image data RGB into an analog image signal using any one decoder in each decoder block and outputs the analog image signal. And an auxiliary amplifier unit 500 controlled by the control signal and supplying the analog image signal to a plurality of data lines in common. All.

The auxiliary amplifier unit 500 may further include an amplifier unit 550 having a plurality of amplifiers for amplifying an analog image signal output using the one decoder, and the decoder unit in accordance with the control signal AEN. And a first switch unit 600 and a second switch unit 700 for controlling and outputting the analog image signal output from the 800.

The amplifier unit is activated and deactivated by the control signal AEN output from the data comparator 400.

The first switch unit 600 is turned off when the amplifier unit 550 is activated so that an analog image signal output from the decoder unit 800 is supplied to the amplifier unit 550. When the amplifier 550 is deactivated, the amplifier 550 is turned on so that the analog image signal output from the decoder 800 is directly output to the data line.

The second switch unit 700 is turned on when the amplifier unit 550 is activated so that the analog image signal amplified by the amplifier unit 550 is supplied to a data line, and the amplifier unit ( When 550 is deactivated, it is turned off.

In addition, the source driver according to an exemplary embodiment of the present invention may further include a gamma reference voltage generator 6 that receives power from an external source and outputs a gamma reference voltage to the decoder 800.

The gamma reference voltage generator 6 may further include a gray amplifier unit (not shown) that amplifies the gamma reference voltage for each gray level.

2 is a diagram illustrating a detailed configuration of the data comparator.

As can be seen in Figure 2, the data comparison unit,

A clock counter CLK COUNTER 100 that receives a reset signal Reset and a shift clock SCK from an external source and outputs a comparison set signal CMP_SET and a comparison register reset signal CR_Reset and a comparison register shift clock CR_SCK. And a comparison operation unit 220 which receives the digital image data RGB from the outside, is set according to the comparison set signal CMP_SET, and performs a comparison operation, and a processing result of the comparison operation performed by the comparison operation unit. And a comparison register unit 300 that receives and stores the control signal AEN.

The comparison register shift clock CR_SCK allows the comparison register to sequentially store the result of the comparison operation.

The comparison register reset signal CR_Reset resets the comparison register unit again when all the processing results of the comparison operation are stored in the comparison register unit for one horizontal period.

The comparison register section outputs a control signal AEN when the comparison register reset signal is input and according to a result stored in the comparison register section.

3 is a diagram illustrating a detailed configuration of the comparison operation unit.

A source driver according to an exemplary embodiment of the present invention will be described with an example in which the digital image data is 6 bits each of red (R), green (G), and blue (B), and 18 bits in total.

The comparison operation unit may include a first one bit latch configured to store a result performed by the first comparison operator 212a and the first comparison operator 212a that perform a comparison operation on the red (R) data among the digital image data. 214a, a second one-bit latch 214b storing a result of the second comparison operator 212b and the second comparison operator 212b which perform a comparison operation on the green (G) data, and blue (B) a third comparison operator 212c for performing a comparison operation on the data and a third one-bit latch 214c for storing a result performed by the third comparison operator 212c.

The first comparison operator (212a) is a comparison operation for the data (R _{k +1)} for a red color that is input to the data (R _k) and (k + 1) th for a red color that is input to the digital image data of k th Do this.

Likewise, the second comparison operator (212b) is a comparison operation to the data (G _{k +1)} of the green input to the data (G _k) and (k + 1) th of the green input to the k-th, the third comparison computing unit (212c) performs the comparison operation on the data (B _{k +1)} for the blue light input to the (k + 1) th data and (B _k) of the blue input to the k-th.

The one-bit latch feeds the comparison operator enable signal CMPEN back to the comparator when the result of the comparison operation performed by the comparison operator is the same so that the comparison operator is activated, and the subsequent comparison is performed. Allow the operation to proceed.

If the result of the comparison operation performed in the comparison operator is not the same, the one-bit latch does not feed back the result of the comparison operation to the comparison operator, so that the comparison operator is deactivated and stops the subsequent comparison operation.

The comparison operator deactivated as described above is maintained in an inactive state until the comparison set signal CMP_SET is input to the one bit latch again and the one bit latch feeds back the comparison operation enable signal CMPEN.

When the comparison set signal CMP_SET is input to the one bit latch at a predetermined cycle, the one bit latch outputs the stored result CMP of the comparison operation to the comparison register unit 300.

That is, the processing result CMP of the comparison operation performed last before the comparison set signal is input is output to the comparison register section.

Next, the comparison register section will be described with reference to FIG.

4 is a block diagram showing an example of a detailed configuration of the comparison register section 300. As shown in FIG.

As shown in FIG. 4, the comparison register unit 300 includes a plurality of comparison registers that receive a processing result CMP of the comparison operation output from the comparison operation unit 400 and output a control signal AEN.

The plurality of comparison registers are composed of a plurality of register groups allocated one for each period. In FIG. 4, one comparison register unit 300 has a total of 15 register groups 310a, 310b, ..., 310o. The case consists of.

One register group consists of three registers that store the processing result of the comparison operation for each of the red (R), green (G), and blue (B) data in each period.

For example, the first register group 310a includes a register CR1_R that stores the processing result of the first comparison operation on red data, and a register CR1_G that stores the processing result of the first comparison operation on green data. ) And a register CR1_B that stores the processing result of the first comparison operation on the red data.

Similarly, the second register group 310b stores the processing result of the second comparison operation.

Since the configuration of the remaining register groups is also the same as that of the first register group, the description above will be replaced.

The plurality of register groups sequentially store the result of the comparison operation according to the comparison register shift clock CR_SCK.

The comparison register unit receives the comparison register reset signal CR_Reset, resets the register groups, and outputs a control signal AEN for controlling the decoder controller and the auxiliary amplifier unit.

The control signal AEN is individually output for each register group, and is supplied to each NAND gate and the respective amplifier groups provided in the decoder control unit described later.

5 is a block diagram illustrating in detail the configuration of the data register 900, the data comparator 400, the decoder 800, and the decoder controller 400 in the source driver according to the embodiment of the present invention. to be.

As shown in FIG. 5, in the source driver according to the exemplary embodiment of the present invention, the data register unit 900 receives the memory data signal MEM_DATA and the shift clock SCK from the outside and outputs the digital image data RGB. It consists of a plurality of data registers MD1_R, MD1_G, MD1_B, MD2_R, ..., MD240_B, each of which registers a memory data signal of any one of red (R), green (G), and blue (B). It receives an input and outputs digital image data RGB.

In FIG. 5, 240 red registers (R), green (G), and blue (B) s each include 720 data registers. However, the present invention is not limited thereto.

In addition, the data register unit 900 is composed of a plurality of register blocks (910a, 910b, ..., 910o) having a plurality of data registers.

In FIG. 5, the total 720 data registers are composed of 15 data register blocks, and one data register block is composed of 16 data registers for each of red (R), green (G), and blue (B). do.

Each of the data registers outputs digital image data according to a signal MEM_DATA sequentially input from the outside.

The digital image data RGB is output to a decoder 800 and a data comparator 400 including a plurality of decoders.

Each of the plurality of decoders is connected to correspond to one data register, and the decoder unit 800 includes a plurality of decoder blocks 810a, 810b, ..., 810o having a plurality of decoders.

Each of the decoder blocks corresponds to each of the data register blocks.

That is, as shown in Figure 5, the decoder unit is provided with a total of 720 decoders to correspond to each of a total of 720 data registers, it is composed of 15 decoder blocks corresponding to each of the 15 data register blocks.

In addition, the decoder 800 is controlled by a decoder control signal DIS input from a decoder controller (not shown), and receives a gamma voltage GMA output from a gamma reference voltage generator (not shown). An analog image signal corresponding to the digital image data RGB is output.

In addition, the digital image data input to the data comparison unit 400 functions as an input signal of a comparison operation performed in the data comparison unit.

The decoder controller 450 may be a plurality of NAND gates that output the decoder control signal DIS through the control signal AEN output from the data comparator and the decoder enable signal DEN input from the outside. It is composed.

Each of the NAND gates corresponds to each of a plurality of register groups constituting the comparison register unit of the data comparison unit.

Each of the NAND gates corresponds to each of the plurality of decoder blocks as shown in FIG. 6, and is connected to the other decoders except any one of the decoder blocks to control whether the decoder is activated.

That is, one decoder not connected to the decoder controller in the decoder block is always active regardless of a decoder control signal, and the decoders connected to the decoder controller are controlled by a decoder control signal DIS output from the decoder controller. Controlled.

Therefore, when the result of the comparison operation performed in the data comparator is the same, only one decoder that is not connected to the decoder controller is driven in the corresponding decoder block to output an analog image signal, and the other decoders are inactivated by the decoder control signal. do.

7 is a block diagram illustrating a decoder unit and an auxiliary amplifier unit in a source driver according to an embodiment of the present invention.

As shown in FIG. 7, the auxiliary amplifier unit 500 includes an amplifier unit 550 composed of a plurality of amplifier groups and a control signal which receives a control signal to control an analog image signal and commonly outputs it to a plurality of data lines. It consists of a first switch unit 600 and a second switch unit 700.

Each of the amplifier groups corresponds to each of the decoder blocks, and includes three amplifiers for amplifying analog image signals for each of red (R), green (G), and blue (B) output from the decoder block.

The first switch unit 600 is composed of a plurality of switches, and the switch is provided to be connected to one decoder which is not controlled by the decoder controller 450 in each decoder block.

The second switch unit 700 is composed of a plurality of switches, the switch is provided to be connected to each of all decoders.

The first switch unit 600 and the second switch unit 700 are controlled by the control signal and have opposite activation states.

For example, when the result of the comparison operation is the same, a control signal of a high signal is output from the first register group 310a included in the comparison register unit 300, and the decoder controller may generate a first decoder block ( A decoder control signal for deactivating the other decoders except one decoder is output to 810a.

Therefore, the analog image signal is output from the first decoder block 810a through one decoder not connected to the decoder controller.

In addition, the switch connected to the first decoder block in the first switch unit 600 is turned off by the control signal of the high signal, and the analog image signal corresponds to the decoder block. It is input to the first amplifier group 551a. At this time, the switches of the second switch unit 700 connected to the first decoder block are all turned on.

The analog image signal input to the first amplifier group 551a is amplified and then commonly output to the plurality of data lines through the second switch unit 700.

In the above, the case where the source driver according to the embodiment of the present invention has a plurality of register groups and decoder blocks and a plurality of amplifier groups has been described.

The technical idea of the present invention may also be applied to the case of having one register group and decoder block and one amplifier group.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

In the liquid crystal display according to the embodiment of the present invention,

A liquid crystal display panel for displaying an image, a source driver and a gate driver for applying a signal for driving the liquid crystal display panel, and a backlight unit for applying a predetermined light to the liquid crystal display panel; ,

The source driver may be configured as a source driver according to an embodiment of the present invention described above.

Next, a method of driving a source driver according to an embodiment of the present invention will be described with reference to the accompanying drawings.

A method of driving a source driver according to an embodiment of the present invention,

Sequentially outputting the digital image data to the data comparator, performing a comparison operation on the digital image data sequentially input from the data comparator, and controlling the control signal according to the result of the comparison operation to the decoder controller and the auxiliary amplifier. Outputting to a decoder; outputting a decoder control signal from the decoder controller to a decoder unit comprising a plurality of decoder blocks having a plurality of decoders; and using any one decoder in each decoder block according to the decoder control signal. And converting the digital image data into an analog image signal and outputting the same, and supplying the analog image signal to a plurality of data lines in common through an auxiliary amplifier unit.

In the following, for convenience of description, a case of a source driver having 720 output channels will be described as an example.

In addition, the 720 output channels include 240 output channels for each of red (R), green (G), and blue (B).

In the step of sequentially outputting the digital image data to the data comparator, the memory data is sequentially input to the data register by the shift clock, and the data register is sequentially output the digital image data to the data comparator.

In the performing of the comparison operation, a comparison operation is performed on a k th input data and a k + 1 th input data with respect to the digital image data sequentially input to the data comparator.

In addition, the performing of the comparison operation may include storing a result of the comparison operation in a one-bit latch.

In addition, the performing of the comparison operation may include feeding back a signal for activating the comparison operator to the comparison operator according to the result of the comparison operation.

If the result of the comparison operation is the same, the comparison operator outputs high, and the output signal is stored in a one bit latch.

The one-bit latch, which has received high, feeds back a signal to the comparator to activate the comparator so that the comparator performs a subsequent comparison operation.

If the result of the comparison operation is not the same, the comparison operator outputs a low, and the output signal is stored in a one bit latch.

As such, the one-bit latch that receives the row does not feed back a signal to the comparator, thereby deactivating the comparator.

The deactivated comparison operator remains inactive until the next comparison set signal is input, and is activated again when the comparison set signal is input to perform the comparison operation on the digital image data.

When the compare set signal is input, the result stored in the one bit latch is output to the compare register section.

More specifically, the result of the comparison operation performed at the comparison operator last before the comparison set signal is input is sequentially stored in the plurality of register groups constituting the comparison register section. Therefore, a high signal is output to the comparison register section only when the comparison operation results before the comparison set signal is input are the same.

The outputting of the control signal may include outputting a control signal according to a result of the comparison operation performed by the data comparator to the decoder controller and the auxiliary amplifier.

That is, each of the plurality of register groups constituting the comparison register unit outputs a control signal according to the stored result.

The outputting of the decoder control signal may include outputting a decoder control signal for controlling the decoder unit from a decoder controller receiving the control signal and a decoder enable signal input from the outside.

For example, when the decoder enable signal and the control signal are both high, each decoder controller is configured of a plurality of NAND gates corresponding to each register group of the comparison register unit. Outputs a decoder control signal that deactivates the decoder.

In addition, each of the NAND gates of the decoder controller corresponds to each of the decoder blocks constituting the decoder, and the decoders other than any one of the plurality of decoders constituting the decoder block are connected to and controlled by the NAND gate.

The outputting of the analog image signal and the common output of the analog image signal to the plurality of data lines through the auxiliary amplifier unit may include any one of the plurality of decoders constituting the decoder unit. When the decoders receive the same digital image data in the decoder block, only one of the decoders is activated to output an analog image signal in common to a plurality of data lines.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

As described above, the source driver and the method of driving the source driver according to an embodiment of the present invention perform a comparison operation on the digital image data, and any one decoder for decoders that receive the same digital image data as a result of the comparison operation. By outputting the analog image signal to a plurality of data lines in common using only, the power consumption can be reduced.

In addition, it is possible to increase the driving force through the auxiliary amplifier unit without increasing the large area, it is possible to implement a high performance miniaturized source driver.

Claims (19)

A data comparator which receives digital image data, performs a comparison operation, and outputs a control signal according to a result of the comparison operation; A decoder controller for receiving a control signal output from the data comparator and outputting a decoder control signal; A decoder unit including one or a plurality of decoder blocks having a plurality of decoders and converting the digital image data into an analog image signal using one decoder in each decoder block according to the decoder control signal; A control unit controlled by the control signal and including an auxiliary amplifier unit for supplying the analog image signal to a plurality of data lines in common; The auxiliary amplifier unit includes a plurality of amplifier groups including a plurality of amplifiers, and a first switch unit and a second switch unit controlled by the control signal to output the analog image signal to a plurality of data lines in common. Source driver, characterized in that. delete The method of claim 1, And the first switch unit comprises a plurality of switches, each switch being connected to one decoder for outputting an analog image signal from the decoder block. The method of claim 1, The second switch unit comprises a plurality of switches, each switch is connected to all the decoders constituting the decoder unit. The method of claim 1, And the first switch unit and the second switch unit are controlled to have opposite activation states. The method of claim 1, Each of the amplifier groups comprises three amplifiers for amplifying analog image signals for red (R), green (G), and blue (B), respectively. The method of claim 1, The source driver includes a gamma reference voltage generator, The gamma reference voltage generator further includes a gray amplifier amplifying the gamma reference voltage according to each gray level. delete The method of claim 1, The data comparator receives a reset signal and a shift clock from an external source, a clock counter for outputting a comparison set signal, a comparison register shift clock and a comparison register reset signal, a comparison operation unit for receiving a digital image data and performing a comparison operation; A source driver comprising a comparison register section for storing a processing result of a comparison operation performed in the comparison operation section. The method of claim 9, And the comparison operation unit comprises a plurality of comparison operators and a one-bit latch dependent on each of the comparison operators. The method of claim 10, And the one bit latch is set by the comparison set signal. The method of claim 10, And the one bit latch feeds back a comparator enable signal to the comparator. The method of claim 9, And the comparison register section comprises a plurality of register groups having a plurality of registers. The method of claim 1, The decoder control unit includes a decoder enable signal input from an external device and a plurality of NAND gates controlled by the control signal. The method of claim 14, And wherein each of the NAND gates corresponds to each of the decoder blocks. The method of claim 15, Each of the NAND gates is connected to a decoder other than a decoder for outputting the analog image signal in a corresponding decoder block. delete delete A liquid crystal display panel for displaying an image; A source driver and a gate driver for applying a signal for driving the liquid crystal display panel; It comprises a backlight unit for applying a predetermined light to the liquid crystal display panel, The liquid crystal display device of claim 1, wherein the source driver comprises a source driver according to any one of claims 1, 3, 7, and 16.

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