JP2734570B2 - Liquid crystal display circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display circuit for driving a liquid crystal display, and more particularly, to a liquid crystal display circuit capable of performing gradation display.

2. Description of the Related Art As a liquid crystal display circuit for performing gradation display (shading display) of a liquid crystal display, there is known a circuit that changes the number of times of frame display according to gradation. In other words, this liquid crystal display circuit performs display in units of 8 frames when performing, for example, 8 gray scale display. When the gray scale is “0”, no display is performed, and when the gray scale is “1”, 8 gray scales are displayed. The display is performed once for each frame, the display is performed twice for eight frames when the gradation is "2", and the display is performed for all the eight frames when the gradation is "7". .

“Problem to be Solved by the Invention” However, according to such a liquid crystal display circuit, there is a drawback that flicker (flicker) appears on the display, making it difficult to see.

The present invention has been made in view of the above circumstances, and has as its object to provide a liquid crystal display circuit capable of performing gradation display with almost no flicker.

[Means for Solving the Problems] The present invention relates to a liquid crystal display that performs gradation display by controlling a number of frame displays in one cycle corresponding to a plurality of bits of display data with a plurality of frames as one cycle. In the circuit, the driving voltage for frame display is multi-staged,
A drive voltage output circuit that outputs the drive voltage value differently between successive display frames, and an electrode drive signal corresponding to the display data value at a frame timing corresponding to the output voltage value of the drive voltage output circuit. And a driving signal output circuit for outputting.

According to the present invention, gradation display is performed by both the voltage control for changing the drive voltage for each frame and the frame time control of how many frames out of a plurality of frames are to be displayed. As a result, flicker based on frame time control can be prevented, and multi-gradation display can be performed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a liquid crystal display circuit according to an embodiment of the present invention. The liquid crystal display circuit shown in FIG.
It is composed of Reference numeral 3 denotes a liquid crystal display driven by the liquid crystal display circuit. In this example, seven scanning electrodes X1 to X7 and five signal electrodes Y1 to Y5 are provided. The electrode drive circuit 2 is a conventionally known circuit.

Next, in the gradation control circuit 1, T1 is a frame signal FLM indicating the start time of frame scanning of the liquid crystal display 3.
(Pulse signal) is applied, T2 is a terminal to which a polarity switching signal M described later is applied, and T3 to T5 are terminals to which display data (3 bits) is applied. Reference numeral 5 denotes an AND gate, and reference numeral 6 denotes a 2-bit counter. The counter 6 is a counter that counts up the frame signal FLM. When the count output becomes “2”, the “1” signal is output from the AND gate 5 and reset.
That is, the counter 6 is configured as a ternary counter, and its count output changes to “0”, “1”, “2”, “0”... Every time the frame signal FLM is supplied. 7 is a decoder for decoding the output of the counter 6,
Reference numerals 8 to 10 denote analog switches whose opening and closing are controlled by the output of the decoder 7. 11 is a voltage dividing circuit, which is a power supply voltage Vc
Voltages Va1 to Va3 obtained by dividing (+ 17V) by a resistor are output. Here, the voltages Va1 to Va3 are set so that the display density when each voltage is supplied is approximately 4: 2: 1, and has a relationship of Va1>Va2> Va3. Reference numerals 12 to 14 denote AND gates, and reference numeral 15 denotes an OR gate. Output data of the OR gate 15 is supplied to the electrode driving circuit 2 as electrode driving data D.

Next, in the power supply driving circuit 2, T4 is a latch clock.
A terminal to which CL is applied, and T5 is a terminal to which the shift clock CP is applied. Reference numeral 17 denotes a 5-bit shift register equal to the number of signal electrodes of the liquid crystal display 3, and reads output data of the OR gate 15 based on the shift clock CP. Data latch 18 reads output data of shift register 17 5
This is a bit latch, and reads data based on a latch clock CL that is output one pulse every five pulses of the shift clock CP. That is, every time 5 pieces of electrode drive data D (5 bits) are read into the shift register 17, the data D is read into the data latch 18. Then, the read data is supplied to the selection switch 19. The selection switch 19 has five input terminals to which five outputs of the data latch 18 are supplied, respectively, and first and second output terminals provided corresponding to each of the input terminals (ie, When a single input terminal is supplied with “1”, “1” and “0” are output from the first and second output terminals corresponding to the input terminal, respectively. When "0" is supplied to one input terminal, "0" and "1" are output from the corresponding first and second output terminals. The output of the selection switch 19 is supplied to each transfer gate TG, and controls the opening and closing of each transfer gate TG. That is, when "1" is supplied from the selection switch 19 to the transfer gate TG, the gate TG is opened, and when "0" is supplied, the gate is closed.

Reference numeral 21 denotes a voltage dividing circuit which outputs voltages V1 to V4 (V1>V2>V3> V4) obtained by dividing the voltage Vs supplied through any of the analog switches 8 to 10 by a resistor. 22 is an inverter for inverting the polarity inversion signal M, and 23 is a shift register. This shift register 23 is a scanning electrode of the liquid crystal display 3.
A 7-bit shift register having the same number as X1 to X7, the frame signal FLM is read by the latch clock CL, the first output terminal becomes "1", and then the second to seventh output terminals at the timing of the latch clock CL. Sequentially become "1", then the frame signal FLM is read again by the latch clock CL, the first output terminal becomes "1", and this operation is repeated thereafter. Reference numeral 24 denotes a selection switch configured similarly to the selection switch 19 described above. The selection switch 24 has seven input terminals for receiving the output of the shift register 23, and has fourteen output terminals corresponding to the respective input terminals. The opening and closing of the transfer gate TG is controlled by the signal of the output terminal.

Next, the operation of the above-described power supply drive circuit 2 will be described. The description will be made on the assumption that the polarity inversion signal M is “1” and the output of the inverter 22 is “0”.

First, power supply drive data D for displaying the first row of dot rows of the liquid crystal display 3 is sequentially output from the gradation control circuit 1 at the timing of the shift clock CP, and is read into the shift register 17. When the reading is completed, the data in the shift register 17 is read into the data latch 18 by the latch clock CL, and the selection switch
Output to 19. Thus, the ground potential is supplied to the signal electrode Y corresponding to the output terminal of the "1" signal of the data latch 18 and the voltage V3 is supplied to the signal electrode Y corresponding to the output terminal of the "0" signal via the transfer gate TG. Is done. On the other hand, when the data in the shift register 17 is read into the data latch 18, the frame signal FLM is read into the shift register 23, whereby “1” is output from the first output terminal of the shift register 23 to the second to second bits. "0" is output from each of the seventh output terminals.
As a result, the voltage Vs is applied to the scan electrode X1 via the two transfer gates TG, and the voltage V4 is applied to the electrodes X2 to X7 via the two transfer gates TG.

Assuming now that "1" is output from the second output terminal of the data latch 18 and "0" is output from the other output terminal, Vs-0 = Vs between the scan electrode X1 and the signal electrode Y2. A voltage is applied, whereby a dot at the intersection of the electrodes X1 and Y2 is displayed. On the other hand, the scanning electrode X1 and the signal electrodes Y1, Y
A low voltage of V4−V3 is applied between 3 and Y5. In this case, each dot at the intersection of the two electrodes is not displayed.

Next, while the display of the first row is performed, data D for displaying the second row is sequentially read into the shift register 17. When the reading is completed, the data in the shift register 17 is transferred to the data latch 18, and the second output terminal of the shift register 23 becomes "1". A column is displayed, and the above operation is repeated thereafter.

By the way, as is well known, the liquid crystal deteriorates rapidly when a direct current is applied, and therefore, it is necessary to periodically change the polarity of the voltage applied to the liquid crystal. The polarity switching signal M is a signal for this purpose, and repeats “1” and “0” at a constant cycle (for example, the same cycle as the frame signal FLM). When the signal M is "1", the above voltage is applied between the electrodes. On the other hand, the signal M
Is “0”, when the output of the data latch 18 is “1”, a voltage of 0−Vs = −Vs is applied between the electrodes. When the output of the data latch 18 is “0”, V1− The power of V2 is applied between the electrodes, and the absolute value of the voltage applied between the electrodes becomes equal to the case where M = "1".

Next, the operation of the gradation control circuit 1 will be described. First, the operation principle of the gradation control circuit 1 is as follows. That is, first, the gradation is controlled by changing the voltage Vs supplied to the electrode drive circuit 2 in three stages (Va1 to Va3). Also, display is performed in units of three frames, and when the display density is low, only one or two frames are displayed. Then, gradation control is performed by both the voltage control and the frame control. The details will be described below.

First, the count output of the counter 6 is the frame signal FL
Every time M is supplied, it changes from 0 → 1 → 2 → 0 → 1 ...
Therefore, the output terminals <0>, <1>,
<2> is sequentially repeated for each frame to become “1”. As a result, the analog switches 8 to 10 are sequentially and repeatedly opened, and the voltage Vs changes from Va3 to Va2 to Va1 to Va3 to Va2 to each frame. Hereinafter, the count output of the counter 6 is referred to as a frame number. On the other hand, the display data is supplied to the AND gates 12 to 14 via the terminals T3 to T5, and these AND gates are ANDed with the output of the decoder 7,
Further, the outputs of the AND gates 12 to 14 are supplied to the OR gate 15, and the output of the OR gate 15 is output as the electrode drive data D.

Now, let the signal shown in FIG. 2 (a) be the frame signal FLM and (b) be the count output of the counter 6. In this case, when the display data is “1” (“0,0,1”), the data D
Is "1" only in the 0th frame, as shown in FIG. 3C, and therefore, display is performed only in the 0th frame. In the 0th frame, the voltage Vs becomes Va3. FIG. 4D shows the drive voltage Vs. The drive voltage Vs shown here indicates only a frame in which display is performed (when data D is "1"), and no display is performed (data D is "0").
In the case of), the frame is indicated by 0 V, and hereinafter, the same expression is used. That is, the display data “1” is displayed once in three frames and is driven at the lowest voltage. Therefore, the display density decreases. Next, when the display data is “2” (“0, 1, 0”), the data D becomes “1” only in the first frame as shown in FIG.
Display is performed only in the first frame. In addition, this first
In the frame, the voltage Vs becomes Va2. FIG. 6F shows the drive voltage Vs. That is, the display data "2" is displayed once in three frames and is driven by a medium voltage.
Therefore, the display density is higher than that in the case of the display data “1”. Next, when the display data is "3"("0, 1, 1"), the data D and the drive voltage Vs are respectively shown in FIG.
(H). That is, in this case, display is performed in the 0th and 1st frames, and the drive voltage Vs is set to Va.
3 and Va2. Therefore, the display density is obtained by adding the display density of the display data “1” and the display data “2”. Similarly, in accordance with the display data "4" to "7", the display is performed by the display timing and the drive voltage Vs shown in FIGS.

As described above, in the above embodiment, gradation control is performed by both the number of display frames and the drive voltage.
As a result, even when the number of gradation control steps is large, the number of control steps for the number of display frames can be reduced, and thus flicker can be minimized.

[Effects of the Invention] As described above, according to the present invention, a plurality of frames are defined as one cycle, and the number of times of frame display in one cycle is controlled in accordance with a plurality of bits of display data, thereby enabling gradation display. In a liquid crystal display circuit, a drive voltage for frame display is multi-staged, and a drive voltage output circuit for outputting the drive voltage value differently between successive display frames, and an output voltage of the drive voltage output circuit Since a drive signal output circuit that outputs an electrode drive signal corresponding to the value of the display data at a frame timing corresponding to the value is provided, it is possible to perform multi-tone display with almost no flicker. is there.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention, and FIG.
The figure is a timing chart for explaining the operation of the embodiment. 1 ... gradation control circuit, 6 ... counter, 7 ... decoder, 8 to 10 ... analog switches, 12 to 14 ... AND gate, 15 ... OR gate.

Claims (1)

(57) [Claims] 1. A liquid crystal display circuit for performing gradation display by controlling a number of frame displays in one cycle corresponding to a plurality of bits of display data in a plurality of frames as one cycle. A drive voltage output circuit that multi-steps the drive voltage and outputs different drive voltage values between successive display frames; and a value of the display data at a frame timing corresponding to an output voltage value of the drive voltage output circuit. And a drive signal output circuit for outputting an electrode drive signal corresponding to the above.