JPH01295228A - Liquid crystal panel driving circuit - Google Patents

Abstract

PURPOSE:To allow varying of effective driving voltages without varying the voltages to be impressed to a liquid crystal by providing a zero bias period in respective back plate periods and setting this zero bias period digitally variably according to the operation of a bright key. CONSTITUTION:The timing signal formed by a display control circuit 11 is sent to an A/D conversion circuit 12, a segment driving circuit 23 and a common driving circuit 24. The segment driving circuit 13 reads video data D1-D3 and forms segment signals Y1-Ym. The common driving circuit 14 selects liquid crystal driving voltages V0, V2, V4 and forms common signals X1-Xn. The zero bias period, i.e., the period of maintaining the segment voltage and the common voltage at the same voltage is provided to the segment signals Y1-Ym and the common signals X1-Xm in the respective back plate periods. This zero bias period is varied according to the contents of a counter 21 in which a bright adjustment signal is set. The bright adjustment by varying the effective driving voltages is thereby enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal panel drive circuit that digitally performs brightness adjustment on a liquid crystal panel.

[Prior Art and Problems to be Solved] In recent years, liquid crystal panels have generally been used as display units for small portable televisions and the like. This liquid crystal panel has a characteristic that its brightness (transmittance) changes depending on the effective value of the applied voltage, so when adjusting the brightness, conventionally the applied voltage value was adjusted linearly using a variable resistor. The effective drive voltage is changed by changing the voltage. FIG. 11 shows an example of the conventional liquid crystal drive voltage waveform, and V2
Positive driving voltages VO, Vl and negative driving voltages V8. V4 (the V4 voltage is omitted in the figure) is generated, and Vl is applied to the segment electrode.

V3 voltage is applied, and the common electrode is VO,
V2 voltage and V2. V4 voltage is applied alternately. In this case, the segment drive voltage is set for one hack pre-period (
VO, V4 . Brightness adjustment is performed by changing the effective drive voltage by varying the voltage levels of Vl and V3.

As mentioned above, in the conventional brightness adjustment method, it is necessary to configure the LCD drive voltage generation circuit so that the voltage value can be varied, which increases the circuit scale and requires that each device operate normally over a wide range of power supply voltages. There was a problem in that the device had to operate in the same way, and was subject to significant circuit constraints.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal panel drive circuit that can vary the effective drive voltage without varying the applied voltage and can digitally adjust brightness while maintaining the optimum bias. do.

[Means and Effects] The present invention provides a zero bias period (a period in which the segment voltage and the common voltage are the same voltage) during each backplate period for the segment signal and the common signal, and uses this zero bias period as the bright adjustment signal. Brightness adjustment is performed by varying the effective drive voltage according to the contents of the counter set.

Further, in the present invention, when the selection time of each common electrode is set to the M back plate period, the zero bias period of the segment signal and the common signal is varied according to the contents of the counter to which the bright adjustment signal is set. By setting each zero bias period in the M backplate period to a value shifted by one step by the number of periods corresponding to the setting value of the counter, fine brightness adjustment can be performed.

Furthermore, the present invention includes a non-volatile memory that stores updated data each time the setting contents of the counter are updated by operating a bright key, and stores the stored contents of the memory in the counter when the power is turned on. It is designed to reproduce the bright state when the power is turned off.

[First Embodiment] The present invention will be described in detail below with reference to the drawings. FIG. 1 shows the overall schematic configuration of a liquid crystal panel drive circuit. In the same figure, 11 is a display control circuit;
A bright adjustment signal is input by operating the bright key provided at 0.

The display control circuit 11 generates brightness modulation pulses P1 to P3.
The frame signal ff, the zero bias timing signal and various clock pulses are generated.As for the zero bias timing signal EC, the ratio between high level and low level can be variably set by the bright adjustment signal from the key human power section 10. The generation circuit for this zero bias timing signal r will be described in detail later.The timing signal created by the display control circuit 11 is then transmitted to the A/D conversion circuit 12. It is sent to the circuit 13 and the common drive circuit 14.

The A/D conversion circuit 12 converts the analog video signal into, for example, 3-bit digital data D1 to D3 in accordance with the sampling signal φS from the display control circuit 11, and outputs the data to the segment drive circuit 13. This segment drive circuit 13
, brightness modulation pulses P1 to P3 are sent from the display control circuit 11.
．． Frame signal 7; r, zero bias timing signal EC
and various clock pulses are raised to L''r, and the liquid crystal driving voltage generation circuit 15 generates liquid crystal driving voltages V1...V2.
, V3 is given.

” The segment I drive circuit 13 is the display control circuit 11.
The A/D conversion circuit operates according to various timing signals from the LCD panel 16, reads the video data D] to D3 from the A/D conversion circuit [2], creates segment drive signals Y1 to Ym of, for example, eight gradations, and drives the segment electrodes (signals) of the liquid crystal panel 16. electrode).

The liquid crystal drive voltage generation circuit 15 includes liquid crystal drive voltages VO,
V1. ．． V2. V3. V4 is generated and Vl.

V2. V3 voltage is output to the segment drive circuit 13, and V3 voltage is output to the segment drive circuit 13.
O, V2. The V4 voltage is output to the common drive circuit 14.

The common drive circuit 14 also includes a display control circuit 11.
From frame signal Oka r, zero bias timing signal EC
, a vertical timing signal SR synchronized with a vertical synchronization signal, and a shift clock Oka02. The common drive circuit 14 reads the vertical timing signal SR given from the display control circuit 11 using the shift clock Oka n2, shifts it sequentially, and adjusts the liquid crystal drive voltage V from the liquid crystal drive voltage generation circuit 15 according to the shift output.
Q.

V2. V4 is selected to create common drive signals X1 to Xn, and the common electrodes of the liquid crystal panel 16 are sequentially driven. '' Voltages VO and V4 are common electrode selection voltages, and v2 is a non-selection voltage.

Therefore, the zero bias timing signal generation circuit provided in the display control circuit IJ is constructed as shown in FIG. 2. In the figure, 21 is a 3-bit (octal) up/ In the down counter, up/down signals U/D and clock pulses CK are input from the key manual section 0 in response to the operation of the bright key.The above counter 21
counts up or down according to the brightness adjustment signal from the key human power unit 10, and inputs the count output Q] to Q3 to the PWM (pulse width modulation) circuit 22. As shown in FIG. 3, this PWM circuit 22 has one period of a frame signal 7; Pulse width modulation is performed using the width as a standard. This pulse width modulated signal is output from the PWM circuit 22 as a zero bias timing signal EC, and the ratio between the high level period t1 and the low level period t2 of this timing signal EC is determined by the count value of the counter 21. It is determined. That is, in the PWM circuit 22, the t1 period is set in proportion to the count value of the counter 21.

The zero bias timing signal EC created in the PWM circuit 22 is sent to the segment drive circuit 13 and the common drive circuit 14 as described above. As shown in FIG. 3, the segment drive circuit 13 divides one backplate period F into n equal parts (in this embodiment, eight parts), and during the t1 period when the zero bias timing signal EC is at a high level, The segment electrodes of the liquid crystal panel 16 are driven by changing the application time ratio of the V1 voltage and the (3) voltage in accordance with the gradation signal for each divided period. Then, during the t2 period when the zero bias timing signal EC is at a low level, the v2 voltage (non-selected) is applied to the segment electrode.

On the other hand, as shown in FIG. 3, the common drive circuit 14 is connected to
During one period, the voltage ``0'' or the voltage ``4'' is selected as the common drive signals X1 to Xn, and during the t2 period when the signal EC is at a low level, the V2 voltage is applied to the common electrode. As a result, the liquid crystal panel 16 receives the zero bias timing signal E.
In the t1 period of C, the display is driven at a gradation according to the video signal, and in the t2 period, both the segment drive signal and the common drive signal are at the V2 level, and the display is driven with zero bias.

The ratio of the t1 period to the t2 period in the above zero bias timing signal ``changes according to the bright adjustment signal, and t
] Bright adjustment is performed by changing the effective drive voltage depending on the ratio to the off period t2 period.

The details of the segment drive circuit 13 and common drive circuit 14 will be explained below.

FIG. 4 shows the configuration of the segment drive circuit 13 = 1
0 = as shown. In the figure, 31 is a data latch clock generation circuit, which receives an input timing signal ST synchronized from the display control circuit 1 at the start of each backplate period F.
Tarotsuku Pulse Oka with I”.

≠2 is input. Data latch clock generation circuit 31
The input timing signal STI is a tarok pulse, 1.
, i, and then shifted sequentially to generate data latch clocks φs1 to φsm. The data latch clocks φs1 to φsm outputted from the data latch clock generation circuit 31 are sent to a data latch circuit 32 of 3 bits×m stages.

Furthermore, when the segment drive circuit 13 is constituted by a plurality of LSIs, the clock STO outputted from the final stage of the data latch clock generation circuit 31 is sent to the next stage LSI as an input timing signal STI. The segment drive circuit 13 includes an A/D conversion circuit 12
The video data D1 to D3 provided from the input terminals are sequentially latched in synchronization with latch clocks φs1 to φsm. The data latched by this data latch circuit 32 is transmitted by a timing signal 7 given every one back plate period F;
It is sent to the gradation signal generation circuit 33 in synchronization with n. Also,
This gradation signal generation circuit 33 receives a frame signal Oka f.

Timing signals 'l'0.7;n, #Ns are given.

The gradation signal generation circuit 33 generates gradation signals y1 to ym according to the data latched by the data latch circuit 32, as will be described in detail later, and outputs them to the analog multiplexer 35 via the level shifter 34.

This analog multiplexer 35 has Vl, V
3 voltages are supplied via the control circuit 36.

The V1/V3 control circuit 36 is supplied with a zero bias timing signal as a control signal.

The Vl/V3 control circuit 36 supplies the Vl and ■3 voltages to the analog multiplexer 35 during the t1 period when the zero bias timing signal EC is at a high level, and supplies the V2 voltage during the t2 period when the zero bias timing signal EC is at a low level. Therefore, the analog multiplexer 35 outputs the segment drive signals -12 to Y1 to Ym in accordance with the gray scale signal provided from the gray scale signal generation circuit 33 via the level shifter 34 during the t1 period of one backplane period F, and outputs the segment drive signals -12 to Y1 to Ym during the t2 period. During the period, the V2 voltage is output as the segment drive signals Y1 to Ym.

FIG. 5 shows details of one system in the data latch circuit 32 and the gradation signal generation circuit 33. In the figure, reference numeral 328 denotes a latch circuit for stages (3 bits) in the data latch circuit 32, into which video data D1 to D3 from the A/D conversion circuit 12 is input.

The latch circuit 32a reads the video data D1 to D3 using the latch clock φsi from the data latch clock, and outputs it in synchronization with the timing signal 7;n. This timing signal In is a signal that is output every one back plate period as shown in the timing chart of FIG. Each bit output read from the latch circuit 32a is output from OR circuits 41a to 4 in the gradation signal generation circuit 33.
1c.

Furthermore, brightness modulation pulses P1 to P3 shown in FIG. 6 are input to the OR circuits 41a to 44c. The output signals of the OR circuits 41a to 41c are input to the reset terminal R of the flip-flop 43 via the NAND circuit 42.

This flip-flop 43 includes a pair of NAND circuits 43a
, 43b, and a timing signal <
6NS is input. The output signal of the flip-flop 43 is inputted together with the frame signal 1' to an exclusive OR circuit (hereinafter abbreviated as EX-OR circuit) 44,
The output of this EX-OR circuit 44 is taken out as a gradation signal yi.

Various timing signals used in the gradation signal generation circuit 33 are set as shown in FIG.

That is, the timing signal JN is outputted at timings that equally divide the backplate period F into eight, and the timing signal≠C is outputted six times between each timing signal <6NS. Then, brightness modulation pulses P1 to P3 are created by sequentially dividing the frequency of this timing signal Oka c.

Therefore, the video data D1 to D3 are the latch clock φsi
When this latch data is read out in synchronization with the timing signal≠n, the gray scale signal becomes 8 during one back plate period F for this latch data. Output times. In other words, the gradation signal generation circuit 33 receives the latch data D from the latch circuit 32a.
When 1 to D3 are read, first, the timing signal <6N
The flip-flop 43 is set by S, and then the brightness modulation pulse P1 obtained by frequency-dividing the timing signal 7;
~P3 is given to OR circuits 41a to 41c. Then, the video data D1~ held in the latch circuit 32a
OR circuit 4 by D3 and brightness modulation pulses P1 to P3]
, a to 41c become all "1", the output of the NAND circuit 42 becomes "0", and the flip-flop 43
is reset. As described above, the flip-flop 43 is set by the timing signal (15Ns) and then reset after a time corresponding to the video data D1 to D3 has elapsed. Therefore, the time width of the output signal of the flip-flop 43 is The output signal of the flip-flop 43 is outputted as a gradation signal y+ via the EX-OR circuit 44. Since it is repeated several times, a certain video data D] ~
The gradation signal y+ for D3 is output eight times during one backplate. Note that the gradation signal yi is input to the EX-OR circuit 44 together with the frame signal 7;
It is inverted and output in synchronization with the frame signal vf.

As described above, the gradation signal y1 is output from the gradation signal generation circuit 33 eight times during one back play period F, and is sent to the analog multiplexer 35 via the level shifter 34. This analog multiplexer 35 has Vl.
t1 during each backplate period F from the V3 control circuit 36.
VL and V3 voltages are applied during the period, and V2 voltage is applied during the t2 period. Therefore, as shown in FIG. 3, the analog multiplexer 35 outputs the segment drive signal Yi in response to the grayscale signal yj from the first grayscale signal generation circuit 33 during the t1 period, and the v2 voltage is output during the t2 period. is output.

In the example of FIG. 3, a case is shown in which the segment drive signal Yj is output six times during one back play period F.

Next, details of the common drive circuit 14 will be explained with reference to FIG. The common drive circuit 14 is given the liquid crystal drive voltage VO, V4°-16=V2 from the liquid crystal drive voltage generation circuit 15, but the VO lightning voltage P channel MO3)
The V4 voltage is supplied to the power supply line 53a via the transistor 51a and the analog switch 52, and the V4 voltage is supplied to the N channel M
O8) Supplied to the power line 53a via the transistor 51b and analog switch 52. Further, the V2 voltage is supplied as is to the power supply line 53b, and is also supplied to the power supply line 53a via the analog switch 54. Then, the MOS transistors 51a and 51b
A frame signal 1r is inputted to the gate of , via a level shifter 55 . That is, the MOS transistors 51a and 51b are alternately controlled on/off by the frame signal 1, and either the VO lightning voltage or the V4 voltage is alternately selected and input to the analog switch 52 every frame. Further, the gate of the analog switch 54 is supplied with a zero bias timing signal EC or an inverter 56.
The output of the level shifter 57 is further input to the gate of the analog switch 52 via an inverter 58. Due to the zero bias timing signal EC, the analog switch 52 is turned on during the t1 period.
is controlled on and the VO or V4 voltage is applied to the power supply line 5.
3a, the analog switch 54 is turned on during the t2 period, and the v2 voltage is supplied to the power supply line 53a.

Analog switches 61a, Blb, 62a, 62b are connected to the power supply lines 53a, 53b in correspondence with the common electrodes of the liquid crystal panel 16, respectively.
-... are connected. Analog switches 8La, Glb, . . . provided on the power line 53a side, and analog switch 6 provided on the power line 53b side.
2a, 82b.

. . . are commonly connected on the output end side. The outputs of the flip-flops 64a, 84b, . . . forming the shift register 63 are connected to the gates of the analog switches 61a, 61b, .
5a.

65b, . . . after level adjustment. In addition, the analog switches 62a, 82b, . . .
The level shifter [i5a, 65b, ・
. . are provided via inverters 66a, eeb, . The shift register 63 includes flip-flops 64a whose number of stages corresponds to the number of common electrodes of the liquid crystal panel 16.

= 18 - 64b, . . . , and the vertical timing signal SR is inputted via the inverter 67 to the data input terminal (2) of the first stage flip-flop 64a.

Further, a clock pulse in2 is inputted to the clock terminal CK of the flip-flops B4a, B4b, . . . via an inverter 68. The above shift register 63
reads the vertical timing signal SR, which is obtained by M in synchronization with the vertical synchronization signal, into the first stage flip-flop 64a by the clock pulse Oka 02, and thereafter by the clock pulse 7;
Shifts sequentially in synchronization with n2. Flip-flops 64a and e4 forming this shift register 63
The output signal of b, causes the analog switch Gla,
61b, -1fi2a, G2b, are on/off controlled and connected to the power line 53a or the power line 53b.
The voltage of the common signal XI is selected.

X2. It is extracted as...

The common drive circuit 14 configured as described above operates according to the frame signal 7;
．． B is controlled on/off, and either the Vo lightning voltage or the V4 voltage is alternately selected every frame and input to the analog switch 52. On the other hand, depending on the zero bias timing signal "lower", the analog switches 52 and 54
or on/off control. That is, during the t1 period when the zero bias timing signal 100 is at a high level, the analog switch 52 is turned on, and the VO or V4 voltage is supplied to the power supply line 53a. Now, when the frame signal vf is at a low level and the VO8)-transistor 51a is on, that is, when it is output to the vO main voltage power supply line 53a, the vertical timing signal SR is input to the shift register 63 and the flip-flop When the voltage is read into the flip-flop 84a, the output of the flip-flop 64a becomes high level, the analog switch G1a is turned on, the analog switch 62a is turned off, and the common signal X1 is selected as the voltage Vo as shown in FIG. is output. Other common signals X2. X3.・Analog switch 61b, . . . side is off, analog switch 62
Since the b and - sides are turned on, the voltage (2) (non-selected) applied to the power supply line 53b is selected and output. After that, when the period t1 passes and the period t2 begins, the zero bias timing signal EC becomes low level, the analog switch 52 is turned off, and the analog switch 54 is turned on, and the voltage 2 is supplied to the power supply line 53a. be done. Therefore, the common signal X1 changes from ■0 voltage to ■2
voltage and remains in that state for a period t2. Furthermore, during the t2 period, the segment drive signal is held at the V2 voltage as described above, so the liquid crystal panel 16 is driven with zero bias.

Then, when entering the next backplate period, the frame signal Jr is inverted to high level and the zero bias timing signal EC returns to high level. Frame signal 7F
When inverted to high level, MOS1-transistor 5La
is turned off, and MOS transistor 51. b is turned on and V4 voltage is selected. Furthermore, when the zero bias timing signal EC returns to high level, the analog switch 5
2 is turned on, the analog switch 54 is turned off, and the 4 voltage is supplied to the power supply line 53a. Furthermore, at this time, the data held in the flip-flop B4a is shifted to the flip-flop 64b by the clock pulse 7;n2, and its output becomes high level, the analog switch 61b is turned on, the analog switch 62b is turned off, and the V4 voltage is output as the common signal X2. Output.

At this time, the output of the flip-flop 64a returns to the low level, so the analog switch 61a is turned off, the analog switch fi2a is turned on, and the common signal X1 is held at the level of 2 voltage (non-selected).

When the above common signal X2 passes the t1 period and enters the t2 period, the common signal
Switch to voltage. Thereafter, in the same way, vertical timing signals - "common signal It is held at the V4 voltage, and held at the V2 voltage for the next <12 periods.

As described above, the segment drive signal Y1 to the liquid crystal panel 16 is outputted n times in one backplate period F, and X times of these are set to the V2 voltage, and at the same time, the common drive signal is set to the V2 voltage for zero bias drive. Therefore, by variably setting the zero bias period, the effective drive voltage changes according to the zero bias period, and brightness is adjusted. Therefore, brightness adjustment can be performed digitally while keeping the liquid crystal driving voltage constant, that is, keeping the optimum bias.

[Second Embodiment of the Invention] Next, a second embodiment of the invention will be described with reference to FIGS. 8 and 9. In the first embodiment, the zero bias period in each hackbray 1 and period F is held constant after the bright adjustment is completed, but in this second embodiment, the zero bias period in each backplay 1 and period F is maintained constant. Brightness adjustment can be made more precisely by varying the bias periods. Some scanning methods for LCD televisions are such that a plurality of common electrodes are simultaneously selected in units of several H (horizontal period) and scanned sequentially.The second embodiment uses such a scanning method. This is realized by the combination of −23=. Well, this second
In the embodiment, the zero bias timing signal generation circuit in the display control circuit 1 is configured as shown in FIG. In this embodiment, a case is shown in which four common electrodes are sequentially scanned while simultaneously selecting each 4H (4 back plates). 21a in Figure 8
is a 5-bit counter, which operates up/down by operating the bright key in the key manual section 10. Then, the output Q1゜Q2 of the lower two bits of the counter 21a is
is input to the decoder 71, and the upper 3 bits output Q3~Q
5 is input to the +1 circuit 72. Further, the count output of a 2-bit counter 73 is applied to the decoder 71. This counter 73 uses a timing signal ¥N8
The count-up operation is performed.

The decoder 71 has a count output Q of the counter 21a.
The operation contents are set by 1 and Q2, for example, the low level signal is +1 until the count value of the counter 73 reaches the count value of the counter 2La, Q2.
Output to circuit 72 and output to counter 73
, Q2, a high level signal is output to the +1 circuit 72. +1 circuit 72 is
When the output signal of the decoder 71 is at low level, the count outputs Q3 to Q5 of the counter 21a are directly converted to DA and DB.
, is output as DC to the PWM circuit 22, and when the output of the decoder 71 is at /\I level, the above values of Q3 to Q5 are +1.
And DA.

It is output to the PWM circuit 22 as DB and DC.

In the above configuration, Ql and Q2 of the counter 21a are set to "1" by the bright key of the key manual unit 10.

If Q3 to Q5 are set to "5", the counter 73 is counted up to "1" by the timing signal Oka Ns in the first backplate period F1, but the values of Ql- and Q2 of the counter 21a are r ], JC, the output of the decoder 71 is held at low level. Therefore, the +1 circuit 72 is connected to the Q3 to Q of the counter 21a.
The output value "5" of 5 is directly output to the PWM circuit 22. Therefore, as shown in FIG. 9, the PWM circuit 22 is at the /S low level during the first 5/8 period (tl) of one backplate period F, and is at the low level during the remaining 378 periods (t2). Outputs zero bias timing signal EC.

Then, in the next second backplate period F2, the counter 73 is counted up to "2" by the timing signal 7;N3, and the outputs of the counters 21a, Ql, and Q2 are "1".
” becomes larger. Therefore, the output of the decoder 71 becomes high level, and the +1 circuit 72 outputs the Q3- of the counter 2La.
The output “5” of Q5 is added to r+IJL, and the addition result “6” is output to the PWM circuit 22.

Therefore, the PWM circuit 22 has 1 back play 1 and period F.
A zero bias timing signal is output, which is at a high level during the first 6/8 period (tl) and at a low level during the remaining 2/8 period (t2).

Thereafter, the counter 73 is sequentially counted up by the timing signal 7;N5, or the output signal of the decoder 71 is held at a high level. Therefore, the third. Fourth
Hack plate period F3. In F4, a zero bias timing signal EC having the same waveform as in the second backplate period F2 is output. The above-mentioned first to fourth backplate periods F1 to F4 constitute one period of timing for brightness adjustment.

The zero bias timing signal EC created as described above is then sent to the segment drive circuit 13 shown in FIG. 4 and the common drive circuit 14 shown in FIG. 7. In the segment drive circuit 13 and the common drive circuit 14, the zero bias timing signal r is applied as in the first embodiment.
Accordingly, segment drive signals and common drive signals are created as shown in FIG. In this case, in the first backplate period F1, the zero bias period X1 is (3/8)F
Therefore, in the second to fourth backplate periods F2 to F4, the zero bias period x2 to X4 becomes (2/8)F.

The zero bias timing signal EC is the Ql of the counter 21a as explained in FIG.

Since the ratio of tl and t2 can be set to different values in the first to fourth backplate periods F1 to F4 depending on the value of Q2, brightness adjustment can be made more finely.

[Third Embodiment of the Invention Next, a third embodiment of the invention will be described with reference to FIG. In the first and second embodiments described above, the display control circuit 11
The zero bias timing signal generation circuit shown in FIGS. 2 and 8 provided in the counter 21 .
Since the count contents of 21a are lost, it is necessary to perform brightness adjustment every time the power is turned on. In order to eliminate the need for such brightness adjustment every time the power is turned on, the third embodiment, as shown in FIG. A non-volatile memory such as E2FROM 81 is provided to always store the set value of counter 2. That is, the count output Q1 of the counter 21~
Q3 is output to the PWM circuit 22 and E2FROM8
], and the data read from the output terminal OUT of this E2PROM 81 is input to the data input terminals D1 to D3 of the counter 21. A controller 82 is connected to the load terminal LOAD of the counter 21 and the read/write control terminal of the E2PROM 8.

In the above configuration, when the contents of the counter 21 are incremented or counted down by the operation of the bright key in the key manual section 10, the controller 82
converts the count value of counter 21 to E2FRO after a certain period of time.
Write to M81. Thereafter, the controller 82 uses the data stored in the E2FROM8L to set the counter 2 at regular intervals.
Refle and Soshu the contents of 1. In this case, the counter 21 is not refreshed when the bright key is operated.
E2 The contents of the counter 21 are refreshed after data writing to the FROM 81 is completed. As a result, the latest setting contents of the counter 21 are stored in the E2PROM 81 by key operations, and the contents of the counter 21 are updated at regular intervals according to the stored contents.

Therefore, even if the power is turned off, the bright setting data will remain on the E2P.
Stored in ROM81, E2FRO is saved when the power is turned on.
The memory data of M81 is written to the counter 2F at regular intervals, and the bright state before the power is turned off is reproduced.

In addition, in FIG. 10 above, the case where the E2PROM 81 is used as the memory for storing the set value of the counter 21 has been explained, but other memory such as RAM with a backup function may also be used. Any memory that can hold data when it is used is sufficient.

In addition, FIG. 10 above shows the case where a memory for data retention is added to the zero-bias timing signal generation circuit shown in FIG. 2, or the same applies to the zero-bias timing signal generation circuit shown in FIG. It can be implemented by

Furthermore, in each of the above embodiments, a plurality of PWM signals are generated during one backplate period, but one PWM signal with different time widths is generated in correspondence with the zero bias timing signal EC.
An M signal may also be generated. Furthermore, it goes without saying that even if multiple gradations are not displayed, brightness adjustment can be performed in the same manner as in the above embodiment.

[Effects of the Invention] As detailed above, according to the present invention, each hack play 1
・A zero bias period is provided during the period, and this zero bias period is digitally variable and set according to the operation of the bright key, so by varying this zero bias period, the effective value of the liquid crystal drive voltage can be varied. I can do it.

That is, the effective drive voltage can be varied without varying the voltage applied to the liquid crystal, and the brightness can be digitally adjusted while maintaining the optimum bias. In addition, since the voltage applied to the liquid crystal can be kept constant, the scale of the power supply circuit can be reduced, and each device no longer needs to consider changes in the power supply voltage, allowing stable operation without being subject to circuit constraints. can.

Also, when the selection time of the common electrode is set to be the M back plate period, the zero bias period during the M hack play 1 period is set to a value that is equal to one step the number of times according to the bright setting data. Therefore, it is possible to more finely variably set the effective drive voltage with one cycle of M backplay 1 period, and finely adjust the brightness.

Furthermore, in the present invention, the contents of the counter where the brightness adjustment data is set are always stored and retained in the non-volatile memory, so that even when the power is turned off, the brightness adjustment data is retained in the memory, and when the power is turned on. It is possible to reproduce the bright state when the power is turned off.

[Brief explanation of the drawing]

1 to 7 show a first embodiment of the present invention, FIG. 1 is a block diagram showing the overall circuit configuration, and FIG. 2 is the configuration of the zero bias timing signal generation circuit in the display control circuit. 3 is a timing chart for explaining the operation, FIG. 4 is a block diagram showing details of the segment drive circuit, and FIG. 5 is a main part of the gradation signal generation circuit in FIG. 4. A circuit configuration diagram, FIG. 6 is a timing chart for explaining the operation of FIG. 5, FIG. 7 is a block diagram showing details of the common drive circuit, and FIG. 8 is a display control circuit in a second embodiment of the present invention. FIG. 9 is a timing chart for explaining the operation of the second embodiment, and FIG. 10 is a block diagram showing the configuration of the zero bias timing signal generation circuit in the third embodiment of the present invention. FIG. 11 is a block diagram showing the configuration of a zero-bias timing signal generation circuit in the prior art, and FIG. 11 is a diagram showing an example of the waveform of a conventional liquid crystal drive voltage. 11...Display control circuit, 12...A/D conversion circuit, 1
3... Segment drive circuit, 14... Common drive circuit, 15... Liquid crystal drive voltage generation circuit, 16... Liquid crystal panel, 21,, 21 a... Counter, 22=-
PWM circuit, 31... Data latch clock generation circuit, 32... Data latch circuit, 33... Gradation signal generation circuit, 34... Level shifter, 35... Analog multiplexer, 36... Vl・V3 control circuit,
53a, 53b...Power line, 52, 54.81
a. 61. b ~, 62a, 62b ~, -...
Analog switch, 55.57.65a, [i5b,
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...Flip-flop, 81...E2 PROM0 Applicant's agent Patent attorney Takehiko Suzue Video signal Fig. 1 Fig. 2 1po 1ζ is δrg

Claims (3)

[Claims] (1) In a liquid crystal panel drive circuit equipped with a liquid crystal panel in which segment electrodes and common electrodes are arranged in a matrix,
a segment signal generating means for generating a segment signal having a gradation according to display data; a common signal generating means for generating a common signal for selectively scanning the common electrode;
means for setting a zero bias period during each back plate period for the segment signal and common signal; a counter whose count contents are set by operating a bright key; 1. A liquid crystal panel drive circuit comprising brightness adjustment means for adjusting brightness by varying the zero bias period of a common signal. (2) Equipped with a liquid crystal panel in which segment electrodes and common electrodes are arranged in a matrix, and the selection time of the common electrodes is M.
In a liquid crystal panel drive circuit set in a backplate period, means for setting a zero bias period in each backplate period for segment signals and common signals, and a counter whose count contents are set by operating a bright key. , means for varying the zero bias period of the segment signal and the common signal according to the set value of the counter, and for setting each zero bias period of the M backplate period according to the set value of the counter. A liquid crystal panel drive circuit characterized by: (3) Equipped with a non-volatile memory that stores the updated data each time the setting contents of the above counter are updated, and when the power is turned on, the stored contents of the memory are loaded into the above counter, and when the power is turned off. The liquid crystal panel drive circuit according to claim 1 or claim 2, wherein the liquid crystal panel drive circuit reproduces a bright state.