JP2001343948A - Driver and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of picture quality at the time of performing the sum average of gradation voltages. SOLUTION: In this display, a first transistor Q11, a second transistor Q12 which is differentially coupled with the first transistor, a third transistor Q13 which is connected in parallel with the second transistor are provided. A switching circuit 41 for changing over a first state in which a first gradation voltage is transferred to the first transistor and a second gradation voltage is transferred to the second transistor and a second state in which the first gradation voltage is transferred to the second transistor and the second gradation voltage is transferred to the first transistor in a prescribed cycle is provided. Offset is cancelled by averaging an error caused by the difference between thresholds of the second transistor and the third transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver and, more particularly, to a driver including an amplifier for obtaining a drive voltage based on a first gray scale voltage and a second gray scale voltage, for example, for driving a TFT type color liquid crystal panel. The technology that is effective when applied to source drivers.

[0002]

2. Description of the Related Art A liquid crystal panel includes a plurality of source lines and gate lines arranged so as to intersect the source lines, and a liquid crystal cell is arranged at an intersection between the source lines and the gate lines. A driving device for driving such a liquid crystal panel includes a source driver for driving a source line and a gate driver for driving a gate line. The source driver outputs drive information in units of one line.
At this time, the gate source driver drives the plurality of source lines in a time-division manner.

[0003] As an example of a document describing a liquid crystal display, there is an "Electronic Communication Handbook (page 472)" issued by Ohm Corporation in 1983.

[0004]

In a source driver, display data is decoded, a gray scale voltage selection corresponding to the decoded result is selected, and the selected gray scale voltage is buffered and then output to a liquid crystal panel. Is done. The gray scale voltage is formed by voltage division by a gray scale voltage generation circuit formed by combining a plurality of resistors. For example, in the case of 64 gradations, a voltage of 64 levels is directly output from the resistance ladder circuit.

[0005] Generally, the image quality is improved at 256 gradations rather than 64 gradations. However, in the case of 256 gradations, a voltage of 256 levels must be output from the resistance ladder circuit, which complicates the configuration of the gradation voltage generation circuit and its surroundings. In order to avoid this, an intermediate level gradation voltage may be formed in the amplifier circuit by averaging the voltages.

That is, according to the output of the decoder,
By selecting two types of voltages from a plurality of gray scale voltages from the gray scale voltage generation circuit and averaging the selected two types of voltages in the amplifier circuit, a voltage at an intermediate level between the two types of voltages is obtained. Is formed on the amplifier circuit side. By doing so, it is not necessary to form a gray scale voltage corresponding to the intermediate level in the gray scale voltage generation circuit, and accordingly, the gray scale voltage generation circuit and its periphery can be simplified. In order to perform such averaging, in the amplifier circuit, a plurality of input terminals corresponding to the number of gradation voltages input to the amplifier circuit, and active elements such as MOS transistors corresponding to the input terminals are provided. Provided. The inventor of the present application has examined the amplifier circuit in that case. When a plurality of input terminals exist for the above-mentioned averaging, a level difference occurs in the source line drive voltage due to variation in the threshold value of the MOS transistor corresponding to the input terminal. Has been found to cause image quality degradation.

An object of the present invention is to provide a technique for preventing the image quality from being deteriorated when performing the averaging of the gradation voltages.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a gray scale voltage generating circuit for generating a plurality of gray scale voltages having different voltage levels from each other, and input data are decoded.
A decoder for selecting a first gray scale voltage and a second gray scale voltage corresponding to the first gray scale voltage from the plurality of gray scale voltages from the gray scale voltage generating circuit; When the liquid crystal driver includes an amplifier for obtaining a drive voltage based on the two gradation voltages, the amplifier includes a first transistor to which an output signal of the amplifier is fed back, A differentially coupled second transistor and a third transistor connected in parallel to the second transistor are provided, the first gray scale voltage is transmitted to the first transistor, and the second gray scale voltage is A first state transmitted to a second transistor;
The first gray scale voltage is transmitted to the second transistor,
A switch circuit is provided for switching at a predetermined cycle between the second state in which the second gradation voltage is transmitted to the first transistor.

According to the above means, the switch circuit switches between the first state and the second state at a predetermined cycle. As a result, in the amplifier, an error caused by a difference in threshold value between the second transistor and the third transistor connected in parallel to the second transistor is averaged, and this averages the grayscale voltages. In this case, the image quality is prevented from deteriorating.

At this time, in order to easily obtain the operation control signal of the switch circuit, the first state and the second state are determined based on an AC signal for AC driving of the liquid crystal and an internal clock signal. It is preferable to provide a circuit for generating a control signal capable of controlling switching between the states.

In the amplifier, a first transistor for forming a differential pair, a second transistor differentially coupled to the first transistor, and a third transistor connected in parallel to the second transistor , The first
A fourth transistor connected in parallel with the transistor, the first grayscale voltage is transmitted to the second transistor, the second grayscale voltage is transmitted to the third transistor, and the output voltage of the amplifier is converted to the first transistor. A first state transmitted to the transistor and the fourth transistor, the first gradation voltage transmitted to the third transistor, the second gradation voltage transmitted to the second transistor, and an output of the amplifier. A second state in which a voltage is transmitted to the first transistor and the fourth transistor, the first gradation voltage is transmitted to the first transistor, and the two gradation voltage is transmitted to the fourth transistor; A third state in which the output voltage of the amplifier is transmitted to the second transistor and the third transistor; and a first state in which the first gray scale voltage is transmitted to the fourth transistor. A switch for switching, at a predetermined cycle, the fourth state in which the second gradation voltage is transmitted to the first transistor and the output voltage of the amplifier is transmitted to the second transistor and the third transistor. Circuit.

According to the above means, the switch circuit switches between the first state, the second state, the third state, and the fourth state at a predetermined cycle. This allows
The difference in threshold value among the first, second, third, and fourth transistors is averaged. This achieves prevention of image quality deterioration when performing averaging of gradation voltages.

At this time, in order to easily obtain an operation control signal of the switch circuit, the first state and the second state are determined based on an AC signal for AC driving of the liquid crystal and an internal clock signal. It is preferable to provide a circuit for generating a control signal capable of controlling switching between a state, the third state, and the fourth state.

Further, the display panel includes a display panel including a plurality of gate lines and a plurality of source lines arranged so as to intersect the plurality of gate lines, and a source line driver for driving the plurality of source lines. When the liquid crystal display device is configured as described above, the driver having the above configuration can be used as the source driver.

[0017]

FIG. 4 shows a configuration example of a liquid crystal display device according to the present invention.

Although not particularly limited, the liquid crystal display device 36 includes a color liquid crystal panel 12, a plurality of gate drivers 10-1 to 10-3 for driving gate lines of the color liquid crystal panel 12, and the color liquid crystal panel. 12
Source drivers 11 for driving data lines
-1 to 11-n, a controller 14 for controlling the operation of the entire liquid crystal display device 36, and a liquid crystal drive power supply circuit 13 for supplying power for driving the color liquid crystal panel 12.

Although not particularly limited, the color liquid crystal panel 12 is of a TFT type and has a size of 1024 × 768.
Dots, a plurality of gate lines, a plurality of data lines arranged to intersect the plurality of gate lines, and an n-channel MOS arranged corresponding to intersections of the gate lines and the data lines
A transistor and a liquid crystal element. For example, FIG.
As shown in FIG. 7, the gate electrodes of the plurality of n-channel MOS transistors 221 are connected to the corresponding gate lines g1 to g1.
g4, the drain electrode of the transistor 221 is connected to the corresponding data lines d1 to d3, and the liquid crystal element 222 is connected between the source electrode of the transistor 221 and the ground GND. To enable color display, three adjacent data lines d1, d2, and d3
It corresponds to GB (red, green, blue), and one pixel is formed by three elements corresponding to RGB. According to the configuration example shown in FIG. 5, the gate lines g1 to g4 are selectively driven to the high level by the gate driver 10-1, and the data lines d1 and d2 are driven by the source driver 11-1 at a voltage level corresponding to the concentration. , D3, the corresponding n-channel MOS transistor 221 is turned on, and the corresponding liquid crystal element 22 is turned on.
2 is charged up. Thereafter, the output signal of the gate driver 10-1 is set to low level, the n-channel MOS transistor 221 is turned off, and the voltage of the liquid crystal element 222 is held.

Next, the source drivers 11-1 to 11-n
Will be described in detail. The plurality of source drivers 1
1-1 to 11-n have the same configuration as each other. Therefore, in the following description, only the source driver 11-1 will be described in detail.

FIG. 6 shows a configuration example of the source driver.

As shown in FIG. 6, the source driver 11
-1 indicates the clock control circuit 80, the latch circuits 92 and 9
3, 94, a decoder 84, an amplifier circuit 85, a data inverting circuit 86, and a gradation voltage generating circuit 87, and are formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The clock control circuit 80 includes a horizontal expansion signal LCHPA1, LCH
PA20-2, a data output horizontal clock signal CL1, a data transfer clock CL2, and a data transfer clock CL4 are input. Enable signals EIO0 to 2R * (* indicates low active or signal inversion), EIO0 to 2L *
Is an enable signal for the source driver, and when this enable signal is asserted to a low level, data is taken into the source driver.
M is an alternating signal. In order to prevent the liquid crystal from being damaged, the AC driving of the liquid crystal is controlled by the AC conversion signal M. The alternating signal M is captured at the timing of the rising edge of the data output horizontal clock signal CL1. Depending on the polarity of the alternating signal M, the alternating signal M has a positive polarity (V0 to V4) and a negative polarity (V5 to V9). Are selectively generated.
Although not particularly limited, when the AC signal M has a logical value “0”, the liquid crystal application voltage of positive polarity is output from the odd output terminals (Y1, Y3,..., Y383), and the even output terminal (Y
2, Y4,..., Y384) output a liquid crystal application voltage of negative polarity. When the AC signal M has the logical value "1", the liquid crystal application voltage of negative polarity is output from the odd output terminals (Y1, Y3,..., Y383), and the even output terminal (Y
2, Y4,..., Y384) output a liquid crystal application voltage of positive polarity. SHL is a signal indicating the shift direction of the display data, and the shift direction of the display data written to the first latch circuit is controlled via the latch address selector 81.

Data D transmitted from controller 14
57-D50, D47-D40, D37-D30, D2
7 to D20, D17 to D10, and D07 to D00 are transmitted to the first latch circuit 92 via the data inverting circuit 86. The inversion circuit 86 inverts the logic of the data according to the data inversion signal POL transmitted from the controller 14.

The first latch circuit 92 includes the data inverting circuit 8
6 is held under the control of the latch address selector 81. Horizontal enlargement and centering display
Under the control of the latch address selector 81, the output is performed by the address control when the output data of the data inversion circuit 86 is written to the first latch circuit 92. At the subsequent stage of the first latch circuit 92, a second latch circuit 93 capable of holding output data of the first latch circuit 92 is provided.
At the subsequent stage of the latch circuit 93, a third latch circuit 94 capable of holding output data of the latch circuit 93 is provided. Each of the first latch circuit 92, the second latch circuit 93, and the third latch circuit 94 includes eight planes of data latches each corresponding to 384 data lines. Eight planes are provided because 8-bit digital data per terminal is required to output, for example, a voltage of 256 gradations from each source line drive terminal.

At the subsequent stage of the latch circuit 94, a decoder 84 for decoding latch circuit output data is provided. The output signal of the decoder 84 is externally output after being buffered by an amplifier circuit 85 at the subsequent stage for driving the source line.

The voltages of various levels required for decoding by the decoder 84 are generated by dividing the input voltages V0 to V9 of various levels by resistance in the gradation voltage generation circuit 87. For example, as shown in FIG. 7, various levels of input voltages V0 to V9 are taken in, and a combination of representatively shown ladder resistors R1 to R8 is used to indicate 256 gradations of positive polarity and 256 gradations of negative polarity. Get multiple levels of voltage. In the amplifier circuit 85, the intermediate level is formed by performing the averaging of the two types of gradation voltages. Therefore, the number of voltage output terminals in the gradation voltage generation circuit 87 is set to 160. Are selected, and the corresponding gray scale voltage is transmitted to the amplifier circuit 85. For example, the output voltage level of 256 gradations is 20 mV in the range of 5 to 10 V.
It is notched.

The amplifier circuit 85 has 384 amplifiers 85-1 to 85-38 corresponding to the number of output terminals of the decoder 84.
4. The amplifiers 85-1 to 85-384 have the same configuration as each other.

FIGS. 8 to 10 show the color liquid crystal panel 12.
Is shown. Note that "+" and "-" indicate that the dot logic is inverted.

FIG. 8 shows a state of the dot inversion driving.

As described above, the source drivers 11-1 to 11-1
In 1-n, AC driving of the liquid crystal is enabled by switching the logic of the AC signal M. For example, by switching the AC signal M for each data output horizontal clock signal CL1, dot inversion driving in which grayscale voltages having different polarities are applied to adjacent dots can be performed.

FIG. 9 shows the state of n-line inversion driving.

When the logic of the AC signal M is switched every n times of the data output horizontal clock signal CL1, n-line inversion driving is performed every one dot in the horizontal direction and every n lines in the vertical direction as shown in FIG. .

FIG. 10 shows a state of the frame inversion driving.

By switching the logic of the AC signal M on a frame-by-frame basis, as shown in FIG.
Frame inversion driving can be performed for each dot and for each frame in the vertical direction.

FIG. 11 shows the relationship between the data input at the time of frame inversion and the AC signal M and the output level.

By selecting the positive and negative gradation voltages according to the logic level of the AC signal M at the time of the rising edge of the data output horizontal clock signal CL1, the next data output horizontal clock signal CL1 is selected. Are output. HV indicates a voltage of 256 gray levels on the positive side, and LV indicates a voltage of 256 gray levels on the negative side. When the AC signal M has the logical value “0”, the liquid crystal application voltage HV of the positive polarity is output from the odd output terminal, and the liquid crystal application voltage LV of the negative polarity is output from the even output terminal. When the AC signal M has a logical value of “1”, a negative liquid crystal application voltage is output from the odd output terminal, and a positive liquid crystal application voltage is output from the even output terminal.

Next, the amplifier circuit 85 will be described in detail.
384 amplifiers 85-1 to 85-1 included in the amplifier circuit 85
85-384 have the same configuration, and one of them will be described in detail.

FIG. 1 representatively shows a configuration example of an amplifier 85-1 which is one of a plurality of amplifiers in the amplifier circuit 85.

A p-channel type MOS transistor Q11
And a p-channel MOS transistor Q12 are differentially coupled, and the p-channel MOS transistor Q1
2, a p-channel type MOS transistor Q13 is differentially coupled. p-channel type MOS transistors Q11 to Q11
The source electrode of Q13 is coupled to high potential side power supply Vdd via p-channel MOS transistor Q1. p
The gate terminals of the channel type MOS transistors Q12 and Q13 are connected to the input terminal IN1 via the switch circuit 41.
Alternatively, an input signal from IN2 is provided. The switch circuit 41 includes an offset cancel signal LCHPA1, LC
Based on HPA2, the grayscale voltage input from input terminal IN1 is transmitted to the gate electrode of p-channel MOS transistor Q12, and the grayscale voltage input from input terminal IN2 is transmitted to the gate electrode of p-channel MOS transistor Q13. The first state to be transmitted and the grayscale voltage input from the input terminal IN1 are transmitted to the gate electrode of the p-channel MOS transistor Q13, and the grayscale voltage input from the input terminal IN2 is transferred to the p-channel MOS transistor Q13.
The second state transmitted to the twelve gate electrodes is switched at a predetermined cycle. As a result, the two gray scale voltages input from the decoder 84 via the input terminals IN1 and IN2 are alternately transmitted to the p-channel MOS transistors Q12 and Q13.

The p-channel type MOS transistor Q
The gate electrodes of 11 to Q13 are n-channel MOS transistors Q3 and Q4 forming a current mirror type load.
To the ground GND. A series connection node of the p-channel MOS transistors Q12 and Q13 and the p-channel MOS transistor Q4 is coupled to the gate electrode of the subsequent n-channel MOS transistor Q5. This p-channel type MOS transistor Q
5 is connected to the p-channel MOS transistor Q2 in series, and the amplifier 85-1
Output terminal OUT is drawn out. A capacitor C1 for phase compensation is provided between the drain electrode and the gate electrode of the p-channel MOS transistor Q5.

A predetermined bias voltage V is applied to the gate electrodes of the p-channel MOS transistors Q1 and Q2.
B, whereby the p-channel MO
S transistors Q1 and Q2 function as constant current sources.

FIG. 2 shows a configuration example of the switch circuit 41.

As shown in FIG.
Are p-channel MOS transistors Q21, Q2
2, Q23 and Q24. p-channel type MO
S-transistor Q21 is arranged so that the signal path between input terminal IN2 and p-channel MOS transistor Q13 can be intermittently connected, and offset cancel signal LCHPA
1 is operation-controlled. The p-channel type MOS transistor Q22 is connected to the input terminal IN1 and the p-channel type M
The signal path between the OS transistor Q13 and the OS transistor Q13 is intermittently arranged, and its operation is controlled by an offset cancel signal LCHPA2. Offset cancel signal LCH
PA1 and LCHPA2 are signals of complementary levels, and therefore, the p-channel MOS transistor Q2
Either 1 or Q22 is selectively conducted. The p-channel MOS transistor Q23 is connected to the input terminal IN2
The signal path between the transistor and the p-channel MOS transistor Q12 is intermittently arranged, and the operation is controlled by an offset cancel signal LCHPA2. The p-channel MOS transistor Q24 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q12 can be intermittently connected, and the offset cancel signal LC
The operation is controlled by the HPA1. The offset cancel signals LCHPA1 and LCHPA2 are signals of complementary levels, so that one of the p-channel MOS transistors Q23 and Q24 is selectively turned on.

FIG. 12 shows an offset cancel signal LCHPA1 for controlling the operation of the switch circuit 41.
An offset cancel signal generation circuit for generating LCHPA2 is shown.

The offset cancel signal generation circuit 121 shown in FIG. 12 is, although not particularly limited, a flip-flop circuit FF1 for synchronizing the AC signal M with the data output horizontal clock signal CL1, and a flip-flop circuit FF1 of the flip-flop circuit FF1. And a flip-flop circuit FF2 for dividing the output signal by １ ／, which is arranged in the clock control circuit 80 shown in FIG. Each of the flip-flop circuits FF1 and FF2 includes a data terminal D, a clock pulse terminal CP, a non-inverted output terminal Q, and an inverted output terminal QN. The output signal from the non-inverting output terminal D of the flip-flop circuit FF1 is
The signal is transmitted to the clock pulse terminal CP of F2. In the flip-flop circuit FF2, the data is fed back from the inverted output terminal QN to the data terminal D. From the non-inverting output terminal Q of the flip-flop circuit FF2, the offset cancel signal LCHP
A1 and LCHPA2 are obtained and transmitted to the switch circuit 41.

FIG. 13 shows the operation timing of the main part of the offset cancel signal generation circuit 121. As shown in FIG. 13, the offset cancel signals LCHPA1 and LCHPA2 are at complementary levels. Since the AC signal M is inverted at a fixed period such as a frame unit in order to prevent burn-in of the liquid crystal panel, the offset signal M is used to perform the offset cancellation for performing the offset operation every four frames, for example. Signals LCHPA1 and LCHPA2 can be easily generated.

FIG. 3 shows an example of an offset canceling operation by the switch circuit 41.

In the first frame, the input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q12, and the input terminal IN2 is connected to the p-channel MOS transistor Q12.
The gate electrode of transistor Q13 is coupled.

In the second frame, the dot inversion of the first frame is performed based on the AC signal M. At this time, the offset cancel control signal LC
Since there is no logical change in HPA1 and LCHPA2, the connection state by the switch circuit 41 is the same as that in the first frame.

In the third frame, the logic of the AC signal M has already been inverted, and the logical changes of the offset cancel control signals LCHPA1 and LCHPA2 are changed.
Input terminal IN1 and p-channel MOS transistor Q
13 are coupled to each other, and the input terminal IN2 is coupled to the gate electrode of the p-channel MOS transistor Q12.

In the fourth frame, dot inversion in the third frame is performed based on the AC signal M. At this time, the offset cancel control signal LC
Since there is no logical change in HPA1 and LCHPA2, the connection state by the switch circuit 41 is the same as that in the third frame.

One cycle is completed in the first to fourth frames. In this one cycle, the switching of the connection state by the switch circuit 41 is performed only once. The connection state is switched by the switch circuit 41 in this manner, whereby the input terminal IN is switched.
The two types of gradation voltages taken in via IN1 and IN2 are:
Since the p-channel MOS transistors Q12 and Q13 are alternately taken in, the switching circuit 4
1 each time the connection state is switched by the input terminal IN
The relationship between the threshold values of the MOS transistors as viewed from 1 and IN2 is reversed, and the offset due to the variation in the threshold value is canceled.

FIG. 14 shows a computer system to which the liquid crystal display device according to the present invention is applied.

This computer system includes a microcomputer 31 and a DRA via a system bus BUS.
M (dynamic random access memory) 3
2. SRAM 33 (static random access memory), ROM (read only memory) 34,
The peripheral device control unit 35, the liquid crystal display device, and the like are connected to each other so as to be able to exchange signals, and perform predetermined data processing according to a predetermined program. The microcomputer 31 is a logical core of the present system, and is mainly used for addressing, reading and writing of information, data operation, instruction sequence, acceptance of interrupts, and information exchange between a storage device and an input / output device. It has a function such as activation, and is composed of an arithmetic control unit, a bus control unit, a memory access control unit, and the like. The DRAM 32, SRAM 33, and ROM 34 are positioned as internal storage devices.
The DRAM 32 is a main memory, and is used as a work area for calculation and control in the microcomputer 31. The SRAM 33 is a secondary cache memory, and stores a part of the storage content of the DRAM 32 as a main memory, so that the information required by the microcomputer 31 can be quickly taken in. . The ROM 34 stores a read-only program. The peripheral device control unit 35 controls the operation of the external storage device 38 such as a hard disk, and controls the information input from the keyboard 39 and the like. Further, an image is displayed by the liquid crystal display device 36.

According to the above-described example, the following effects can be obtained.

(1) One cycle is completed in the first to fourth frames of the liquid crystal panel, and the connection state is switched only once by the switch circuit 41 in this one cycle. By switching the connection state by the switch circuit 41 in this manner,
The two types of gradation voltages taken in through the input terminals IN1 and IN2 are p-channel MOS transistors Q
12 and Q13 alternately, the level relationship of the threshold value of the MOS transistor viewed from the input terminals IN1 and IN2 is reversed every time the connection state is switched by the switch circuit 41, and the variation in the threshold value Is canceled.

(2) In the color liquid crystal panel 12 and the liquid crystal display device 36 including the source driver having the operation and effect (1), the offset caused by the variation in the threshold value of the MOS transistor in the amplifier is cancelled. Is improved.

FIG. 15 shows another configuration example of the amplifier 85-1.

The amplifier 85-1 shown in FIG.
The major difference from that shown in FIG.
The difference is that a p-channel MOS transistor Q14 connected in parallel to the OS transistor Q11 is provided, and a switch circuit 42 is provided instead of the switch circuit 41. The switch circuit 42 transmits the first gradation voltage to the p-channel MOS transistor Q12,
The second gradation voltage is transmitted to the p-channel MOS transistor Q13, and the output voltage of the amplifier 85-1 is applied to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q11.
The first state transmitted to the channel type MOS transistor Q14 and the first gradation voltage are applied to the p-channel type MOS transistor Q14.
The second gradation voltage is transmitted to the p-channel MOS transistor Q12, and the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q13.
The second state transmitted to the S transistor Q14, the first gradation voltage is transmitted to the p-channel MOS transistor Q11, and the two gradation voltage is transmitted to the p-channel MOS transistor Q14. 8
The third state in which the output voltage of 5-1 is transmitted to the p-channel MOS transistors Q12 and Q13, and the first gradation voltage is transmitted to the p-channel MOS transistor Q14, and the second gradation voltage is transmitted to the p-channel MOS transistor Q14. Is transmitted to the p-channel MOS transistor Q11, and the output voltage of the amplifier is changed to the p-channel MOS transistor Q11.
12 and the p-channel type MOS transistor Q13
Is provided for switching at a predetermined cycle between the first state and the fourth state transmitted to the second state.

FIG. 16 shows a configuration example of the switch circuit 42.

As shown in FIG. 16, the switch circuit 42 includes p-channel MOS transistors Q31 to Q31.
Q42.

P-channel MOS transistor Q31
Are arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q11 can be intermittently connected, and the operation thereof is controlled by the offset cancel signal LCHPB1. The p-channel MOS transistor Q32 has an input terminal IN2 and a p-channel MOS transistor Q1.
1 is intermittently arranged, and its operation is controlled by an offset cancel signal LCHPB2.
The p-channel MOS transistor Q33 is connected to the amplifier 8
A signal path between the output terminal OUT of 5-1 and the p-channel type MOS transistor Q11 is intermittently arranged,
The operation is controlled by the offset cancel signal CHOPA. The p-channel MOS transistor Q34 is
Input terminal IN1 and p-channel MOS transistor Q
14 is intermittently arranged, and its operation is controlled by an offset cancel signal LCHPB2. The p-channel MOS transistor Q35 is connected to the input terminal IN2 and the p-channel MOS transistor Q14.
Are intermittently arranged, and the operation is controlled by an offset cancel signal LCHPB1. p
The channel type MOS transistor Q36 is connected to the amplifier 85
The signal path between the -1 output terminal OUT and the p-channel MOS transistor Q14 is intermittently arranged, and the operation is controlled by the offset cancel signal CHOPA. The p-channel MOS transistor Q42 has an input terminal IN1 and a p-channel MOS transistor Q1.
2 are intermittently arranged, and the operation is controlled by an offset cancel signal LCHPA1.
The p-channel MOS transistor Q41 is arranged so that the signal path between the input terminal IN2 and the p-channel MOS transistor Q12 can be intermittently connected, and is controlled in operation by an offset cancel signal LCHPA2.

P-channel type MOS transistor Q40
Are arranged so that the signal path between the output terminal OUT of the amplifier 85-1 and the p-channel MOS transistor Q12 can be intermittently connected, and the operation thereof is controlled by the offset cancel signal CHOPB. The p-channel MOS transistor Q39 is arranged so that the signal path between the input terminal IN1 and the p-channel MOS transistor Q13 can be intermittently connected, and its operation is controlled by an offset cancel signal LCHPA2. p-channel type MOS transistor Q3
Numeral 8 is arranged so that the signal path between the input terminal IN2 and the p-channel type MOS transistor Q13 can be intermittently connected, and its operation is controlled by an offset cancel signal LCHPA1. The p-channel type MOS transistor Q37 is
Output terminal OUT of amplifier 85-1 and p-channel type MO
A signal path between the S transistor Q13 and the S transistor Q13 is intermittently arranged, and the operation is controlled by an offset cancel signal CHOPB.

FIG. 17 shows an offset cancel signal LCHPA1 for controlling the operation of the switch circuit 42.
LCHPA2, CHOPB, LCHPB1, LCHPB
2, an offset cancel signal generation circuit 122 for generating CHOPA is shown.

The offset cancel signal generation circuit 122 shown in FIG. 17 is, although not particularly limited, a flip-flop circuit FF3 for synchronizing the AC signal M with the data output horizontal clock signal CL1, and a flip-flop circuit FF3 of the flip-flop circuit FF3. A flip-flop circuit FF4 for dividing the output signal by と, and a flip-flop circuit F
In order to further divide the output signal of F5 by １ ／, a flip-flop circuit FF5 and inverters G1 to G5, G10
G14, and NAND gates G6 to G9. The output signal from the non-inverting output terminal Q of the flip-flop circuit FF4 is inverted by the inverter G1 to obtain the offset cancel signal CHOPB. Then, this signal is further inverted by the inverter G10 to obtain the offset cancel signal CHOPA. The output signal from the non-inverting output terminal Q of the flip-flop circuit FF4 is inverted by the inverter G2, and the output signal from the inverted output terminal QN of the flip-flop circuit FF4 is inverted by the inverter G3. The output signal from the non-inverted output terminal Q of the flip-flop circuit FF5 is inverted by the inverter G4, and the output signal from the inverted output terminal QN of the flip-flop circuit FF5 is inverted by the inverter G5. The NAND logic of the output signals of the inverters G2 and G4 is obtained by a NAND gate G6, and the output signal is output to the inverter G1 in the subsequent stage.
By being inverted by 1, an offset cancel signal LCHPB1 is obtained. The NAND logic of the output signals of the inverters G3 and G5 is obtained by the NAND gate G7, and the output signal is inverted by the inverter G12 at the subsequent stage to obtain the offset cancel signal LCHPA1. The NAND logic of the output signals of the inverters G3 and G4 is obtained by the NAND gate G8, and the output signal is inverted by the inverter G13 at the subsequent stage to obtain the offset cancel signal LCHPA2. The NAND logic of the output signals of the inverters G2 and G5 is the NAND gate G.
9 and its output signal is inverted by the inverter G14 at the subsequent stage, so that the offset cancel signal LC
HPB2 is obtained.

FIG. 18 shows operation waveforms of main parts in the offset cancel signal generation circuit 122.
As shown in FIG. 18, based on the AC signal M and the data output horizontal clock signal CL1, the offset cancel signals LCHPA1, LCHPA2, CHOP
B, LCHPB1, LCHPB2, and CHOPA are easily generated. Since the alternating signal M is inverted at a fixed period such as a frame unit as described above, by using the inverted signal M, the offset cancel signal can be easily generated at a timing such that an offset cancel operation is performed every eight frames, for example. can do.

FIG. 19 shows an example of an offset cancel operation by the switch circuit 41.

In the first frame, the input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q12, and the input terminal IN2 is connected to the p-channel MOS transistor Q12.
The gate electrode of transistor Q13 is coupled to the output terminal of amplifier 85-1, and the gate electrodes of p-channel MOS transistors Q11 and Q14 are coupled.

In the second frame, dot inversion of the first frame is performed based on the AC signal M. At this time, the offset cancel signal LCHP
A1, LCHPA2, CHOPB, LCHPB1, LC
Since there is no logical change between HPB2 and CHOPA, the connection state by the switch circuit 42 is the same as that in the first frame.

In the third frame, the logic of the AC signal M has already been inverted, and the input terminal IN1 is connected to the gate electrode of the p-channel MOS transistor Q13 by setting the offset cancel signal LCHPA2 to low level. The input terminal IN2 is connected to the gate electrode of the p-channel MOS transistor Q12.

In the fourth frame, dot inversion in the third frame is performed based on the AC signal M. At this time, the offset cancel signal LCHP
A1, LCHPA2, CHOPB, LCHPB1, LC
Since there is no logical change between HPB2 and CHOPA, the connection state by the switch circuit 42 is the same as that in the third frame.

In the fifth frame, when the offset cancel signal LCHPB1 is changed to the low level, the signal input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q11, and the input terminal IN2
Is coupled to the gate electrode of p-channel type MOS transistor Q14. At this time, the output terminal OUT of the amplifier 85-1 is coupled to the gate electrodes of the p-channel MOS transistors Q12 and Q13 by setting the offset cancel signal CHOPB to low level.

In the sixth frame, the AC signal M
, The dot inversion of the fifth frame is performed.
At this time, the offset cancel signal LCHPA
1, LCHPA2, CHOPB, LCHPB1, LCH
Since there is no logical change in PB2 and CHOPA, the connection state by the switch circuit 42 is the same as that in the fifth frame.

In the seventh frame, when the offset cancel signal LCHPB2 is changed to the low level, the input terminal IN1 is coupled to the gate electrode of the p-channel MOS transistor Q14, and the input signal IN2 is changed to p.
Coupled to the gate electrode of channel type MOS transistor Q12.

In the eighth frame, the dot inversion in the seventh frame is performed based on the AC signal M. At this time, the offset cancel signal LCHP
A1, LCHPA2, CHOPB, LCHPB1, LC
Since there is no logical change in HPB2 and CHOPA, the connection state by the switch circuit 42 is the same as that in the seventh frame.

In the structure shown in FIG. 16, the first gradation voltage is transmitted to p-channel MOS transistor Q12, and the second gradation voltage is transmitted to p-channel MOS transistor Q13. The first state in which the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14, and the first gradation voltage is transmitted to the p-channel MOS transistor Q13. A second state in which the second gradation voltage is transmitted to the p-channel MOS transistor Q12, and the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistor Q11 and the p-channel MOS transistor Q14. And the first gradation voltage is applied to the p-channel MOS transistor. A third state in which the two gradation voltages are transmitted to the p-channel MOS transistor Q14, and the output voltage of the amplifier 85-1 is transmitted to the p-channel MOS transistors Q12 and Q13. , The first gradation voltage is transmitted to the p-channel MOS transistor Q14, and the second gradation voltage is transmitted to the p-channel MOS transistor Q11.
The output voltage of the amplifier is transmitted to the p-channel type MOS transistor Q12 and the p-channel type
Since the fourth state transmitted to the OS transistor Q13 is switched at a predetermined cycle, the p-channel MOS
Offset cancellation caused by variations in the threshold values of the transistors Q11 to Q14 can be performed.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the invention which was mainly made by the present inventor has been applied to
Although the description has been given of the case where the present invention is applied to a type color liquid crystal panel, the present invention is not limited thereto, and can be widely applied to various display panels.

The present invention can be applied on condition that an amplifier circuit for outputting a liquid crystal application voltage based on at least the first gradation voltage and the corresponding second gradation voltage is provided.

[0081]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first state and the second state are switched at a predetermined cycle by the switch circuit, whereby the second transistor and the third transistor connected in parallel to the second transistor are switched.
It is possible to cancel an offset due to a difference in threshold voltage between the transistor and the transistor, thereby preventing deterioration in image quality when performing averaging of gradation voltages.

Further, the first state,
By switching between the second state, the third state, and the fourth state at a predetermined cycle, the first transistor, the second
The difference between the threshold values of the transistor, the third transistor, and the fourth transistor is averaged, so that it is possible to prevent the image quality from deteriorating when performing the averaging of the gradation voltages.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of an amplifier in a liquid crystal driver according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a switch circuit included in the amplifier.

FIG. 3 is an explanatory diagram of an example of an offset cancel operation by the switch circuit.

FIG. 4 is a block diagram illustrating a configuration example of a liquid crystal display device including the liquid crystal driver.

FIG. 5 is a circuit diagram illustrating a configuration example of a color liquid crystal panel included in the liquid crystal display device.

FIG. 6 is a block diagram illustrating a configuration example of a source driver that is the liquid crystal driver.

FIG. 7 is an explanatory diagram of an output voltage of a gradation voltage generation circuit included in the source driver.

FIG. 8 is a diagram illustrating a driving example of the color liquid crystal panel.

FIG. 9 is a diagram illustrating a driving example of the color liquid crystal panel.

FIG. 10 is an explanatory diagram of a driving example of the color liquid crystal panel.

FIG. 11 is an explanatory diagram showing a relationship between a data input, an alternating signal, and an output level at the time of frame inversion of the color liquid crystal panel.

FIG. 12 is a block diagram illustrating a configuration example of an offset cancel signal generation circuit included in the source driver.

FIG. 13 is an operation timing chart of a main part in the offset cancel signal generation circuit.

FIG. 14 is a block diagram illustrating a configuration example of a computer system to which the liquid crystal display device is applied.

FIG. 15 is a circuit diagram illustrating another configuration example of the amplifier.

FIG. 16 is a circuit diagram illustrating another configuration example of the switch circuit.

FIG. 17 is a circuit diagram of another configuration example of the offset cancel signal generation circuit.

18 is an operation timing chart of a main part in the offset cancel signal generation circuit shown in FIG.

FIG. 19 is an explanatory diagram of an example of an offset cancel operation by the switch circuit.

[Explanation of symbols]

12 Liquid Crystal Panel 11-1 to 11-n Source Driver 10-1 to 10-3 Gate Driver 36 Liquid Crystal Display Device 41, 42 Switch Circuit 80 Clock Control Circuit 81 Latch Address Selector 84 Decoder 85 Amplifier Circuit 85-1 to 85-384 Amplifier 86 Data inversion circuit 87 Gradation voltage generation circuit 92 First latch circuit 93 Second latch circuit 94 Third latch circuit 121, 122 Offset cancel signal generation circuit Q11, Q12, Q13, Q14 p-channel type MO
S transistor

Continuing on the front page (72) Inventor Kazuhiro Okamura 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Koichi Kodera 5--22, Josuihoncho, Kodaira-shi, Tokyo No. 1 In Hitachi, Ltd. LSI Systems Co., Ltd. (72) Inventor Satoshi Yamaguchi 3681 Hayano, Mobara-shi, Chiba Prefecture Inside Hitachi Device Engineering Co., Ltd. (72) Kenji Kawada 3681 Hayano, Mobara-shi, Chiba Prefecture Hitachi Device Engineering Co., Ltd. (72) Inventor Shinya Suzuki 3681 Hayano, Mobara-shi, Chiba F-term (reference) 2H093 NA16 NA31 NA53 NC34 ND06 5C006 AA14 AA16 AA17 AA22 AC26 BB16 BC12 BF24 BF25 BF26 BF43 FA22 FA38 5C080 AA10 BB05 CC03 DD05 EE29 EE30 JJ01 JJ02 JJ03 JJ04 JJ05

Claims (5)

[Claims] 1. A gray-scale voltage generating circuit for generating a plurality of gray-scale voltages having different voltage levels from each other; a plurality of gray-scale voltage generating circuits for decoding input data; A decoder for selecting a first gradation voltage and a corresponding second gradation voltage from the gradation voltages; and a driving voltage based on the first gradation voltage and the corresponding second gradation voltage. A driver for forming a differential pair; a second transistor differentially coupled to the first transistor; and a second transistor. A third transistor connected in parallel to the first transistor, and the first gradation voltage is transmitted to the first transistor.
A first state in which the second gradation voltage is transmitted to the second transistor, a first state in which the first gradation voltage is transmitted to the second transistor, and a second state in which the second gradation voltage is transmitted to the first transistor; A switch circuit for switching between the second state and the second state at a predetermined cycle. 2. An AC signal for AC driving of a liquid crystal,
2. The driver according to claim 1, further comprising a circuit that generates a control signal capable of controlling switching between the first state and the second state based on an internal clock signal. 3. A grayscale voltage generating circuit for generating a plurality of grayscale voltages having different voltage levels from each other, decoding input data, and generating a plurality of grayscale voltages from the grayscale voltage generating circuit based on the decoding result. A decoder for selecting a first gradation voltage and a corresponding second gradation voltage from the gradation voltages; and a driving voltage based on the first gradation voltage and the corresponding second gradation voltage. A driver for forming a differential pair; a second transistor differentially coupled to the first transistor; and a second transistor. A third transistor connected in parallel to the first transistor, a fourth transistor connected in parallel to the first transistor, and the first grayscale voltage is transmitted to the second transistor;
The second gray scale voltage is transmitted to the third transistor,
A first state in which the output voltage of the amplifier is transmitted to the first transistor and the fourth transistor;
The gray scale voltage is transmitted to the third transistor, and the second transistor
A second state in which a gray scale voltage is transmitted to the second transistor and an output voltage of the amplifier is transmitted to the first transistor and the fourth transistor; and a first state in which the first gray scale voltage is transmitted to the first transistor. A third state in which the two gradation voltages are transmitted to the fourth transistor, and an output voltage of the amplifier is transmitted to the second transistor and the third transistor, and the first gradation voltage is transmitted to the third transistor. 4
The second gradation voltage is transmitted to the transistor and the first gradation voltage is transmitted to the first
A switch circuit for switching, at a predetermined cycle, a fourth state transmitted to a transistor and the output voltage of the amplifier being transmitted to the second transistor and the third transistor. driver. 4. An alternating signal for alternating current driving of a liquid crystal,
4. A circuit for generating a control signal capable of controlling switching between the first state, the second state, the third state, and the fourth state based on an internal clock signal.
The driver described. 5. A liquid crystal including a display panel including a plurality of gate lines and a plurality of source lines disposed to intersect the plurality of gate lines, and a source driver for driving the plurality of source lines. The display device according to any one of claims 1 to 4, wherein the source driver is used as the source driver.
A liquid crystal display device characterized by using the driver described in the paragraph.