JP2005316188A - Driving circuit of flat display device, and flat display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely assure desired characteristics by simple adjustment work by applying a driving circuit of a flat display device and a flat display device to a display device by, for example, an organic EL element to correct light emission characteristics in various manners. <P>SOLUTION: Amplifier circuits 56A to 56N and 76A to 76H relating to the driving systems of signal lines are constituted in operational amplifier circuits by a chopper circuit system and the influence due to offset voltages is eliminated by spatial and time integral effects by changing over lines and frames as a unit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a drive circuit for a flat display device and a flat display device, and can be applied to, for example, a display device using an organic EL (Electro Luminescence) element. In the present invention, an amplifier circuit related to a signal line drive system is configured as an operational amplifier circuit using a chopper circuit system, and the setting is switched in units of lines and frames, and the influence of the offset voltage due to the spatial and temporal integration effects. By removing the light, it is possible to cope with various light emission characteristics, and to ensure the desired characteristics by simple adjustment work.

  Conventionally, in a liquid crystal display device which is one of flat display devices, as disclosed in, for example, Japanese Patent Laid-Open No. 10-333648, gamma characteristics are switched by setting a reference voltage used for digital-analog conversion processing. Has been made.

  That is, as shown in FIG. 14, in the liquid crystal display device 1, each pixel (P) 3R, 3G, and 3B is formed by a liquid crystal cell, a switching element of the liquid crystal cell, and a storage capacitor, and the pixels 3R, 3G, and 3B are arranged in a matrix. The display part 2 is formed in a shape. In the liquid crystal display device 1, each pixel 3R, 3G, 3B of the display unit 2 is connected to a horizontal drive circuit 4 and a vertical drive circuit 5 via a signal line (column line) SIG and a gate line (row line) G, respectively. The pixels 3R, 3G, and 3B are sequentially selected by the vertical drive circuit 5, and the gradation of each pixel 3R, 3G, and 3B is set by the drive signal from the horizontal drive circuit 4, thereby displaying a desired image. Has been made. A color image can be displayed by sequentially and sequentially arranging pixels 3R, 3G, and 3B provided with red, green, and blue color filters, respectively.

  For this reason, the liquid crystal display device 1 inputs red, green, and blue image data DR, DG, and DB to be displayed from the device main body 6 to the controller 7 in parallel and synchronizes with the image data DR, DG, and DB. The gate line G of the display unit 2 is driven by the vertical drive circuit 5 according to the timing signal. The image data DR, DG, and DB are time-division multiplexed so as to correspond to driving of the signal line SIG in the horizontal drive circuit 4 to generate one system of image data D1, and the horizontal drive circuit 4 is generated from the image data D1. To drive the signal line SIG.

  FIG. 15 is a block diagram showing the horizontal drive circuit 4 and the controller 7 in detail together with related structures. The controller 7 supports the driving of the signal line SIG by the horizontal drive circuit 4 by sequentially storing and outputting the image data DR, DG, DB output from the apparatus main body 6 to the memory 10 under the control of the memory control circuit 9. As described above, the image data DR, DG, and DB are time-division multiplexed and output by one system so that the image data relating to the same color is continuous in line units in units of horizontal scanning periods. Specifically, in this example, for the red, green, and blue pixels 3R, 3G, and 3B, the horizontal drive circuit 4 sequentially drives the red pixel 3R, the green pixel 3G, and the blue pixel 3B in line units. As a result, the controller 7 cyclically repeats the red image data DR, the green image data DG, and the blue image data DB in units of lines, as shown in FIG. 16B. This image data D1 is output.

  Further, the controller 7 generates various timing signals synchronized with the image data D1 by the timing generator (TG) 11 and outputs them to the horizontal drive circuit 4 and the vertical drive circuit 5. Here, in this timing signal, for example, the clock CK of the image data D1 (FIG. 16A), the start pulse indicating the start and end timing of the image data DR, DG, DB of each color in the image data D1. ST (FIG. 16C), strobe pulse SP (FIG. 16D), and the like.

  In addition, the controller 7 generates the original reference voltages VRT, VB to VG, VRB, which are the generation references of the reference voltage used for the digital / analog conversion processing, by the original reference voltage generation circuit 12 and outputs the generated voltage to the horizontal drive circuit 4.

  The horizontal driving circuit 4 inputs the image data D1 output from the controller 7 to the shift register 13, and sequentially distributes and outputs the image data D1 to the signal line system of the display unit 2. The reference voltage generation circuit 14 generates reference voltages V1 to V64 corresponding to the gradations of the image data D1 from the original reference voltages VRT, VB to VG, and VRB input from the controller 7, and outputs them.

  Each of the digital / analog conversion circuits (D / A) 15A to 15N performs digital / analog conversion processing on the output data of the shift register 13, and in this example, in this example, the drive signals of the adjacent three signal lines SIG are time-division multiplexed. A drive signal is output. The digital / analog conversion circuits 15A to 15N select and output the reference voltages V1 to V64 generated by the reference voltage generation circuit 14 according to the output data of the shift register 13, thereby outputting the image data output from the shift register 13. Is converted from digital to analog.

  The amplifier circuits 16A to 16N amplify the output signals of the digital-analog converter circuits 15A to 15N, respectively, and output the amplified signals to the display unit 2. In the display unit 2, the selectors 17A to 17N output the outputs of the amplifier circuits 16A to 16N. The signals are sequentially and cyclically output to the signal lines SIG related to the red, green, and blue pixels 3R, 3G, and 3B, respectively.

  In this way, the reference voltages V1 to V64 generated from the original reference voltages VRT, VB to VG, and VRB are selected to generate the drive signals for the signal lines SIG, and FIG. It is a block diagram which shows the structure of the reference | standard voltage generation circuit 12 used for the production | generation of VB-VG, VRB, and the reference voltage generation circuit 14 used for the production | generation of reference voltage V1-V64.

  The original reference voltage generating circuit 12 is provided with a voltage dividing circuit 21 in which a predetermined number of resistors are connected in series, and the voltage dividing circuit 21 divides the reference voltage generating voltage VCOM to provide original reference voltages VRT, VB to VG, VRB. Is generated. As a result, the original reference voltage generation circuit 12 generates the original reference voltages VRT, VB to VG, and VRB by resistance voltage division and outputs them through the amplifier circuits 24A to 24H, respectively. Note that the original reference voltage generation circuit 12 is configured so that the voltage applied to the voltage dividing circuit 21 can be switched by the selection circuit 22 and the inverting amplifier circuit 23, and thereby can cope with line inversion or frame inversion. ing. Accordingly, FIG. 16F shows the potential of the signal line SIG in the case of line inversion.

  On the other hand, the reference voltage generation circuit 14 forms a resistor series circuit 26 by further connecting in series the voltage dividing circuits R1 to R7 in which a predetermined number of resistors having the same resistance value are connected in series. One end of a circuit 26, connection points of voltage dividing circuits R1 to R7 constituting the resistor series circuit 26, and the other end of the resistor series circuit 26 are respectively supplied to original reference voltages VRT, VB to VG through amplifier circuits 27A to 27H. VRB is input. Thereby, the reference voltage generation circuit 14 further divides each potential difference by the original reference voltages VRT, VB to VG, VRB generated by the original reference voltage generation circuit 12 by these voltage dividing circuits R1 to R7, respectively. Reference voltages V1 to V64 are generated in the range of VRT and VRB.

  In this way, the reference voltages V1 to V64 are generated from the original reference voltages VRT, VB to VG, and VRB, so that the reference voltage generation circuit 14 has a predetermined number of resistors constituting the voltage dividing circuits R1 to R7. As a result, the original reference voltages VRT, VB to VG and VRB are divided to output a plurality of reference voltages V1 to V64 corresponding to the gradation of the image data D1.

  In the original reference voltage generation circuit 12, the resistors constituting the voltage dividing circuit 21 are displayed so that an image having a desired gamma characteristic is displayed by the reference voltages V1 to V64 corresponding to the gradation of the image data D1. Value is set. As a result, an example in which the voltage VCOM is set to 5 [V] can secure a desired gamma characteristic by polygonal line approximation by setting the original reference voltages VRT, VB to VG, and VRB, as indicated by reference numeral L1 in FIG. ing. In the original reference voltage generation circuit 12, the original reference voltages VRT, VB to VG, VRB output from the voltage dividing circuit 21 can be switched by changing the wiring pattern, whereby the characteristic indicated by reference numeral L1. As shown by reference numeral L2 in comparison with the above, for example, with the original reference voltages VRT and VRB that are potentials at both ends being fixed, the remaining original reference voltages VB to VG are varied within the range indicated by the arrows, and various gamma characteristics are obtained. Can be made variable.

  In this way, the gamma characteristic can be switched by the setting of the original reference voltage generation circuit 12 that generates the original reference voltages VRT, VB to VG, VRB. The controller 7 is formed by a control IC, whereas the horizontal drive circuit 4 is formed by a driver IC. As a result, in the conventional liquid crystal display device 1, it is possible to manufacture products with different gamma characteristics by changing only the control IC. It is made so that it can be shortened. Symbols CA to CH are stray capacitances between these ICs.

  By the way, in such a flat display device, there is a display device using an organic EL element. In the display unit of the display device using such an organic EL element, similarly to the display unit of the liquid crystal display device, the signal line SIG is driven. A method for setting the gradation of each organic EL element has been proposed. Accordingly, it is considered that the display device of the organic EL element according to such a method can be configured using a control IC or the like related to the liquid crystal display device.

  However, in the organic EL element, it is necessary to change the setting of the reference voltages V1 to V64 corresponding to each color because the light emission characteristics are different for each product and the light emission characteristics change with time. become. Accordingly, there is a problem that the display device cannot actually be configured depending on the drive circuit related to the liquid crystal display device described above with reference to FIG. Specifically, the organic EL element needs to adjust the black level and the dynamic range for each color and for each product. It has been found that no adjustment is required for the gamma characteristic itself in the organic EL element. Accordingly, when the original reference voltage generation circuit 12 shown in FIG. 17 is applied, it is necessary to adjust the voltage across the voltage dividing circuit 21 for each product for each color.

  As one method for solving this problem, there is a method in which the original reference voltages VRT, VB to VG, VRB can be set by setting data from the outside. That is, for example, as shown in FIG. 19, a plurality of digital / analog conversion circuits 31A to 31H that respectively generate original reference voltages VRT, VB to VG, and VRB constitute an original reference voltage generation circuit 30, and original reference voltages VRT, VB to VG are formed. , By supplying original reference voltage setting data DV instructing VRB to each of the plurality of digital-analog conversion circuits 31A to 31H, each of the original reference voltages VRT, VB to VG, VRB can be externally adjusted within a predetermined range. Thus, it is considered that the black level and the dynamic range can be adjusted without changing the gamma characteristic to cope with the variation in the light emission characteristic for each color and each product. In addition, it is considered that it is possible to cope with a change in light emission characteristics over time.

  However, in this type of display device, operational amplifier circuits are applied to the amplifier circuits 16A to 16N (FIG. 15), 24A to 24H, and 27A to 27H (FIGS. 17 and 19). If the generation of the original reference voltages VRT, VB to VG, and VRB can be adjusted in this way, the adjustment work for ensuring desired characteristics becomes complicated.

  That is, these operational amplifier circuits 16A to 16N, 24A to 24H, and 27A to 27H are constituted by differential amplifier circuits. Here, the differential amplifier circuit is configured by connecting transistors TR1 and TR2 of a differential pair to a constant current circuit 36 and transistors TR3 and TR4 as shown in the input stage in FIG. In this differential amplifier circuit, the gate dimensions of the transistors TR1 and TR2 forming the differential pair are different during the manufacturing process. As a result, the transistors TR1 and TR2 have different gate-source voltages, and this difference appears as an offset voltage in the output voltage Vout.

  Such an offset voltage is generated independently for each of the original reference voltages VRT, VB to VG, and VRB to vary the original reference voltages VRT, VB to VG, and VRB. The voltages VRT, VB to VG, and VRB are varied. As a result, there are cases where the desired characteristics cannot be ensured simply by setting the original reference voltages VRT, VB to VG, VRB based on the original reference voltage setting data, so that adjustment time is required to secure the desired characteristics. Become.

  Further, as shown in FIG. 21, due to such variations, in the display device, the gamma characteristic varies from the design center characteristic indicated by the symbol L1 in the range indicated by the symbols L2 and L3. 21 is an example showing the adjustment range planned for the design of the original reference voltages VB to VG. In the actual product, the characteristic range shown in FIG. The adjustable range is reduced due to variations. In this case, if the adjustable range based on the design center characteristic is expanded so that the adjustable range can be secured for all products, the resolution related to the adjustment is lowered. If the adjustable range based on the design center characteristic is not expanded in this way, adjustment cannot be performed with a so-called worst-case product having a large variation from the design center characteristic. As a result, the adjustment work becomes complicated, and time is required for the adjustment. In some cases, adjustment may not be possible.

  On the other hand, for example, Japanese Patent Laid-Open No. 2001-343948 proposes a method of canceling the influence of the offset voltage of the operational amplifier circuit by a so-called chopper circuit method. Here, in this method, as shown in FIG. 22 in comparison with FIG. 20, the setting of the input end is switched between the inverting input and the non-inverting input by the switch circuit 37, and the switch circuits 38, 39 are interlocked with this switching. Thus, the input terminal of the input signal is switched, and the output of the output signal is switched so as to correspond to these switching. Here, in switching the output signal, it is conceivable to switch the output terminal of the input stage by the switch circuit 40 as shown in FIG. In Japanese Patent Laid-Open No. 2001-343948, the influence of the offset voltage is canceled by the effect of integration in the time axis direction on the display screen by switching the setting by these chopper methods in units of frame periods. ing. 23A and 23B, in contrast to FIG. 20, these switch circuits 37 to 40 switch the setting of the input terminal between the inverting input and the non-inverting input, and at the input terminal and the input stage of the input signal. It is a connection diagram which shows the state which switched the output terminal of the output signal, respectively.

However, the cancellation of the influence of the offset voltage in units of the frame period has a problem that the display flickers when applied to a display panel using organic EL elements.
JP-A-10-333648 JP 2001-343948 A

  The present invention has been made in consideration of the above points. A driving circuit for a flat display device, which can ensure various desired light emission characteristics by a simple adjustment operation so as to cope with various light emission characteristics. The present invention intends to propose a flat display device using a drive circuit.

  In order to solve such a problem, in the first aspect of the present invention, an input circuit for inputting original reference voltage setting data for instructing setting of an original reference voltage, applied to a driving circuit of a flat display device, and original reference voltage setting data A plurality of digital-to-analog conversion circuits that respectively generate original reference voltages, a plurality of digital-analog conversion circuits for amplifying and outputting a plurality of original reference voltages, and a plurality of resistors A plurality of series-connected voltage dividing circuits are connected in series, and the original reference voltage output from the amplifier circuit is input between both ends and the voltage dividing circuit, respectively, and a plurality of reference voltages are divided by the voltage divided by the plurality of voltage dividing circuits. A reference voltage generation circuit that outputs a voltage, and outputs a drive signal by inputting a plurality of reference voltages and selectively outputting them according to image data related to the corresponding signal line A plurality of selection circuits and a drive signal amplification circuit that amplifies the drive signal output from the selection circuit and outputs the amplified signal to the signal line. The amplification circuit for the original reference signal and / or the drive signal is a chopper type The setting of the chopper method is switched in units of lines, and the setting of the chopper method is switched in units of frames in each line.

  According to a seventh aspect of the present invention, the horizontal drive circuit is applied to the flat display device, and the horizontal drive circuit is responsive to the input circuit for inputting the original reference voltage setting data for instructing the setting of the original reference voltage, and the original reference voltage setting data. A plurality of digital-to-analog conversion circuits for generating original reference voltages, a plurality of digital-to-analog conversion circuits for amplifying and outputting a plurality of original reference voltages, and a plurality of resistors connected in series Multiple voltage dividers are connected in series, the original reference voltage output from the amplifier circuit is input between both ends and the voltage divider circuit, and a plurality of reference voltages are output by the voltage divided by the voltage divider circuits. A plurality of selections for outputting a drive signal by inputting a plurality of reference voltages and selecting and outputting according to image data related to corresponding signal lines And an amplifier circuit for a drive signal that amplifies the drive signal output from the selection circuit and outputs the amplified signal to the signal line. The amplifier circuit for the original reference signal and / or the drive signal is a chopper type operational amplifier circuit The setting by the chopper method is switched in units of lines, and the setting by the chopper method is switched in units of frames in each line.

  According to the configuration of the first aspect, an input circuit that is applied to a driving circuit of a flat display device and inputs original reference voltage setting data for instructing setting of an original reference voltage, and an original reference voltage according to the original reference voltage setting data. A plurality of digital-to-analog conversion circuits, a plurality of digital-to-analog conversion circuits for amplifying and outputting a plurality of original reference voltages, and a voltage dividing circuit having a plurality of resistors connected in series In addition, a plurality of serial connections are made, and the original reference voltage output from the amplifier circuit is input between both ends and the voltage dividing circuit, respectively, and a plurality of reference voltages are output by the divided voltages by the plurality of voltage dividing circuits. A plurality of selection circuits for outputting drive signals by inputting a plurality of reference voltages and selecting and outputting in accordance with image data relating to corresponding signal lines; If so and a amplifier circuit for driving signal output to amplifying the signal line drive signal outputted from the may correspond to the various light-emitting characteristics. At this time, the amplifier circuit for the original reference signal and / or the drive signal is formed by a chopper type operational amplifier circuit, and the setting by the chopper method is switched in units of lines, and in each line, the chopper type is switched in units of frames. If the setting by the method is switched, the so-called chopper circuit method can be applied to cancel the influence of the offset voltage due to the spatial integration effect on the display screen and the integration effect in the time axis direction. Thus, a desired gamma characteristic can be reliably ensured by a simple adjustment operation.

  Thereby, according to the structure of Claim 7, it can respond to various light emission characteristics, and can provide the flat display apparatus which can ensure reliably the desired gamma characteristic by simple adjustment work.

  According to the present invention, a desired gamma characteristic can be reliably ensured by a simple adjustment operation so as to cope with various light emission characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing PDA (Personal Digital Assistants) according to an embodiment of the present invention. In the apparatus main body 42, the PDA 41 displays various images on the display unit 44 by executing predetermined processing procedures with the controller 43, which is arithmetic processing means, in response to the operation of the operator. In FIG. 2, the same components as those described above with reference to FIG.

  Here, in this embodiment, the display unit 44 is a color image display panel in which pixels of organic EL elements are arranged in a matrix, and a vertical drive circuit (not shown) using gate lines connected to the pixels. Thus, the pixels are selected in line units, and the gradation of each pixel is set by driving the signal line SIG.

  When the PDA 41 is shipped from the factory, the light emission characteristics of each color are measured with respect to the display unit 44 using the organic EL element. Based on the measurement results, the original reference voltages VRT, VB to VG, and VRB are set in the memory 50. The original reference voltage setting data DV to be instructed is recorded, and by using this original reference voltage setting data DV, it is possible to correct the variation in the light emission characteristics of each color and the light emission characteristics among the products, and thereby correct white balance The display image can be displayed by color reproducibility.

  In this embodiment, among these original reference voltages VRT, VB to VG, VRB, the original reference voltage VRT having the highest voltage and the original reference voltage VRB having the lowest voltage are the levels of the black level and the white level, respectively. Accordingly, in the following description, these two original reference voltages VRT and VRB will be appropriately referred to as a black level original reference voltage VRT and a white level original reference voltage VRB, respectively. Correspondingly, the original reference voltage setting data DV corresponding to the original reference voltage VRT for black level and the original reference voltage VRB for white level is appropriately set to the original reference voltage setting data for black level, the original reference voltage for white level. These are referred to as setting data, and are indicated by symbols DVVRT and DVVRB, respectively, and correspondingly, original reference voltage setting data DV related to the original reference voltages VB to VG are indicated by symbols DVVB to DVVG, respectively. Thus, the memory 50 holds the black level original reference voltage setting data DVVRT, the white level original reference voltage setting data DVVRB, and other original reference voltage setting data DVVB to DVVG.

  The PDA 41 can adjust a white balance, a black level, and a white level in the display unit 44 by executing a predetermined processing procedure by the controller 43 so as to be able to cope with a change in light emission characteristics with time according to user's preference. The adjustment result is recorded and held in the memory 45, and the display on the display unit 44 is set based on the adjustment result. The PDA 41 corrects the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB among the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB recorded in the memory 50 at the time of factory shipment. Data D2 is recorded and held in the memory 45 for each color in the format of difference data ΔDVVRT and ΔDVRVR corresponding to the original reference voltage setting data DVVRT and DVVRB, and the correction data D2 recorded in the memory 45 is stored in the controller 47. It outputs to the controller 47 at the timing according to the processing. Accordingly, the PDA 41 records and holds the adjustment result such as the white balance adjustment, and further sets the display of the display unit 44 based on the adjustment result.

  The controller 47 is configured by an integrated circuit, and time-division multiplexes the image data DR, DG, DB of each color output from the apparatus main body 42 in units of lines, and outputs image data D1 of one system. The original reference voltage setting data DV is corrected by the correction data D2 output from the controller 43 of the apparatus main body 42 and output to the horizontal drive circuit 55.

  That is, in the controller 47, the timing generator (TG) 58 generates and outputs various timing signals synchronized with the image data D1, DR to DB. The memory control circuit 59 controls the operation of the memory 60 on the basis of this timing signal. The memory 60 sequentially stores and outputs the image data DR to DB output from the apparatus main body 42, thereby outputting the image data DR. , DG and DB are time-division multiplexed in line units to output image data D1.

  The memory control circuit 61 controls the operation of the memory 50 to read the original reference voltage setting data DV from the memory 50 and output it to the original reference voltage setting circuit 63 in the horizontal scanning cycle.

  The original reference voltage setting circuit 63 corrects and outputs the original reference voltage setting data DV output from the memory control circuit 61 with the correction data D2 output from the controller 43 of the apparatus main body 42. That is, as shown in FIG. 3, the original reference voltage setting circuit 63 includes the original reference voltage for black level among the original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB) input via the memory control circuit 61. The setting data DVVRT and the white level original reference voltage setting data DVVRB are input to the adder circuit 63A, where the corresponding correction data D2 (ΔDVVRT, ΔDVVRB) output from the apparatus main body 42 are added, and thereby for the black level. The original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB are corrected. Further, the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB are input to the encoder 63B, and the remaining original reference voltage setting data DVVB to DVVG are selected by the selector (SEL) 63C. The original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB are converted into serial data and output. In the original reference voltage setting circuit 63, the original reference voltage setting separately output from the apparatus main body 42 instead of the original reference voltage setting data DVVB to DVVG output from the memory control circuit 61 as described above is set by the selector 63C. Data can be output.

  In this series of processing, the original reference voltage setting circuit 63 generates and outputs original reference voltage setting data DV corresponding to the driving of the signal line SIG in the horizontal drive circuit 55. In this embodiment, the display unit 44 sets red, green, and blue pixels that are continuous in the horizontal direction as one set, and drives the one set of pixels in a time-division manner using a single drive signal. The reference voltage setting circuit 63 is configured to switch and output the original reference voltage setting data DV for red, green, and blue image data DR, DG, and DB, respectively, during one horizontal scanning period.

  The horizontal drive circuit 55 is configured by an integrated circuit separate from the controller 47, and each set of image data D1 output from the controller 47 is composed of the red, green, and blue pixels that are continuous in the horizontal direction by the shift register 13. After the distribution, the digital / analog conversion processing is performed by the digital / analog conversion circuits 15A to 15N by the selector. The drive signals resulting from the digital-analog conversion processing results are amplified by the amplification circuits 56A to 56N and output to the display unit 44. In the display unit 44, the output signals of the amplification circuits 56A to 56N are respectively output by the selectors 17A to 17N. Allocate to signal line SIG.

  The horizontal drive circuit 55 applies the reference voltages V1 to V64 of the digital / analog conversion circuits 15A to 15N related to such a series of processes according to the original reference voltage setting data DV by the original reference voltage generation circuit 70 and the reference voltage generation circuit 69. Generate.

  FIG. 4 is a block diagram showing the original reference voltage generation circuit 70 and the reference voltage generation circuit 69. Here, the reference voltage generating circuit 69 is formed in the same manner as the reference voltage generating circuit 14 described above with reference to FIG. 17 except that the amplifier circuits 27A to 27H are omitted, and the original reference voltage generating circuit 70 outputs the original voltage. Reference voltages V1 to V64 are generated and output from the reference voltages VRT, VB to VG, and VRB by resistance voltage division.

  In the original reference voltage generation circuit 70, original reference voltages VRT, VB to VG, and VRB are generated by digital / analog conversion circuits (D / A) 71A to 71H according to the original reference voltage setting data DV, respectively.

  Here, among the digital / analog conversion circuits 71A to 71H, the digital / analog conversion circuits 71A and 71H related to the generation of the black level original reference voltage VRT and the white level original reference voltage VRB are divided by the voltage dividing circuits 72A and 72H, respectively. The generation voltage VCOM is divided to generate a plurality of original reference voltage candidate voltages. Here, the voltage dividing circuits 72A and 72H are constituted by a series circuit of a plurality of resistors having the same resistance value, and the reference voltage generating voltage VCOM is divided and output with a resolution corresponding to the number of bits of the original reference voltage setting data DV. . In this embodiment, the original reference voltage setting data DV is formed by 6 bits, and the reference voltage generation voltage VCOM is set to 5 [V], so that the voltage dividing circuits 72A and 72H are about 80 [mV]. ] 64 types of candidate voltages having different voltages are output in units of (≈5 [V] / 64).

  The selectors 73A and 73H select 64 types of candidate voltages output from the voltage dividing circuits 72A and 72H, respectively, according to the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB. Output. The selectors 73A and 73H output the black level original reference voltage VRT and the white level original reference voltage VRB generated in this way via the amplifier circuits 76A and 76H, respectively.

  On the other hand, the other digital analog conversion circuits 71B to 71G other than the digital analog conversion circuits 71A and 71H are respectively subjected to the original reference by the resistance voltage division by the voltage dividing circuits 72B to 72G, similarly to the digital analog conversion circuits 71A and 71H. A plurality of types of candidate voltages of the voltages VB to VG are generated, and the plurality of types of candidate voltages are selected by the selectors 73B to 73G according to the original reference voltage setting data DV, and the original reference voltages VB to VG are output. In the digital / analog conversion circuits 71B to 71G, voltage dividing circuits 72B to 72G for generating candidate voltages of the original reference voltages VB to VG are connected in series between the digital / analog conversion circuits 71B to 71G. The black level original reference voltage VRT and white level original reference voltage VRB by 71A and 71H are connected.

  Thus, as shown in FIG. 5, among these original reference voltages VRT, VB to VG, VRB, the original reference voltages VB to VG excluding the black level original reference voltage VRT and the white level original reference voltage VRB are respectively It is difficult to vary the voltage only within the range of candidate voltages output from the voltage divider circuits 72B to 72G connected in series. As a result, as shown in FIG. 6 in comparison with FIG. Even when the original reference voltage setting data DV is erroneously set due to noise mixing, output of a drive signal due to extreme gamma characteristics can be prevented, and significant image quality degradation due to noise can be prevented.

  Further, both ends of the voltage dividing circuits 72B to 72G connected in series in this way are connected to the original reference voltages VRT and VRB which are the first and second original reference voltages, so that dynamic range adjustment, black level When the original reference voltages VRT and VRB are varied in order to correct variations in light emission characteristics between colors and light emission characteristics between products by adjustment, as shown in FIG. 7 in comparison with FIG. The original reference voltages VB to VG also change following the changes of the original reference voltages VRT and VRB by the resistance voltage dividing ratios of the voltage dividing circuits 72B to 72G connected in series. With respect to the voltages VB to VG, it is possible to omit the process of re-setting, thereby omitting the calculation process related to these remaining digital-analog conversion circuits. It is adapted to be able to simplify the integer operations.

  The original reference voltage generation circuit 70 supplies the original reference voltages VB to VG output from the digital / analog conversion circuits 71B to 71G via the amplifier circuits 76B to 76G, the original reference voltage VRT for white level, and the original reference voltage for white level. It is output to the reference voltage generation circuit 69 together with VRB.

  The decoder 75 sequentially takes in the original reference voltage setting data DV by serial data output from the controller 47, distributes it to the digital / analog conversion circuits 71A to 71H at the timing corresponding to the switching of the contacts in the selectors 17A to 17N.

  FIG. 8 is a characteristic curve diagram showing an example of the gamma characteristic realized in this way. In this embodiment, for example, the gamma characteristic can be varied by setting the original reference voltage setting data DV as shown by the reference L2A with respect to the characteristic curve shown by the reference L1A. A desired image can be displayed. Also, by setting the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB, the black level and the white level are set for each color and for each product, and the variation of the light emission characteristics for each color and for each product, It is designed to be able to cope with a change in light emission characteristics over time. Further, by storing two types of data in the memory 50 so as to correspond to the line inversion, or by switching the correction data D2 corresponding to the line inversion, the gamma characteristics relating to the liquid crystal display panels indicated by the symbols L3 and L4. Has also been made possible.

  In such a configuration, in the horizontal drive circuit 55, the original reference voltage generation circuit 70 is integrated with the reference voltage generation circuit 69 and the digital / analog conversion circuits 15A to 15N, whereby the original reference voltages VRT and VB to VG are integrated. , The number of amplifier circuits related to the path for outputting VRB from the original reference voltage generation circuit 70 to the reference voltage generation circuit 69 is reduced as compared with the conventional one, and the offset voltage of the operational amplifier circuit in the drive system of the signal line SIG is correspondingly reduced. The effect on the display by is reduced.

  The amplifier circuits 76A to 76H and 56A to 56N provided in the driving system of the signal line SIG are formed by the so-called chopper circuit system described above with reference to FIG. The setting by this chopper method is switched by the timing shown in FIG. 1 by the timing signal.

  That is, the amplifier circuits 56A to 56N that output the drive signal to the signal line SIG are controlled by the timing generator 58 based on the vertical synchronization signal Vsync (FIG. 1A) and the horizontal synchronization signal Hsync (FIG. 1B). Change the setting in units of lines. Specifically, in this embodiment, the setting is switched for each line, thereby canceling the influence of the offset voltage between successive lines due to the spatial integration effect on the display screen (FIG. 1C). These amplifier circuits 56A to 56N also switch the setting for each line in units of frames. Specifically, in this embodiment, the setting is switched for each frame, thereby ensuring the integration effect in the time axis direction on the display screen to cancel the influence of the offset voltage.

  Similarly, in the amplification circuits 76A to 76H that output the original reference voltages VRT, VB to VG, and VRB, the setting is switched for each line in units of lines, and this is continuously performed by the spatial integration effect on the display screen. The influence of the offset voltage is canceled between the lines to be performed (FIG. 1D). The amplifying circuits 76A to 76H also switch the setting for each line in units of frames for each line, thereby ensuring the integration effect in the time axis direction on the display screen and canceling the influence of the offset voltage. It is made like that.

  That is, as shown in FIG. 9, with respect to the gamma characteristic based on the original reference voltage setting data DV indicated by reference numeral L4, as indicated by reference numerals L5 and L6, the original reference voltages VRT, VB˜ Even when the VG and VRB are offset and the gamma characteristics are changed, the switching of such settings in the amplifier circuits 76A to 76H causes the original reference voltage as shown in FIG. In the offsets of VRT, VB to VG, and VRB, the offset direction can be reversed with respect to the gamma characteristic indicated by the symbol L4, thereby canceling the influence of the offset voltage.

  Accordingly, as shown in FIG. 11 in comparison with FIG. 21, in this embodiment, a sufficiently adjustable range of the gamma characteristic is sufficiently ensured and can be adjusted easily and reliably.

(2) Operation of Embodiment In the above configuration, in this PDA 41 (FIG. 2), image data DR to DB for display is input from the apparatus main body 42 to the controller 47, and here, in line units via the memory 60 Time-division multiplexing processing is performed so that image data relating to the same color is continuous, and image data D 1 as a result of the processing is input to the horizontal drive circuit 55. In the horizontal drive circuit 55, the image data D1 is taken into the shift register 13, and the image data relating to the same color is input to the digital / analog conversion circuits 15A to 15N in parallel in units of lines. The digital-analog conversion circuits 15A to 15N convert the signals into drive signals, which are input to the selectors 17A to 17N via the amplifier circuits 56A to 56N, respectively. As a result, the image data D1 is a combination of the red, green, and blue pixels with respect to the pixels by the organic EL elements that are cyclically repeated in the horizontal direction in the order of red, green, and blue in the display unit 44. After being distributed, the signal is converted into a drive signal, and the drive signal is distributed to the signal lines SIG related to the red, green, and blue pixels by the selectors 17A to 17N, and thus the PDA 41 uses the image data DR to DB for each pixel. The gradation is set and a desired image is displayed.

  Also, in the original reference voltage generation circuit 70 (FIG. 4), a plurality of original reference voltages VRT, VB to VG, VRB are generated, and a plurality of voltage dividing circuits R1 to R7 formed by connecting a predetermined number of resistors in series are provided. Further, in the reference voltage generation circuit 69 using a resistor series circuit connected in series, the original reference voltages VRT, VB to VG, VRB are divided to form reference voltages V1 to V64. In the digital analog conversion circuits 15A to 15N, In response to the selection of the reference voltages V1 to V64, the image data D1 is subjected to digital-analog conversion processing to generate a drive signal. Is generated and an image is displayed.

  Thus, in the organic EL element, although the gamma characteristic itself does not vary, the light emission characteristic differs for each color and for each product, and the light emission characteristic changes with time. On the other hand, the PDA 41 divides the black level original reference voltage VRT and the white level original reference voltage VRB by the voltage dividing circuits 32B to 32G to generate the original reference voltages VB to VG. Reference voltages V1 to V64 are generated by dividing VB to VG and VRB by voltage dividing circuits R1 to R7. Thus, the image data DR to DB are digital-analog converted to generate a drive signal, and the black level original reference voltage VRT and the white level original reference voltage VRB are set for each color and each product. Therefore, it is necessary to correct so as to cope with the change with time.

  For this reason, the PDA 41 measures the light emission characteristics for each color and for each product, and based on the measurement results, the original reference voltages for instructing the settings of the original reference voltages VRT, VB to VG, VRB can be secured. Setting data DV is recorded and held in the memory 50. In addition, correction data D <b> 2 for correcting the change with time of the light emission characteristics is recorded in the memory 45. In the PDA 41, after the original reference voltage setting data DV is corrected by the correction data D2 in the original reference voltage setting circuit 63, it is sequentially input to the horizontal drive circuit 55 corresponding to time division multiplexing of the image data D1. The

  In the horizontal drive circuit 55, the original reference voltage setting data DV is divided into respective systems of original reference voltages VRT, VB to VG, VRB by the decoder 75, and these original reference voltage setting data DV are converted into digital / analog conversion circuits 71A to 71A. Digital analog conversion processing is performed by 71H to generate original reference voltages VRT, VB to VG, VRB.

  Thus, in this embodiment, by setting the original reference voltage setting data DV, various light emission characteristics can be dealt with, and various display panels can be dealt with easily and quickly. That is, the dynamic range adjustment, black level adjustment, and gamma characteristics can be changed simply by changing the data, so that the development period can be greatly shortened compared to the conventional case, and the effort required for development can also be reduced.

  This also makes it possible to flexibly deal with variations in emission characteristics from color to color and from product to product, and changes in light emission characteristics due to changes over time. Such variations in characteristics, deviations in white balance due to changes over time, and color reproducibility. It is possible to provide a high-quality display image by effectively avoiding deterioration of the image.

  In this way, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV so as to be able to cope with various light emission characteristics. In this PDA 41, the amplifier circuits 76A to 76H by the operational amplifier circuit are provided. The original reference voltages VRT, VB to VG, VRB are input to the resistor series circuit 26 of the reference voltage generation circuit 69. In addition, each drive signal is input to the selectors 17A to 17N via the similar amplifier circuits 56A to 56N, and is output to each signal line SIG. As a result, the drive signal output to the signal line SIG in this way is input to each pixel by changing the characteristic of the original reference voltage setting data DV by the offset voltage by the amplifier circuits 76A to 76H and 56A to 56N. The

  In this embodiment, an operational amplifier circuit using a chopper circuit system is applied to the amplifier circuits 76A to 76H and 56A to 56N, and the setting of the input end is switched between the inverting input and the non-inverting input for each line in units of lines. At the same time, the output of the input signal and the output of the output signal at the input stage are switched, thereby canceling the influence of the offset voltage due to the spatial integration effect on the display screen. In each line, the setting of the amplifier circuits 76A to 76H and 56A to 56N is switched for each frame in units of frames, thereby using the integration effect in the time axis direction on the display screen to change the offset voltage. The effect is cancelled.

  Thus, in this embodiment, the desired characteristics can be ensured with high accuracy by the original reference voltage setting data DV, and the desired characteristics can be reliably secured by a simple adjustment operation. Further, it is possible to reduce the decrease in the adjustable range, and it is also possible to ensure the desired characteristics by simple adjustment work.

  In this way, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV so that the light emission characteristics can be variously corrected. In this PDA 41, the digital / analog conversion circuits 71A, 71H at both ends are arranged. Then, the reference voltage generation voltage VCOM is divided by the voltage dividing circuits 72A and 72H to generate a plurality of candidate voltages for the original reference voltages VRT and VRB, respectively, and the plurality of candidate voltages are selected by the original reference voltage setting data DV. The original reference voltages VRT and VRB are generated. Thereby, in these original reference voltages VRT and VRB, various voltages can be set between the reference voltage generating voltage VCOM and the ground potential.

  On the other hand, in the digital-analog conversion circuits 71B to 71G related to the remaining original reference voltages VB to VG, the voltage dividing circuits 72B to 72G are connected in series and both ends are connected to the original reference voltages VRT and VRB. The voltage dividing circuits 72B to 72G respectively divide and generate a plurality of candidate voltages of the original reference voltages VB to VG. The plurality of candidate voltages are selected by the original reference voltage setting data DV to generate the original reference voltages VB to VG. Is done.

  As a result, the original reference voltages VB to VG are held such that the voltage changes only within the range of candidate voltages output from the voltage dividing circuits 72B to 72G connected in series, respectively. Even when the original reference voltage setting data DV is erroneously set due to mixing, it is possible to prevent the output of a drive signal due to extreme gamma characteristics and to prevent significant image quality degradation due to noise.

  In addition, both ends of the voltage dividing circuits 72B to 72G connected in series in this way are connected to the original reference voltages VRT and VRB, so that the original reference voltages VRT and VRB are adjusted by dynamic range adjustment and black level adjustment. When variable, the original reference voltages VB to VG change following the changes of the original reference voltages VRT and VRB by the resistance voltage dividing ratios of the voltage dividing circuits 72B to 72G connected in series. As a result, for these original reference voltages VB to VG, the process of resetting the remaining original reference voltages VB to VG in the dynamic range adjustment and the black level adjustment can be omitted. The calculation process related to the original reference voltages VB to VG can be omitted, and the adjustment work can be simplified.

  Further, in this way, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV, and the original reference voltage setting corresponding to the time division multiplexing processing related to the transmission of the image data D1. By switching the data DV, one system of the original reference voltage generation circuit can be shared for the processing of the image data of each color, whereby the overall configuration can be simplified.

  As a result, the PDA 41 eventually switches the original reference voltage setting data DV three times in one line. As a result, even when the gamma characteristic is erroneously set due to noise mixing, for example, the erroneous gamma setting due to the influence of noise can be stopped in one line, thereby reducing image quality degradation due to noise. .

  Thus, in the PDA 41, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV in this way, and the original reference voltages VRT, VB to VG, VRB are generated. By providing the circuit on the side of the reference voltage generation circuit and integrating it as an integrated circuit, the original reference voltage generation circuit 70 can omit the amplifier circuit used to output the original reference voltages VRT, VB to VG, and VRB. . Thereby, the configuration can be simplified and power consumption can be reduced accordingly. Further, since this amplifier circuit is not required, the influence of the offset voltage by the operational amplifier circuit can be reduced correspondingly, and the original reference voltages VRT, VB to VG, VRB input to the reference voltage generation circuit are correspondingly reduced. The accuracy can be improved, thereby improving the accuracy of the gamma setting and improving the productivity.

(3) Effects of the embodiment According to the configuration described above, the amplifier circuit related to the signal line drive system is configured as an operational amplifier circuit using a chopper circuit system, and the setting is switched in units of lines and frames. By removing the influence of the offset voltage by the temporal integration effect, it is possible to cope with various light emission characteristics, and a desired gamma characteristic can be reliably ensured by a simple adjustment operation.

  FIG. 12 is a time chart illustrating switching of the settings of the amplifier circuits 56A to 56N and 76A to 76H according to the second embodiment in comparison with FIG. The PDA according to this actual example is configured in the same manner as the PDA 41 according to the first embodiment described above except that the configurations related to the amplifier circuits 56A to 56N and 76A to 76H are different.

  In this embodiment, the amplifier circuits 56A to 56N are set for each line under the control of the timing generator 58 based on the vertical synchronization signal Vsync (FIG. 12A) and the horizontal synchronization signal Hsync (FIG. 12B). Thus, the influence of the offset voltage between successive lines is canceled by the spatial integration effect on the display screen (FIG. 12C). In addition, the amplification circuits 56A to 56N switch the setting for each frame for each frame, thereby ensuring the integration effect in the time axis direction on the display screen and canceling the influence of the offset voltage. .

  On the other hand, in the amplification circuits 76A to 76H, the setting is switched every two lines, thereby canceling the influence of the offset voltage due to the spatial integration effect on the display screen (FIG. 12D). In addition, the amplification circuits 76A to 76H change the setting for each line for each frame, thereby ensuring the integration effect in the time axis direction on the display screen to cancel the influence of the offset voltage. .

  As in this embodiment, the same effect as that of the first embodiment can be obtained even when the setting switching in the amplifier circuit related to the output of the original reference voltage is executed every two lines.

  FIG. 13 is a time chart illustrating switching of the settings of the amplifier circuits 56A to 56N and 76A to 76H according to the third embodiment in comparison with FIG. The PDA according to this actual example is configured in the same manner as the PDA 41 according to the first embodiment described above except that the configurations related to the amplifier circuits 56A to 56N and 76A to 76H are different.

  In this embodiment, the amplifier circuits 56A to 56N are set for each line by the control of the timing generator 58 based on the vertical synchronization signal Vsync (FIG. 13A) and the horizontal synchronization signal Hsync (FIG. 13B). Thus, the influence of the offset voltage is canceled by the spatial integration effect on the display screen (FIG. 13C). In addition, the amplification circuits 56A to 56N are configured to switch the setting for each line for each frame, thereby ensuring the integration effect in the time axis direction on the display screen and canceling the influence of the offset voltage. ing.

  On the other hand, in the amplification circuits 76A to 76H, the setting is switched every four lines, thereby canceling the influence of the offset voltage due to the spatial integration effect on the display screen (FIG. 13D). In addition, the amplification circuits 76A to 76H change the setting for each line for each frame, thereby ensuring the integration effect in the time axis direction on the display screen to cancel the influence of the offset voltage. .

  As in this embodiment, the same effect as that of the first embodiment can be obtained by switching the setting in the amplifier circuit related to the output of the original reference voltage every four lines.

  In the above-described embodiment, the case where the chopper circuit method is applied to the amplifier circuit for both the drive signal and the original reference voltage to drive the line unit and the frame unit is described, but the present invention is not limited to this. One may be switched only in line units or frame units, and one may be omitted from applying the chopper circuit method.

  Further, in the above-described embodiment, the case where the output signal output is switched at the input stage to configure the chopper type amplifier circuit has been described. However, the present invention is not limited to this, for example, the output signal output is switched at the output stage. Therefore, the present invention can be widely applied to a case where an amplifier circuit using a chopper method is configured.

  In the above-described embodiment, the case where the original reference voltage is generated by the digital-analog conversion circuit has been described. However, the present invention is not limited to this, and the original reference voltage is set by the wiring pattern setting as described above with reference to FIG. It can be widely applied to the case of generating.

  In the above-described embodiments, the case where the present invention is applied to a PDA has been described. However, the present invention is not limited to this and can be widely applied to various video devices.

  The present invention relates to a driving circuit for a flat display device and a flat display device, and can be applied to a display device using an organic EL element, for example.

It is a time chart which shows switching of the setting of the amplifier circuit of PDA which concerns on the Example of this invention. It is a block diagram which shows PDA based on the Example of this invention. FIG. 3 is a block diagram showing an original reference voltage setting circuit in the PDA of FIG. 2. FIG. 3 is a block diagram showing an original reference voltage generation circuit and a reference voltage generation circuit in the PDA of FIG. 2. It is a characteristic curve figure with which it uses for description of the gamma characteristic in PDA of FIG. It is a characteristic curve figure with which it uses for description of the influence of the noise in PDA of FIG. FIG. 3 is a characteristic curve diagram for explaining dynamic range adjustment in the PDA of FIG. 2. FIG. 3 is a characteristic curve diagram illustrating a setting example of gamma characteristics in the PDA of FIG. 2. It is a characteristic curve figure with which it uses for description of the change of the gamma characteristic by the offset voltage of an amplifier circuit. It is a characteristic curve figure with which it uses for description of the cancellation of the influence by the offset voltage of an amplifier circuit. It is a characteristic curve figure which shows the gamma correction by the cancellation of the influence by the offset voltage of an amplifier circuit. It is a time chart which shows switching of the setting of the amplifier circuit of PDA which concerns on Example 2 of this invention. It is a time chart which shows switching of the setting of the amplifier circuit of PDA which concerns on Example 3 of this invention. It is a block diagram which shows the conventional liquid crystal display device. It is a block diagram which shows the horizontal drive circuit in the liquid crystal display device of FIG. 13 with a periphery structure. It is a time chart with which it uses for description of FIG. FIG. 15 is a block diagram illustrating an original reference voltage generation circuit and a reference voltage generation circuit in the horizontal drive circuit and controller of FIG. 14. It is a characteristic curve figure with which it uses for description of the gamma characteristic in the liquid crystal display device of FIG. It is a block diagram which shows the example of the original reference voltage generation circuit by a digital analog conversion circuit. It is a connection diagram which shows the structure of the input stage of a differential amplifier circuit. It is a characteristic curve figure with which it uses for description of the change of the adjustable range by an offset voltage. It is a connection diagram with which it uses for description by a chopper circuit system. FIG. 23 is a connection diagram illustrating setting switching by connection in FIG. 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2, 44 ... Display part, 3R, 3G, 3B ... Pixel, 4, 55 ... Horizontal drive circuit, 6, 42 ... Device main body, 7, 43, 47 ... Controller, 9, 59, 61 ... Memory control circuit, 10, 45, 50, 60 ... Memory, 12, 30, 70 ... Original reference voltage generation circuit, 13 ... Shift register, 14, 69 ... Reference voltage generation circuit 15A to 15N, 31A to 31H, 71A to 71H... Digital-to-analog conversion circuit, 16A to 16N, 24A to 24H, 27A to 27H, 56A to 56N, 76A to 76H. ... Selector, 21, 72A to 72H, R1 to R7 ... Voltage divider circuit, 26 ... Resistance series circuit, 63 ... Original reference voltage setting circuit, 75 ... Decoder

Claims (8)

In a drive circuit of a flat display device for generating a drive signal by performing digital-analog conversion processing on image data, and driving a signal line of a display unit in which pixels are arranged in a matrix by the drive signal,
An input circuit for inputting original reference voltage setting data for instructing setting of the original reference voltage;
In accordance with the original reference voltage setting data, a plurality of digital-analog conversion circuits that respectively generate original reference voltages;
An amplification circuit for original reference voltage that amplifies and outputs a plurality of original reference voltages by the plurality of digital-analog conversion circuits;
A plurality of voltage dividing circuits in which a plurality of resistors are connected in series are further connected in series, and the original reference voltage output from the amplifier circuit is input between both ends and the voltage dividing circuit, respectively. A reference voltage generation circuit that outputs a plurality of reference voltages by the divided voltage by
A plurality of selection circuits for outputting the drive signal by inputting the plurality of reference voltages and selectively outputting the selected reference voltages according to the image data of the corresponding signal lines;
A drive signal amplification circuit that amplifies the drive signal output from the selection circuit and outputs the amplified signal to the signal line;
The amplification circuit for the original reference voltage and / or drive signal is
Formed by a chopper-type operational amplifier circuit,
Switching the setting by the chopper method in units of lines,
In each line, the setting circuit according to the chopper method is switched on a frame-by-frame basis. 2. The driving circuit for a flat display device according to claim 1, wherein switching in units of the lines in the amplification circuit for the original reference voltage and the driving signal is switching for each line. 3. Switching in units of the lines in the driving signal amplifier circuit is switching for each line,
2. The driving circuit for a flat display device according to claim 1, wherein switching in units of the lines in the amplification circuit for the original reference voltage is switching for every two lines. Switching in units of the lines in the driving signal amplifier circuit is switching for each line,
2. The driving circuit for a flat display device according to claim 1, wherein switching in units of the lines in the amplification circuit for the original reference voltage is switching for every four lines. The digital-to-analog converter circuit is
A voltage dividing circuit for generating a plurality of candidate voltages of the original reference voltage;
The flat display device according to claim 1, further comprising: a selection circuit that outputs the original reference voltage by inputting the plurality of candidate voltages and selectively outputting the candidate voltage according to the original reference voltage setting data. Drive circuit. The driving circuit for a flat display device according to claim 1, wherein the original reference voltage generation circuit, the reference voltage generation circuit, the selection circuit, and the input circuit are integrated into an integrated circuit. In a flat display device that displays an image based on image data,
A display unit in which pixels are arranged in a matrix;
A horizontal drive circuit for driving the signal line of the display unit by a drive signal,
The horizontal drive circuit includes:
An input circuit for inputting original reference voltage setting data for instructing setting of the original reference voltage;
In accordance with the original reference voltage setting data, a plurality of digital-analog conversion circuits that respectively generate original reference voltages;
An amplification circuit for original reference voltage that amplifies and outputs a plurality of original reference voltages by the plurality of digital-analog conversion circuits;
A plurality of voltage dividing circuits in which a plurality of resistors are connected in series are further connected in series, and the original reference voltage output from the amplifier circuit is input between both ends and the voltage dividing circuit, respectively. A reference voltage generation circuit that outputs a plurality of reference voltages by the divided voltage by
A plurality of selection circuits for outputting the drive signal by inputting the plurality of reference voltages and selectively outputting the selected reference voltages according to the image data of the corresponding signal lines;
A drive signal amplification circuit that amplifies the drive signal output from the selection circuit and outputs the amplified signal to the signal line;
The amplification circuit for the original reference voltage and / or drive signal is
Formed by a chopper-type operational amplifier circuit,
Switching the setting by the chopper method in units of lines,
In each line, the setting according to the chopper method is switched on a frame-by-frame basis. The digital-to-analog converter circuit is
A voltage dividing circuit for generating a plurality of candidate voltages of the original reference voltage;
The flat display device according to claim 7, further comprising: a selection circuit that outputs the original reference voltage by inputting the plurality of candidate voltages and selectively outputting the candidate voltage according to the original reference voltage setting data. .

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