JP2008046371A - Signal processing circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct tailing that occurs in a boundary portion of a black window or a black line displayed by a dot line inversion driving system and behind the boundary potion along scanning. <P>SOLUTION: A tailing correcting circuit 64 sets a weighting factor to each signal level of video signals in an odd-numbered line and an even-numbered line from a dot line inversion circuit 63 on the basis of the timing pulse from a timing generator 65 under the control of a microcomputer 55, and calculates a difference between the sum of the weighting factors on the odd-numbered lines and the sum of the weighting factors on the even-numbered lines to detect a pixel position where tailing occurs. This invention can be applied to a liquid crystal display system that processes video signals for displaying a video on an LCD panel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal processing circuit and method, and more particularly to correcting a boundary portion such as a black window or a black line displayed on a display device driven by a dot line inversion driving method and a tail generated behind the scanning of the boundary portion. The present invention relates to a signal processing circuit and method that can be used.

  In a display device in which pixels are arranged in a matrix, for example, an active matrix liquid crystal display (LCD), as a driving method, each pixel is sequentially driven pixel by line (line). A dot sequential drive system is known. As the dot sequential driving method, there are a 1H inversion driving method and a dot inversion driving method.

  In the 1H inversion driving method, when writing a video signal, there is a resistance component between the left and right pixels in a line (hereinafter referred to as Cs line) that supplies a predetermined DC voltage to each pixel as a common voltage VCOM. There is a parasitic capacitance between the Cs line and the signal line. Due to these reasons, in the 1H inversion driving method, the video signal jumps into the Cs line and the gate line, and the potential of the Cs line fluctuates in the direction of the same polarity as the video signal. Or, shading failure may occur, and the image quality may be greatly impaired.

  Further, while the pixel holds pixel information for one field period, the potential of the signal line fluctuates every 1H (H is a horizontal scanning period). Here, in the case of the 1H inversion driving method, since the polarities of the video signals written in the adjacent left and right pixels are the same, the fluctuation of the potential of the signal line becomes large. Since it jumps into the pixel by source / drain coupling, the crosstalk in the vertical direction becomes conspicuous, causing image quality defects.

  On the other hand, in the dot inversion driving method, since video signals are simultaneously written in opposite polarities to adjacent left and right pixels, fluctuations in the potentials of the Cs line and signal line are canceled between adjacent pixels, so that 1H inversion driving is performed. The problem of poor image quality of the system can be solved. However, on the other hand, since the polarities of the video signals written to the adjacent left and right pixels are different, it is affected by the electrolysis of the adjacent pixels, and therefore a domain (light-outflow region) is generated at the corner of the pixel opening. There is. As a result, the aperture ratio of the pixel is lowered and the transmittance is lowered, leading to a reduction in contrast.

  On the other hand, in the pixel array after the video signal is written, the odd number rows between the adjacent pixel columns so that the polarities of the pixels are the same in the adjacent left and right pixels and the opposite polarity in the upper and lower pixels. There has been proposed a dot line inversion driving method in which video signals having opposite polarities are simultaneously written to pixels in two separate rows, for example, the upper and lower rows.

  In this dot line inversion driving method, as in the case of the dot inversion driving method, video signals having opposite polarities are given to adjacent signal lines, and the polarity of the pixels in the pixel array after writing the video signal is As in the case of the 1H inversion driving method, the left and right pixels adjacent to each other have the same polarity, so that a decrease in contrast can be suppressed without decreasing the aperture ratio of the pixels.

  Incidentally, tailing may occur in a display panel driven by the dot line inversion driving method. For example, as shown in FIG. 1, this tailing is luminance unevenness that occurs at the upper edge and the lower edge portion of the black window 11 when the black window 11 is displayed on the gray background screen 1 or the like. is there.

  In the example of FIG. 1, a gray background screen 1 displayed on a display panel driven by a dot line inversion driving method is shown. In the screen 1, the arrow direction from left to right is the scan direction. ing. A black window 11 is displayed at the center of the screen 1, and the white edge and the black edge are scanned behind the upper edge and the lower edge of the black window 11 and behind the upper edge and the lower edge as shown by the white dotted line. In addition, tailing that is uneven brightness of black has occurred.

  FIG. 2 shows an enlarged view of the right part of the black window 11 in the screen 1 of FIG. The squares represent the pixels constituting the screen 1. The pixels in the second to fourth rows from the top and the first to fourth columns from the left are pixels that display the black window 11. The other pixels are pixels that display the background (gray).

  As shown in FIG. 2, in the dot line inversion driving method, each gate line (Gate_Line) is connected so as to go back and forth between the next line and the original line every other pixel. As shown in the pixels marked with B and the pixels marked with B, data (signal) lines (Data_Line) 1 and 2, data lines 3 and 4, data lines 5 and 6, data lines 7 and 8,. When there is a potential difference between the lines, the fluctuation of the Cs line and the signal line becomes unbalanced, which is caused by insufficient writing. Except for the edge portion, the Cs line and signal line fluctuations are canceled out, so that no tailing occurs.

  That is, due to the occurrence of tailing, pixels marked with A at the edge of the black window 11 become whitish than gray to be displayed, as represented by white, and pixels marked with B As shown by the fine hatching, it becomes darker than the gray that should be displayed.

  Here, Patent Document 1 proposes that correction processing by signal processing is performed on insufficiently written pixels of a liquid crystal display device in a dot line inversion driving method.

JP 2003-316332 A

  However, in the proposal of Patent Document 1, it is determined whether or not to correct from the correction pixel, the pixel written immediately before the correction pixel, and the video signal of the pixel written immediately after the correction pixel. Therefore, for example, when a black window is displayed on a gray background, only insufficiently written pixels that occur on the upper or lower side of the black window display can be corrected.

  That is, in the tailing phenomenon by the dot line inversion driving method, when the black window 11 on the gray background is displayed on the screen 1 as described above with reference to FIG. In addition, luminance unevenness may occur not only behind the scan of the boundary portion, but in the proposal of Patent Document 1, it is difficult to correct a portion existing in the gray area after the scan of the boundary portion.

  As described above, in the conventional dot line inversion driving method, it has been difficult to surely correct the boundary portion such as a black window or a black line and the tail that occurs behind the scanning of the boundary portion.

  The present invention has been made in view of such a situation, and reliably corrects a boundary portion such as a black window or a black line displayed by a dot line inversion driving method and a tail generated behind the scanning of the boundary portion. It is something that can be done.

  A signal processing circuit according to one aspect of the present invention is a signal processing circuit that processes a video signal output to a display device driven by a dot line inversion driving method, and that corresponds to a signal level of a first video signal that passes through a line memory. A first weighting factor calculating means for setting a first weighting factor and calculating a sum of the first weighting factors; and a second weighting factor corresponding to the signal level of the second video signal not passing through the line memory. A second weighting factor calculating unit that sets a weighting factor and calculates a sum of the second weighting factors; and the first and second weighting factors calculated by the first and second weighting factor calculating units Difference amount calculation means for obtaining a difference amount of the sum of coefficients, and correction means for correcting the signal levels of the first and second video signals based on the difference amount obtained by the difference amount calculation means. .

  The information processing apparatus may further include storage means for storing a threshold value at the signal level for setting the first and second weighting factors.

  A correction coefficient for each gradation of the signal levels of the first and second video signals is calculated, and the first and second correction coefficients are calculated based on the difference amount and the correction coefficient obtained by the difference amount calculation means. Correction amount calculation means for calculating the correction amount of the signal level of the video signal is further provided, and the correction means sets the correction amount of the signal level of the first and second video signals calculated by the correction amount calculation means. Based on this, signal levels of the first and second video signals can be corrected.

  Storage means for storing a correction coefficient for a predetermined gradation of the signal level is further provided, and the correction amount calculation means is configured to perform the first and first corrections based on the correction coefficient for the predetermined gradation stored in the storage means. The correction coefficient for each gradation of the signal level of the two video signals can be calculated.

  A signal processing method according to one aspect of the present invention is a signal processing method of a signal processing circuit that processes a video signal output to a display device driven by a dot line inversion driving method, and a signal of a first video signal that passes through a line memory. A first weighting factor is set according to the level, the sum of the first weighting factors is calculated, and a second weighting factor is set according to the signal level of the second video signal that does not pass through the line memory Then, a sum of the second weighting factors is calculated, a difference amount of the calculated sum of the first and second weighting factors is obtained, and the first and second weighting factors are obtained based on the obtained difference amount. And a step of correcting the signal level of the second video signal.

  In one aspect of the present invention, a first weighting factor corresponding to the signal level of the first video signal passing through the line memory is set, a sum of the first weighting factors is calculated, and the line memory is passed through. A second weighting factor corresponding to the signal level of the second video signal that is not present is set, and the sum of the second weighting factors is calculated. Then, a difference amount of the calculated sum of the first and second weight coefficients is obtained, and the signal levels of the first and second video signals are corrected based on the obtained difference amount.

  According to the present invention, it is possible to reliably correct a boundary portion such as a black window or a black line displayed by the dot line inversion driving method, and a tail generated behind scanning of the boundary portion.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  A signal processing circuit according to one aspect of the present invention is a signal processing circuit (for example, the digital signal in FIG. 3) that processes a video signal output to a display device (for example, the LCD panel 54 in FIG. 3) driven by a dot line inversion driving method. In the signal driver IC 52), a first weight coefficient corresponding to the signal level of the first video signal passing through the line memory (for example, the line memory 104 in FIG. 4) is set, and the sum of the first weight coefficients is calculated. First weighting factor calculating means for calculating (for example, comparison / weighting factor calculating circuit 152-1 in FIG. 8) and a second weighting factor corresponding to the signal level of the second video signal that does not pass through the line memory. A second weighting factor calculating means (for example, the comparison / weighting factor calculating circuit 152-2 in FIG. 8) for calculating the sum of the second weighting factors, and the first and second weighting factor calculation Calculated by means Based on the difference amount calculating means (for example, the difference amount calculating circuit 153 in FIG. 8) for obtaining the difference amount of the sum of the first and second weighting coefficients and the difference amount obtained by the difference amount calculating means. Correction means (for example, addition / subtraction circuits 157-1 and 157-2 in FIG. 8) for correcting the signal levels of the first and second video signals.

  A storage unit (for example, the register 151 in FIG. 8) for storing a threshold value at the signal level for setting the first and second weighting factors may be further provided.

  A correction coefficient for each gradation of the signal levels of the first and second video signals is calculated, and the first and second correction coefficients are calculated based on the difference amount and the correction coefficient obtained by the difference amount calculation means. It further comprises correction amount calculation means (for example, correction amount calculation circuits 155-1 and 155-2 in FIG. 8) for calculating the correction amount of the signal level of the video signal, and the correction means is calculated by the correction amount calculation means. The signal levels of the first and second video signals can be corrected based on the correction amounts of the signal levels of the first and second video signals.

  The storage unit (for example, the register 154 in FIG. 8) for storing the correction coefficient of the predetermined gradation of the signal level is further provided, and the correction amount calculation unit is a correction coefficient of the predetermined gradation stored in the storage unit Based on the above, it is possible to calculate a correction coefficient for each gradation of the signal levels of the first and second video signals.

  A signal processing method according to one aspect of the present invention is a signal processing method of a signal processing circuit that processes a video signal output to a display device driven by a dot line inversion driving method, and a signal of a first video signal that passes through a line memory. A first weighting coefficient corresponding to the level is set, and the sum of the first weighting coefficients is calculated (for example, step S31 in FIG. 13), and the signal level of the second video signal that does not pass through the line memory is set. A corresponding second weighting factor is set, the sum of the second weighting factors is calculated (for example, step S32 in FIG. 13), and the difference amount of the calculated sum of the first and second weighting factors is calculated. (For example, step S33 in FIG. 13), and based on the obtained difference amount, the signal levels of the first and second video signals are corrected (for example, step S36 in FIG. 13).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 is a block diagram showing a configuration example of a liquid crystal display system to which the present invention is applied.

  In the example of FIG. 3, the liquid crystal display system includes a scan converter 51, a digital signal driver (DSD) IC (Integrated Circuit) 52, an S / H (Sample / Hold) driver 53, an LCD (Liquid Crystal Display) panel. 54, a microcomputer 55, and an operation unit 56, and performs signal processing of video signals to be displayed on the LCD panel 54.

  An analog video signal is serially input to the scan converter 51 from outside (not shown) (for example, a personal computer). The scan converter 51 incorporates an A / D (Analog / Digital) conversion circuit (not shown), and performs A / D conversion, pixel number conversion, line number conversion, frequency conversion, and the like under the control of the microcomputer 55. The converted video signal, vertical synchronizing signal, horizontal synchronizing signal, and master clock are output.

  For example, the scan converter 51 converts an analog video signal into a digital video signal having the number of pixels, the number of lines, and the frequency according to the LCD panel 54, and converts the converted digital video signal into a digital signal in a serial or parallel manner. Output to the driver IC 52. In the example of FIG. 3, the video signal from the scan converter 51 is input to the digital signal driver IC 52 in parallel from the input port 1 and the input port 2.

  The digital signal driver IC 52 includes a double speed drive circuit 61, a signal correction circuit 62, a dot line inversion circuit 63, a tail correction circuit 64, and a timing generator 65, and is parallel to the video signals of the input ports 1 and 2. Then, the video signal processing for the LCD panel 54 is performed, and the processed video signal is output from the output ports 1 and 2 to the S / H driver 53, and various timing pulses are generated.

  Hereinafter, a line passing through the input port 1 and the output port 1 is also referred to as an odd line, and a line passing through the input port 2 and the output port 2 is also referred to as an even line.

  The double speed drive circuit 61 includes a field memory (not shown). When the input from the scan converter 51 is serial, the double speed drive circuit 61 writes data for one field within one vertical period based on the timing pulse from the timing generator 65 under the control of the microcomputer 55. In addition, the process for obtaining double-speed data is performed by reading data for one field twice in one vertical period from the field memory. In the case of the example in FIG. 3, the double-speed drive circuit 61 outputs the two parallel signals to the signal correction circuit 62 as they are in two parallels without performing the double-speed processing because the input from the scan converter 51 is parallel.

  When two digital signal driver ICs 52 are configured, the signal of the input port 1 is selected by one digital signal driver IC 52, the double speed processing is performed, and the input port 2 of the other digital signal driver IC 52 is processed. A signal is selected and double speed processing is performed.

  The signal correction circuit 62 performs gamma correction on the video signal from the double speed drive circuit 61 based on the timing pulse from the timing generator 65 under the control of the microcomputer 55, and further applies to the LCD panel 54. Performs color unevenness correction for displayed colors.

  The dot line inversion circuit 63 uses the line memory 104 shown in FIG. 4 on the basis of the timing pulse from the timing generator 65 under the control of the microcomputer 55, to either the odd line or the even line. Causes the previous line of data to be output, and the other of the odd line or even line to output the data of the current line.

  FIG. 4 shows a configuration example of the dot line inversion circuit 63. In the example of FIG. 4, the dot line inversion circuit 63 includes a dot shift selector 101, a left / right inversion selector 102, an up / down inversion preselector 103, a line memory 104, and an up / down inversion post selector 105, and a horizontal position from the microcomputer 55. Based on the setting signal HP, the left / right inversion signal RGT, and the up / down inversion signal DWN, one of the odd line and even line signals is delayed.

  The dot shift selector 101 receives the odd line video signal and the even line video signal from the signal correction circuit 62 from the input ports 1 and 2, respectively. When the horizontal position setting HP of the display on the LCD panel 54 is shifted by 1, the dot shift selector 101 switches the positions of the odd line and even line data displayed on the LCD panel 54. Therefore, the horizontal position setting signal from the microcomputer 55 is displayed. Based on HP, the port passing through the line memory 104 is switched.

  That is, the dot shift selector 101 outputs 0 or 1 as indicated by the horizontal position setting signal HP and outputs the signals of the input ports 1 and 2 as they are to the odd and even lines, respectively, as the port replacement selection process. 2 and 2 are exchanged, and processing for outputting to the even and odd lines is performed.

  The left / right inversion selector 102 performs the left / right inversion of the display on the LCD panel 54, so that the positions of the odd line and even line data displayed on the LCD panel 54 are switched. Similarly to the dot shift selector 101, the ports passing through the line memory 104 are switched.

  When the vertical inversion preselector 103 inverts the display on the LCD panel 54, the data positions of the odd lines and the even lines do not change, but the ports through the line memory 104 must be switched. The ports passing through the line memory 104 are switched based on the upside down signal DWN. That is, the up / down inversion pre-selector 103 outputs one of the odd lines and even lines to the line memory 104, and outputs the other of the odd lines and even lines to the up / down inversion post selector 105. To do.

  The line memory 104 delays the input video signal by one line. The video signal delayed by one line by the line memory 104 is input to the upside down post selector 105.

  The vertical inversion post selector 105 returns the port exchanged by the vertical inversion preselector 103 based on the vertical inversion signal DWN from the microcomputer 55. For example, when the up / down inversion preselector 103 outputs an odd line video signal to the line memory 104, the up / down inversion post selector 105 outputs the video signal from the line memory 104 from the output port 1, and the up / down inversion preselector 103. From the output port 2.

  When the up / down inversion preselector 103 outputs the video signal of even lines to the line memory 104, the up / down inversion post selector 105 outputs the video signal from the line memory 104 from the output port 2, and the up / down inversion preselector 103. From the output port 1.

  Returning to FIG. 3, the tail correction circuit 64 is controlled by the microcomputer 55 and based on the timing pulse from the timing generator 65, the odd-line and even-line video signal signals from the dot line inversion circuit 63. A weighting factor is set for each level, and a pixel position where tailing occurs is detected by calculating the difference between the sum of the weighting factors of the odd lines and the sum of the weighting factors of the even lines.

  The tail correction circuit 64 corrects the tail based on the detected pixel position. The odd line and even line video signals with corrected tailing are output from the output ports 1 and 2 to the S / H driver 53, respectively.

  The timing generator 65 is supplied with a master clock, a vertical synchronizing signal, and a horizontal synchronizing signal from the scan converter 51. The timing generator 65 generates various timing pulses based on the master clock, the vertical synchronization signal, and the horizontal synchronization signal, and performs all timing control of the liquid crystal display system.

  The odd line video signal from the output port 1 of the digital signal driver IC 52 and the even line video signal from the output port 2 of the digital signal driver IC 52 are input to the S / H driver 53. The S / H driver 53 converts the odd-numbered and even-numbered digital video signals into analog video signals based on the timing pulse from the timing generator 65 under the control of the microcomputer 55.

  Then, the S / H driver 53 converts the odd-numbered analog video signal into a plurality of pixels as either a negative polarity (hereinafter also referred to as L level) or a positive polarity (hereinafter also referred to as H level) video signal. Each is input to the LCD panel 54, and an analog video signal of even lines is input to the LCD panel 54 as a video signal of the other of the L level and the H level. For example, when the LCD panel 54 is a 12-pixel simultaneous writing type liquid crystal panel in which 12 pixels are written in parallel, the video signals of both lines are input to the LCD panel 54 by 6 pixels.

  The LCD panel 54 is a liquid crystal panel driven by a dot line inversion driving method, and is a transparent insulating substrate on which a pixel array unit in which pixels including liquid crystal cells as electro-optical elements are two-dimensionally arranged in a matrix is formed, For example, a first glass substrate and a second glass substrate are arranged to face each other with a predetermined gap, and a liquid crystal material is sealed in the gap. The LCD panel 54 is, for example, a 12-pixel simultaneous writing type liquid crystal panel that writes 12 pixels in parallel. Based on the drive timing pulse from the timing generator 65, the image signal from the S / H driver 53 is simultaneously received by 12 pixels. By writing to each pixel of the LCD panel 54, an image corresponding to the image signal is displayed.

  Note that in the case of a 24-pixel simultaneous writing type liquid crystal panel that writes 24 pixels in parallel, a video signal of 24 pixels is input from the S / H driver 53, so that the video signal from the S / H driver 53 is 24 pixels. At the same time, each pixel is written.

  The microcomputer 55 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like, and executes user instructions and various programs from the operation unit 56. Thus, the processing of each part of the liquid crystal display system is controlled. For example, the microcomputer 55 performs various settings of the liquid crystal display system based on user instructions from the operation unit 56, and sends instructions corresponding to the various settings to the scan converter 51, the digital signal driver IC 52, and the S / H driver. The processing of the scan converter 51, the digital signal driver IC 52, and the S / H driver 53 is controlled by writing to a register (not shown) incorporated in the 53.

  The operation unit 56 includes buttons and dials, and outputs an instruction signal based on a user operation to the microcomputer 55. For example, in response to a user operation, the operation unit 56 outputs an instruction signal related to correction of color unevenness, an instruction signal related to upside down or left and right inversion, and the like to the microcomputer 55.

  FIG. 5 shows a configuration example of the LCD panel 54. In the example of FIG. 5, the horizontal direction indicates the H (Horizontal) system of the panel, and the vertical direction indicates the V (Vertical) system of the panel, and the H data lines (Data_Line) 1 to 9 and the V system The pixel transistors wired to the gate lines (Gate_Line) 1 to 4 are shown. Hereinafter, the pixel transistor is simply referred to as a pixel.

  In the LCD panel 54, a data line (also referred to as a signal line) is wired for each column with respect to the matrix-like pixel arrangement, but the gate line is not connected to each row but to the next row every other pixel. The connection is such that it goes back and forth between two rows of pixels, meandering across two rows of pixels.

  For example, when attention is paid to the gate line 1, the gate line 1 is a pixel in the first row (first stage) from the top of the data line 1, a pixel in the second row from the top of the data line 2, and a pixel from the top of the data line 3. The pixels in the row are connected so as to connect the pixels in the second row from the top of the data line 4. Similarly, paying attention to the gate line 2, the gate line 2 includes the pixel in the second row from the top of the data line 1, the pixel in the third row from the top of the data line 2, and the pixel in the second row from the top of the data line 3. Are connected so as to connect the pixels in the third row from the top of the data line 4.

  When attention is paid to the gate line 3, the gate line 3 includes the pixel on the third row from the top of the data line 1, the pixel on the fourth row from the top of the data line 2, the pixel on the third row from the top of the data line 3, It is connected so as to connect the pixels in the fourth row from the top of the data line 4. Similarly, paying attention to the gate line 4, the gate line 4 includes the pixel on the fourth row from the top of the data line 1, the pixel on the fifth row from the top of the data line 2, and the pixel on the fourth row from the top of the data line 3. Are connected so as to connect the pixels in the fifth row from the top of the data line 4.

  On the other hand, the video signal to each data line includes signals input to data lines 1, 3, 5, 7, 9 (hereinafter collectively referred to as data odd lines), and data lines 2, 4 , 6 and 8 (hereinafter collectively referred to as data even lines) are opposite in polarity (H level or L level) with respect to the counter potential (VCOM). The odd lines and the even data lines are input simultaneously. The video signal to each data line is input with the polarity reversed every 1H (H: horizontal scanning period) (that is, every gate line).

  In the case of the example of FIG. 6, in the gate line 1, an odd line video signal from the output port 1 is input as an H level to the data odd line by the S / H driver 53. The video signal of the even line is input as the L level to the data even line. On the other hand, in the gate line 2, the odd line video signal from the output port 1 is input to the data odd line as the L level by the S / H driver 53, and the even line video signal from the output port 2. Is input as an H level to the even data line. Since the gate line 3 is the same as that of the gate line 1 and the gate line 4 is the same as that of the gate line 2, the description thereof is omitted because it is repeated.

  As described above, as shown in FIG. 6, an H level video signal is written to the pixels of the data odd lines in the gate lines 1 and 3, and simultaneously with the writing of the data odd lines, An L level video signal is written. Further, an L level video signal is written to the pixels of the data odd lines in the gate lines 2 and 4, and an H level video signal is written to the pixels of the data even lines simultaneously with the writing of the data odd lines.

  In the example of FIG. 6, an example of the LCD panel 54 when a black window is displayed on a gray background is shown. In the LCD panel 54, the direction from left to right represents the scanning direction, the hatched pixels represent the pixels in the gray background portion, and the black pixels represent the pixels in the black window portion. That is, the signal levels of the second to fourth pixels from the top of the data lines 3 to 6 are black levels, and the signal levels of the other pixels are gray levels.

  As described above, in the dot line inversion driving method, the potential variation due to capacitive coupling is kept to a minimum by simultaneously writing reverse polarities to the pixel transistors. In addition, 1H (the reverse polarity is written simultaneously for each period to cancel the fluctuation of VCOM and the gate line. However, conventionally, when a black window is displayed on a gray background, Since writing to the pixels connected to the same gate line is unbalanced, fluctuations in the VCOM and the gate line are not canceled out, and tailing occurs as shown in FIG.

  FIG. 7 shows an example of a conventional LCD panel when a black window with a gray background is displayed.

  In the conventional LCD panel, as in the LCD panel 54 of FIG. 6, the black pixels in the second to fourth stages from the top of the data lines 3 to 6 are pixels constituting the black window portion. Among the pixels constituting the gray background in the LCD panel 54, tailing occurs in the upper and lower ends of the black window and several pixels generated behind the scanning of the black window. As a result, the tailing pixel with the letter a is whiter than the gray to be displayed, as shown in white, and the tailing with the letter b is occurring. The pixel is darker than the gray to be displayed, as represented by the hatching that is finer than the hatch that represents the gray background.

  Specifically, in the example of FIG. 7, the pixels of the data lines 3, 5, and 7 in the gate line 1 and the pixels of the data lines 4, 6, and 8 in the gate line 4 become whitish due to the occurrence of tailing. Thus, the pixel of the data line 8 in the gate line 1 and the pixel of the data line 7 in the gate line 4 are darkened due to the occurrence of tailing.

  Hereinafter, tailing correction for correcting tailing that occurs at the upper and lower ends of these black windows and tailing that occurs behind the scanning of the black window will be described. FIG. 8 shows a configuration example of the tailing correction circuit 64 of FIG.

  In the example of FIG. 8, the tail correction circuit 64 includes a register 151, comparison / weighting coefficient calculation circuits 152-1 and 152-2, a difference amount calculation circuit 153, a register 154, and correction amount calculation circuits 155-1 and 155-. 2 and stage number adjustment circuits 156-1 and 156-2, and addition / subtraction circuits 157-1 and 157-2.

  The odd-line video signal (hereinafter also referred to as ODD data) from the dot line inversion circuit 63 is input to the comparison / weighting coefficient calculation circuit 152-1 and the stage number adjustment circuit 156-1. The even line video signal (hereinafter also referred to as EVEN data) from the dot line inversion circuit 63 is input to the comparison / weighting coefficient calculation circuit 152-2 and the stage number adjustment circuit 156-2.

 The register 151 stores n (n ≧ 2) threshold settings for the signal level of the video signal from the dot line inversion circuit 63.

  The comparison / weighting factor calculation circuit 152-1 sets the weighting factor based on the threshold setting of the register 151 with respect to the signal level of the odd-numbered video signal from the dot line inversion circuit 63, and sets the weighting factor of the ODD data. Calculate the sum ODD_CNT. The comparison / weighting coefficient calculation circuit 152-2 sets the weighting coefficient based on the threshold setting of the register 151 for the signal level of the video signal of the even line from the dot line inversion circuit 63, and sets the weighting coefficient of the EVEN data. Calculate the sum EVEN_CNT.

  The difference amount calculation circuit 153 uses the sum ODD_CNT of the weighting coefficients from the comparison / weighting coefficient calculation circuit 152-1 and the sum EVEN_CNT of the weighting coefficients from the comparison / weighting coefficient calculation circuit 152-2 to calculate the respective weighting coefficients. Sum difference ODD_CNT1 and EVEN_CNT1 are calculated. Differences ODD_CNT1 and EVEN_CNT1 of the sum of the weighting coefficients are expressed by the following equations (1) and (2), respectively.

ODD_CNT1 = ODD_CNT EVEN_CNT (1)
EVEN_CNT1 = EVEN_CNT ODD_CNT (2)

  As will be described later with reference to FIGS. 9 and 10, the pixel position where tailing occurs (that is, the position of the correction pixel for which tailing is to be corrected) can be detected based on the differences ODD_CNT1 and EVEN_CNT1 of the sum of these weighting factors. become.

  The register 154 stores m (for example, three) correction coefficients set to arbitrary gradations at the signal level of the video signal.

  Based on the correction coefficient stored in the register 154, the correction amount calculation circuits 155-1 and 155-2 linearly interpolate the correction coefficient for gradations other than the gradation for which the correction coefficient is set. Thus, correction coefficients for all gradations of 0% to 100% of the video signal are calculated.

  Then, the correction amount calculation circuit 155-1 corrects the correction amount for the correction pixel in the video signal from the stage number adjustment circuit 156-1 based on the difference ODD_CNT1 of the sum of the calculated correction coefficient and the weight coefficient from the difference amount calculation circuit 153. Is calculated. Based on the calculated correction coefficient and the difference EVEN_CNT1 of the sum of the weighting coefficients from the difference amount calculation circuit 153, the correction amount calculation circuit 155-2 calculates the correction amount for the correction pixel in the video signal from the stage number adjustment circuit 156-2. calculate.

  The correction amount of the correction pixel calculated by the correction amount calculation circuit 155-1 is output to the addition / subtraction circuit 157-1, and the correction amount of the correction pixel calculated by the correction amount calculation circuit 155-2 is the addition / subtraction circuit 157-2. Is output.

  The stage number adjustment circuit 156-1 is a dot line inversion circuit for matching the pixel position with the video signal of the processing line passing through the comparison / weighting coefficient calculation circuit 152-1, the difference amount calculation circuit 153, and the correction amount calculation circuit 155-1. The odd-numbered video signal from 63 is delayed to adjust the number of stages. The video signal from the stage number adjustment circuit 156-1 is output to the correction amount calculation circuit 155-1 and the addition / subtraction circuit 157-1.

  The stage number adjustment circuit 156-2 is a dot line inversion circuit for aligning the pixel position with the video signal of the processing line passing through the comparison / weight coefficient calculation circuit 152-2, the difference amount calculation circuit 153, and the correction amount calculation circuit 155-2. The even line video signal from 63 is delayed to adjust the number of stages. The video signal from the stage number adjustment circuit 156-2 is output to the correction amount calculation circuit 155-2 and the addition / subtraction circuit 157-2.

  The addition / subtraction circuit 157-1 corrects the trailing by adding / subtracting the correction amount of the correction pixel calculated by the correction amount calculation circuit 155-1 to / from the video signal from the stage number adjustment circuit 156-1. The video signal of the odd line whose tailing is corrected is output from the output port 1 to the S / H driver 53.

  The addition / subtraction circuit 157-2 corrects the trailing by adding / subtracting the correction amount of the correction pixel calculated by the correction amount calculation circuit 155-2 to / from the video signal from the stage number adjustment circuit 156-2. The even-line video signal whose tailing is corrected is output from the output port 2 to the S / H driver 53.

  Hereinafter, comparison / weighting coefficient calculation circuits 152-1 and 152-2, correction amount calculation circuits 155-1 and 155-2, stage number adjustment circuits 156-1 and 156-2, and addition / subtraction circuits 157-1 and 157 -2 is simply referred to as a comparison / weighting coefficient calculation circuit 152, a correction amount calculation circuit 155, a stage number adjustment circuit 156, and an addition / subtraction circuit 157.

  FIG. 9 is a diagram illustrating the sum of the weighting coefficients calculated by the tail correction circuit 64 of FIG. 8 and the difference between the sums of the weighting coefficients. In the example of FIG. 9, in the LCD panel 54 of FIG. 6 described above, based on the threshold setting of the register 151, the signal level weighting factor of the pixel that is the black window portion is set to 2, and the pixel signal that is the gray portion of the background When the level weighting factor is 0, the sum of weighting factors ODD_CNT for odd data lines, the sum of weighting factors EVEN_CNT for even data lines, and ODD_CNT1 and EVEN_CNT1 that take the difference of the sums of the respective weighting factors It is shown.

  The left side of FIG. 9 shows the weight coefficient sum ODD_CNT and the difference ODD_CNT1 for each data odd line (data lines 1, 3, 5, and 7) for each gate line, and the right side shows the data even line ( The sum of the weighting factors EVEN_CNT and the difference EVEN_CNT1 for the data lines 2, 4, 6, 8) are shown for each gate line.

  For odd data lines, for each gate line, the first frame represents the sum of the weighting factors from data line 1 to data line 1, and the second frame represents data line 1 to data line 3 The third frame shows the sum of the weighting factors from data line 1 to data line 5, and the fourth frame shows the sum of the weighting factors from data line 1 to data line 7. The sum of the weighting factors is shown.

  That is, since the pixels of the data lines 1, 3, 5, and 7 in the gate line 1 are the background gray portions, the weight coefficients are all 0. Therefore, in the gate line 1, as shown in the first row from the upper left, the weight coefficient sum ODD_CNT-1 up to the data line 1 becomes "0", and the weight coefficient sum ODD_CNT- up to the data line 3 is displayed. 1 becomes “0”, the weight coefficient sum ODD_CNT-1 up to the data line 5 becomes “0”, and the weight coefficient sum ODD_CNT-1 up to the data line 7 becomes “0”.

  Since the pixels of the data lines 1 and 7 in the gate line 2 are the gray part of the background, the weight coefficient is 0, and the pixels of the data lines 3 and 5 are the black window part, so the weight coefficient is 2. Therefore, in the gate line 2, as shown in the second row from the upper left, the weight coefficient sum ODD_CNT-2 up to the data line 1 becomes "0", and the weight coefficient sum ODD_CNT- up to the data line 3 is displayed. 2 becomes “2”, the sum ODD_CNT-2 of the weight coefficients up to the data line 5 becomes “4”, and the sum ODD_CNT-2 of the weight coefficients up to the data line 7 becomes “4”.

  Since the pixels of the data lines 1 and 7 in the gate line 3 are the gray portion of the background, the weighting factor is 0, and the pixels of the data lines 3 and 5 are the black window portion, so the weighting factor is 2. Therefore, in the gate line 3, as shown in the third row from the upper left, the weight coefficient sum ODD_CNT-3 up to the data line 1 becomes "0", and the weight coefficient sum ODD_CNT- up to the data line 3 is displayed. 3 becomes “2”, the sum ODD_CNT-3 of the weight coefficients up to the data line 5 becomes “4”, and the sum ODD_CNT-3 of the weight coefficients up to the data line 7 becomes “4”.

  Since the pixels of the data lines 1 and 7 in the gate line 4 are the gray portion of the background, the weighting factor is 0, and the pixels of the data lines 3 and 5 are the black window portion, so the weighting factor is 2. Therefore, in the gate line 4, the weight coefficient sum ODD_CNT-4 up to the data line 1 becomes “0” as shown in the fourth row from the upper left side, and the weight coefficient sum ODD_CNT− up to the data line 3 becomes “0”. 4 becomes “2”, the sum ODD_CNT-4 of the weight coefficients up to the data line 5 becomes “4”, and the sum ODD_CNT-4 of the weight coefficients up to the data line 7 becomes “4”.

  For even data lines, for each gate line, the first frame shows the sum of the weighting factors from data line 2 to data line 2, and the second frame is from data line 2 to data line 4. The third frame shows the sum of the weighting factors from the data line 2 to the data line 6, and the fourth frame shows the sum of the weighting factors from the data line 2 to the data line 8. The sum of the weighting factors is shown.

  That is, since the pixels of the data lines 2 and 8 in the gate line 1 are the gray portion of the background, the weighting factor is 0, and the pixels of the data lines 4 and 6 are the black window portion, so the weighting factor is 2. . Therefore, in the gate line 1, as shown in the first row from the upper right side, the weight coefficient sum EVEN_CNT-1 up to the data line 2 is “0”, and the weight coefficient sum EVEN_CNT− up to the data line 4 is “0”. 1 becomes “2”, the sum EVEN_CNT-1 of the weight coefficients up to the data line 6 becomes “4”, and the sum EVEN_CNT-1 of the weight coefficients up to the data line 8 becomes “4”.

  Since the pixels of the data lines 2 and 8 in the gate line 2 are the gray part of the background, the weight coefficient is 0, and the pixels of the data lines 4 and 6 are the black window part, so the weight coefficient is 2. Therefore, in the gate line 2, as shown in the second row from the upper right side, the weight coefficient sum EVEN_CNT-2 up to the data line 2 is "0", and the weight coefficient sum EVEN_CNT- up to the data line 4 is displayed. 2 becomes “2”, the sum EVEN_CNT-2 of the weight coefficients up to the data line 6 becomes “4”, and the sum EVEN_CNT-2 of the weight coefficients up to the data line 8 becomes “4”.

  Since the pixels of the data lines 2 and 8 in the gate line 3 are the gray portion of the background, the weighting factor is 0, and the pixels of the data lines 4 and 6 are the black window portion, so the weighting factor is 2. Accordingly, in the gate line 3, as shown in the third row from the upper right side, the sum EVEN_CNT-3 of the weight coefficients up to the data line 2 becomes “0”, and the sum of the weight coefficients up to the data line 4 EVEN_CNT− 3 becomes “2”, the sum EVEN_CNT-3 of the weight coefficients up to the data line 6 becomes “4”, and the sum EVEN_CNT-3 of the weight coefficients up to the data line 8 becomes “4”.

  Since the pixels of the data lines 2, 4, 6, and 8 in the gate line 4 are the gray portion of the background, the weighting coefficients are all 0. Therefore, in the gate line 4, as shown in the fourth row from the upper right side, the sum EVEN_CNT-4 of the weight coefficients up to the data line 1 becomes “0”, and the sum of the weight coefficients up to the data line 3 EVEN_CNT− 4 becomes “0”, the sum EVEN_CNT-4 of the weight coefficients up to the data line 5 becomes “0”, and the sum EVEN_CNT-4 of the weight coefficients up to the data line 7 becomes “0”.

  Then, the difference ODD_CNT1- * (*: represents an arbitrary number of the gate lines) of the sum of the weight coefficients in the odd-numbered data line is the sum of the weight coefficients ODD_CNT in the odd-numbered data line as shown in the above-described equation (1). -* Minus the sum of weighting factors EVEN_CNT- * in the even data lines.

  Therefore, in the gate line 1, as shown in the fifth row from the upper left, the difference ODD_CNT1-1 of the sum of the weight coefficients up to the data line 1 becomes “0”, and the sum of the weight coefficients up to the data line 3 Difference ODD_CNT1-1 is “−2”, the difference ODD_CNT1-1 of the sum of the weight coefficients up to the data line 5 is “−4”, and the difference ODD_CNT1-1 of the sum of the weight coefficients up to the data line 7 is “− 4 ".

  In the gate line 2, as shown in the sixth row from the upper left, the difference ODD_CNT1-2 of the sum of the weighting factors up to the data line 1 becomes “0”, and the difference of the sum of the weighting factors up to the data line 3 ODD_CNT1-2 becomes “0”, the difference ODD_CNT1-2 of the sum of the weight coefficients up to the data line 5 becomes “0”, and the difference ODD_CNT1-2 of the sum of the weight coefficients up to the data line 7 becomes “0”.

  In the gate line 3, the difference ODD_CNT1-3 in the sum of the weighting factors up to the data line 1 becomes “0” as shown in the seventh row from the upper left, and the difference in the sum of the weighting factors up to the data line 3 ODD_CNT1-3 becomes “0”, the difference ODD_CNT1-3 of the sum of the weight coefficients up to the data line 5 becomes “0”, and the difference ODD_CNT1-3 of the sum of the weight coefficients up to the data line 7 becomes “0”.

  In the gate line 4, the difference ODD_CNT1-4 in the sum of the weight coefficients up to the data line 1 becomes “0” as shown in the eighth row from the top on the left side, and the difference in the sum of the weight coefficients up to the data line 3 ODD_CNT1-4 becomes “2”, the difference ODD_CNT1-4 of the sum of the weight coefficients up to the data line 5 becomes “4”, and the difference ODD_CNT1-4 of the sum of the weight coefficients up to the data line 7 becomes “4”.

  On the other hand, the difference EVEN_CNT1- * (*: arbitrary number) of the sum of the weighting coefficients in the data even lines is calculated from the sum of the weighting coefficients EVEN_CNT- * in the data even lines as shown in the above equation (2). This is the sum of the weighting factors ODD_CNT- * for odd lines.

  Therefore, in the gate line 1, as shown in the fifth row from the upper right side, the difference EVEN_CNT1-1 of the weight coefficients up to the data line 1 is “0”, and the sum of the weight coefficients up to the data line 3 is “0”. The difference EVENCNT1-1 is “2”, the difference EVEN_CNT1-1 of the sum of the weight coefficients up to the data line 5 is “4”, and the difference EVEN_CNT1-1 of the sum of the weight coefficients up to the data line 7 is “4”. Become.

  In the gate line 2, as shown in the sixth row from the upper right side, the difference EVEN_CNT 1-2 of the weighting factors up to the data line 1 becomes “0”, and the difference of the sum of the weighting factors up to the data line 3 EVENCNT1-2 becomes “0”, the difference EVEN_CNT1-2 of the sum of the weight coefficients up to the data line 5 becomes “0”, and the difference EVEN_CNT1-2 of the sum of the weight coefficients up to the data line 7 becomes “0”.

  In the gate line 3, as shown in the seventh row from the upper right, the difference EVEN_CNT1-3 of the weighting factors up to the data line 1 becomes “0”, and the difference of the sum of the weighting factors up to the data line 3 EVENCNT1-3 becomes “0”, the difference EVEN_CNT1-3 of the sum of the weight coefficients up to the data line 5 becomes “0”, and the difference EVEN_CNT1-3 of the sum of the weight coefficients up to the data line 7 becomes “0”.

  In the gate line 4, the difference EVEN_CNT 1-4 of the weighting factors up to the data line 1 becomes “0” as shown in the eighth row from the upper right side, and the difference of the sum of the weighting factors up to the data line 3 EVENCNT1-4 becomes “−2”, the difference EVEN_CNT1-4 of the weight coefficient sum up to the data line 5 becomes “−4”, and the difference EVEN_CNT1-4 of the weight coefficient sum up to the data line 7 becomes “−4”. It becomes.

  FIG. 10 shows an example in which the differences ODD_CNT1 and EVEN_CNT1 of the sum of the weighting coefficients calculated as described above are assigned to each pixel of the LCD panel 54 in FIG.

  In the example of FIG. 10, the values of −2, 2, −4, 4, −4, and 4 are shown in the pixels of the data lines 3 to 8 in the gate line 1, respectively. The values of -2, -2, 4, -4, 4, -4 are shown for the pixels 3 to 8, respectively, and the value of 0 is shown for the other pixels.

  Here, the pixels of the data lines 3, 5, and 7 in the gate line 1 and the data lines 4, 6, and 8 in the gate line 4 in which the values of −2, −4, and −4 are shown in FIG. This is a pixel with the letter a, which becomes whitish. That is, it can be seen that the data lines 3, 5, and 7 in the gate line 1 and the data lines 4, 6, and 8 in the gate line 4 are pixels that require subtraction by correction to the signal level.

  Further, the pixels of the data lines 4, 6, and 8 in the gate line 1 and the data lines 3, 5, and 7 in the gate line 1 in which the values of 2, 4, and 4 are indicated become dark due to the occurrence of tailing in FIG. This is a pixel with the letter b. In the example of FIG. 7, the letter b is not attached, but actually the pixels constituting the black window (data lines 4 and 6 in the gate line 1 and data lines 3 and 5 in the gate line 4). Is also dark. That is, it can be seen that the pixels of the data lines 4, 6, and 8 in the gate line 1 and the data lines 3, 5, and 7 in the gate line 4 are pixels that require addition by correction to the signal level.

  As described above, since the signed weighting coefficient is set only for the pixel where the tailing occurs by the difference ODD_CNT1 and EVEN_CNT1 of the sum of the weighting coefficients, the correction pixel can be easily detected and the correction pixel It is also possible to clarify the setting of the adjustment for correction.

  FIG. 11 shows an example of correction coefficient values set by the correction amount calculation circuit 155. In the example of FIG. 11, the vertical axis represents the signal level (0% to 100%) of the video signal, and the horizontal axis represents the correction coefficient value (0 to 511).

  For example, in the register 154, correction is made to an arbitrary gradation of the signal level, and in the case of the example of FIG. 11, three gradations of a gradation of 25%, a gradation of 50%, and a gradation of 75%, respectively. Coefficient values DOT_COEF1 to DOT_COEF3 are set and stored. In this case, the correction coefficient value DOT_COEF1 that is the same as that of the 25% gradation is set for the gradation of 0%, and the correction coefficient value DOT_COEF3 that is the same as 75% is set for the gradation of 100%. Yes.

  Here, the correction amount calculation circuit 155 sets the correction coefficient values DOT_COEF1 to DOT_COEF3 stored in the register 154 as they are for the gradation of 25%, the gradation of 50%, and the gradation of 75% of the signal level. However, for other gradations, correction coefficients for all gradations of 0% to 100% of the signal level of the video signal are calculated and set by linear interpolation of the correction coefficients.

  For example, the correction coefficient value DOT_COEF1 is set as the interpolation coefficient of 0% to 25% gradation, and the value obtained by linear interpolation of the correction coefficient values DOT_COEF1 and DOT_COEF2 is set as the interpolation coefficient of 25% to 50% gradation. Then, linear interpolation of correction coefficient values DOT_COEF2 and DOT_COEF3 is set as an interpolation coefficient of 50% to 75% gradation, and correction coefficient value DOT_COEF3 is set as an interpolation coefficient of 75% to 100% gradation.

  The correction amount of the correction pixel is calculated based on these correction coefficient values and the differences ODD_CNT1 and EVEN_CNT1 of the sum of the weighting coefficients obtained by the difference calculation circuit 153, and the calculated correction amount is added to or subtracted from the video signal. Further, it is possible to correct the upper and lower ends of the black window with the gray background and the tailing generated behind the scanning of the black window.

  Next, with reference to the flowchart of FIG. 12, signal processing for displaying in the liquid crystal display system of FIG. 3 will be described. That is, the signal processing and display control processing of the liquid crystal display system of FIG. 3 will be described with reference to FIG.

  In step S11, the scan converter 51 performs A / D conversion, pixel number conversion, line number conversion, frequency conversion on an input signal (analog video signal) from a personal computer (not shown) according to the LCD panel 54. The converted video signal, vertical synchronizing signal, horizontal synchronizing signal, and master clock are output. In the case of the example in FIG. 3, the converted digital video signal is input in parallel to the digital signal driver IC 52 from the input port 1 and the input port 2.

  In step S12, the double speed drive circuit 61 performs double speed conversion according to the input. That is, when the input from the scan converter 51 is parallel, the double speed drive circuit 61 does not perform double speed processing, and outputs the two parallel signals as they are to the signal correction circuit 62 in two parallels. When the input from the scan converter 51 is serial, the digital video signal from the scan converter 51 is subjected to double speed conversion, and the double speed signal is output to the signal correction circuit 62 in two parallels.

  In step S13, the signal correction circuit 62 performs gamma correction on the video signal from the double speed drive circuit 61 based on the timing pulse from the timing generator 65 under the control of the microcomputer 55, and Color unevenness correction of the color displayed on the LCD panel 54 is performed.

  In step S <b> 14, the dot line inversion circuit 63 delays the video line based on the horizontal position setting signal HP, the left / right inversion signal RGT, and the up / down inversion signal DWN from the timing generator 65 under the control of the microcomputer 55. (Odd line or even line) is selected, and the video signal of the selected video line is delayed using the line memory 104. For example, when an odd line is selected, the dot line inversion circuit 63 outputs the data of the current line for the even line, and outputs the previous data for the odd line.

  In step S <b> 15, the tail correction circuit 64 executes tail correction of the video signal from the dot line inversion circuit 63. This tailing correction process will be described in detail later with reference to FIG. 12. However, the tailing correction process in step S15 causes the tailing generated at the upper and lower ends of the black window on the gray background and behind the scanning of the black window. Is corrected. Then, the video signals of the odd lines and the even lines whose tailing is corrected are output from the output ports 1 and 2 to the S / H driver 53, respectively.

  In step S <b> 16, the S / H driver 53 converts the odd line and even line video signals from the tail correction circuit 64 to analog, and inputs the analog video signals to the LCD panel 54. For example, when the LCD panel 54 of FIG. 3 is a 12-pixel simultaneous writing type liquid crystal panel in which 12 pixels are written in parallel, the S / H driver 53 converts an odd-line analog video signal as an H-level video signal, for example. Six pixels are input to the odd-numbered data lines of the LCD panel 54, and even-numbered analog video signals are input to the even-numbered data lines of the LCD panel 54 as the L-level video signals.

  When the input of the 1H line is finished, in the next 1H line, the analog video signal of the odd line is input to the LCD panel 54 every 6 pixels as the L level video signal, and the analog video of the even line is input. The signal is input to the LCD panel 54 in units of 6 pixels as an H level video signal. That is, the video signal to the data line is input to the LCD panel 54 with the polarity reversed every 1H. Further, in the case of 1F (field) / 1H inversion driving processing, in the next field, the odd-line analog video signal is set to the H level by 6 pixels, and the even-line analog video signal is set to the L level by 6 pixels. The polarity is inverted for each field and input to the LCD panel 54.

  In step S <b> 17, the LCD panel 54 receives 12 pixels of the odd line and even line video signals input from the S / H driver 53 simultaneously on the basis of the drive timing pulse from the timing generator 65. The video corresponding to the video signal is displayed.

  Next, the tail correction process in step S15 of FIG. 12 will be described with reference to the flowchart of FIG.

  The odd line video signals from the dot line inversion circuit 63 are input to the comparison / weighting coefficient calculation circuit 152-1 and the stage number adjustment circuit 156-1. The video signals of even lines from the dot line inversion circuit 63 are input to the comparison / weighting coefficient calculation circuit 152-2 and the stage number adjustment circuit 156-2. The odd-numbered and even-numbered video signals input to the stage number adjusting circuits 152-1 and 152-2 are adjusted in the number of stages, respectively, and the correction amount calculating circuits 155-1 and 155-2 and the addition / subtraction circuit 157- 1 and 157-2.

  In step S31, the comparison / weighting coefficient calculation circuit 152-1 calculates the weighting coefficient based on the threshold setting of the register 151 with respect to the signal level of each pixel of the odd-line video signal input from the dot line inversion circuit 63. Then, as described above with reference to FIG. 9, the sum ODD_CNT of the weight coefficients of the odd lines is calculated.

  In step S32, the comparison / weighting coefficient calculation circuit 152-2 calculates the weighting coefficient based on the threshold setting of the register 151 with respect to the signal level of each pixel of the even-line video signal input from the dot line inversion circuit 63. Then, as described above with reference to FIG. 9, the sum EVEN_CNT of the weight coefficients of the even lines is calculated. Note that the processing of these steps S31 and S32 is processing executed in parallel.

  In step S33, the difference amount calculation circuit 153 uses the weight coefficient sum ODD_CNT from the comparison / weighting coefficient calculation circuit 152-1 and the weighting coefficient sum EVEN_CNT from the comparison / weighting coefficient calculation circuit 152-2 to obtain an equation. A difference ODD_CNT1 of the sum of the weighting factors expressed by (1) and EVEN_CNT1 expressed by equation (2) are calculated.

  In step S34, the correction amount calculation circuits 155-1 and 155-2, based on the correction coefficients stored in the register 154 (three correction coefficients in the example of FIG. 11), all levels of the signal level of the video signal. The key correction coefficient is calculated.

  In step S35, the correction amount calculation circuits 155-1 and 155-2, based on the calculated correction coefficient and the differences ODD_CNT1 and EVEN_CNT1 of the sum of the weight coefficients from the difference amount calculation circuit 153, respectively, The correction amount for the correction pixels in the video signals from 1 and 156-2 is calculated.

  That is, as described above with reference to FIG. 10, the correction pixel can be detected by the differences ODD_CNT1 and EVEN_CNT1 of the sum of the weighting coefficients from the difference amount calculation circuit 153, and the correction for the correction pixel can be adjusted. Recognize. Therefore, the correction amount calculation circuits 155-1 and 155-2 calculate the correction pixel from the signal level of the correction pixel in the video signal from the stage number adjustment circuits 156-1 and 156-2, the correction level, and the calculated correction coefficient. The amount of correction is calculated.

  In step S36, the addition / subtraction circuits 157-1 and 157-2 apply the correction pixels calculated by the correction amount calculation circuits 155-1 and 155-2 to the video signals from the stage number adjustment circuits 156-1 and 156-2, respectively. Add or subtract the correction amount to correct the tailing.

  In this way, the odd-line video signal whose tail is corrected is output from the output port 1 to the S / H driver 53, and the even-line video signal whose tail is corrected is output from the output port 2 to the S / H driver 53. The output is output to the H driver 53, the tailing correction process ends, and the process returns to step S15 in FIG.

  As described above, in the liquid crystal display system of FIG. 1, the weighting coefficient is set based on the threshold setting of the register 151 for the signal level of the video signal of the odd and even lines, and the weighting coefficient of the odd and even lines is set. The sum of ODD_CNT and EVEN_CNT is calculated, and the difference ODD_CNT1 and EVEN_CNT1 of the sum of the respective weighting coefficients is calculated. The correct correction position and the degree of correction can be easily detected. That is, based on the difference ODD_CNT1 and EVEN_CNT1 of the sum of the weight coefficients of the odd and even lines, it is possible to easily correct the boundary portion such as the black window and the black line, and the trailing behind the boundary scan. .

  Further, based on the correction coefficient stored in the register 154, the correction coefficient for all the gradations of the video signal is calculated, and based on the correction coefficient as well as the difference ODD_CNT1 and EVEN_CNT1 of the sum of the odd and even line weighting coefficients. Thus, since the correction amount of the correction pixel is calculated, the tailing correction according to the gradation of the video signal can be easily performed.

  In the above description, the example in which the tailing correction process is performed using the LCD panel using the liquid crystal cell as the display element of the pixel has been described. However, the present invention is not limited to the LCD panel. The present invention can be applied to all display devices that employ a dot line inversion driving method, such as a display system that performs signal processing of a video signal to be displayed on a projector.

  In the present specification, the step of describing the program stored in the program recording medium is not limited to the processing performed in time series in the described order, but is not necessarily performed in time series. Or the process performed separately is also included.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a figure explaining the tailing in a dot line inversion drive system. It is a figure explaining the tailing in a dot line inversion drive system. It is a block diagram which shows the structural example of the liquid crystal display system to which this invention is applied. FIG. 4 is a block diagram illustrating a configuration example of a dot line inversion circuit in FIG. 3. It is a figure which shows the structural example of the LCD panel of FIG. FIG. 4 is a diagram schematically illustrating a configuration example of the LCD panel in FIG. 3. It is a figure explaining the tailing in the conventional LCD panel. FIG. 4 is a block diagram illustrating a configuration example of a tail correction circuit of FIG. 3. It is a figure explaining the difference of the sum of a weighting coefficient, and the sum of a weighting coefficient. FIG. 10 is a diagram illustrating a case where the difference of the sum of the weighting factors in FIG. 9 is assigned to each pixel of the LCD panel in FIG. 6. It is a figure which shows the example of a correction coefficient value. 2 is a flowchart for explaining signal processing and display control processing of the liquid crystal display system of FIG. 1. It is a flowchart explaining the tailing correction process of step S15 of FIG.

Explanation of symbols

  51 Scan Converter, 52 Digital Signal Driver IC, 53 S / H Driver, 54 LCD Panel, 55 Microcomputer, 63 Dot Line Inversion Circuit, 64 Trailing Correction Circuit, 65 Timing Generator, 104 Line Memory, 151 Register, 152-1 , 152-2 Comparison weight coefficient calculation circuit, 153 Difference amount calculation circuit, 154 Register, 155-1, 155-2 Correction amount calculation circuit, 156-1, 156-2 Stage number adjustment circuit, 157-1, 157-2 Addition / subtraction circuit

Claims (5)

In a signal processing circuit for processing a video signal output to a display device driven by a dot line inversion driving method,
First weighting factor calculating means for setting a first weighting factor corresponding to the signal level of the first video signal passing through the line memory and calculating the sum of the first weighting factors;
A second weighting factor calculating means for setting a second weighting factor according to the signal level of the second video signal not passing through the line memory and calculating the sum of the second weighting factors;
Difference amount calculating means for obtaining a difference amount of the sum of the first and second weighting coefficients calculated by the first and second weighting coefficient calculating means;
A signal processing circuit comprising: correction means for correcting signal levels of the first and second video signals based on the difference amount obtained by the difference amount calculation means. The signal processing circuit according to claim 1, further comprising storage means for storing a threshold value at the signal level for setting the first and second weighting factors. A correction coefficient for each gradation of the signal levels of the first and second video signals is calculated, and the first and second correction coefficients are calculated based on the difference amount and the correction coefficient obtained by the difference amount calculation means. A correction amount calculating means for calculating a correction amount of the signal level of the video signal,
The correction means corrects signal levels of the first and second video signals based on correction amounts of signal levels of the first and second video signals calculated by the correction amount calculation means. 2. The signal processing circuit according to 1. Storage means for storing a correction coefficient of a predetermined gradation of the signal level;
4. The correction amount calculating unit calculates a correction coefficient for each gradation of the signal levels of the first and second video signals based on a correction coefficient of a predetermined gradation stored in the storage unit. A signal processing circuit according to 1. In a signal processing method of a signal processing circuit for processing a video signal output to a display device driven by a dot line inversion driving method,
Setting a first weighting factor according to the signal level of the first video signal passing through the line memory, calculating the sum of the first weighting factor,
Setting a second weighting factor according to the signal level of the second video signal not passing through the line memory, and calculating the sum of the second weighting factor,
Obtaining a difference amount of the sum of the calculated first and second weighting factors;
A signal processing method comprising: correcting signal levels of the first and second video signals based on the obtained difference amount.

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