JPH04371994A - Multicolor liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide an inexpensive gradational liquid crystal display device capable of reducing the cost of a driving circuit as much as possible when a gradational display is realized. CONSTITUTION:This liquid crystal display device consists of a drain voltage generating circuit 34, a gate driver 7, a drain driver 28, and a liquid crystal panel 41 and an external drain voltage generating circuit 34 switches voltages corresponding to many gradations to generate a drain voltage controlling the transmissivity of liquid crystal; and a drain voltage selecting circuit 37 switches two ON and OFF level voltages to realize the gradational display without increasing the frequency of switching of the drain voltage selecting circuit 37 even if the number of gradations increases.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a liquid crystal display device.
In particular, the present invention relates to a liquid crystal driving transistor that can be used in multiple colors without increasing driver cost in an active matrix liquid crystal display device.

0002

2. Description of the Related Art Conventionally, in order to display multiple colors on an active matrix type liquid crystal display device using transistor elements, Hitachi LCD Driver LSI Data Book (90'.3
) of P. 650~P. LCD driver HD described in 664
There is a method using 66310T. In this method, all the voltages necessary for multicolor display are input to a liquid crystal driver, and the liquid crystal driver selects the voltages according to display data and applies them to the liquid crystal elements, thereby realizing multicolor display. However, when the number of multi-color displays increases, this method becomes difficult to use with a high voltage circuit (HD6631).
No consideration is given to the fact that the scale of the voltage selection circuit (25V at 0T) increases, which increases the driver cost.

The prior art will be explained in detail below with reference to FIGS. 2 to 7. The LCD driver HD66310T is capable of 8-level gradation display, but to simplify the explanation, we will use 4-level gradation display here, and the display resolution of the liquid crystal display is N pixels in the horizontal direction and M pixels in the vertical direction. This will be explained as a pixel (N and M are natural numbers of 1 or more).

FIG. 2 is a block diagram showing the configuration of a conventional liquid crystal display device, in which 1 is display data, 2 is a data clock, and 3 is a horizontal clock. One period of the horizontal clock 3 corresponds to one horizontal period, that is, N Display data 1 for pixels is sent in synchronization with data clock 2. In this embodiment, it is assumed that the display data 1 is 2 bits of gradation information and is sent as one pixel data. 200 is a data liquid crystal driver that receives display data 1 and outputs a voltage according to the data to a liquid crystal element. Reference numeral 201 denotes a display data latch circuit, which is initialized with the horizontal clock 3 and sequentially captures display data from the beginning with the data clock 2. 202-20
4 are outputs of the display data latch circuit 201, which are 2-bit first pixel data, second pixel data, and Nth pixel data, respectively. 205 is a horizontal latch circuit that latches the first pixel data 202, second pixel data 203, and Nth pixel data 204 with the horizontal clock 3 and holds them for one horizontal period;
06 to 208 are the latched data, which are 2-bit first pixel horizontal data, second pixel horizontal data, and N
This is pixel horizontal data. 209 is a decoding circuit, 21
0 to 212 are the outputs of the decoding circuit 209, and D0 to
There are 4-bit first pixel decode data, second pixel decode data, and Nth pixel decode data consisting of D3. The decoding circuit 209 decodes each input horizontal data, and according to the decoded value, D0 of each decoded data.
- Set one bit of the three bits of D3 to "high" and set the remaining three bits to "low". 213 is a gate voltage select circuit, 214 is a multi-level voltage of four levels of V0 to V3 voltage, and the gate voltage select circuit 213 is
One voltage from among the multi-level voltages is selected and outputted corresponding to each input decoded data. 215 to 217 are the outputs of the gate voltage selection circuit 213, which are the first pixel voltage, the second pixel voltage, and the Nth pixel voltage, respectively. Reference numeral 26 is a leading signal, which is a signal that becomes "high" at the beginning of one frame (one screen). Reference numeral 27 is a line clock which takes in the leading signal 26, instructs writing of the first line, and thereafter sequentially shifts the line to be instructed to write to the second line and then to the third line. A line driver 218 instructs a writing line for each pixel voltage output by the data liquid crystal driver 200. 29 is a line shift circuit, and 30 to 32 are outputs of the line shift circuit 29, which are a first line signal, a second line signal, and an Mth line signal, respectively. The line shift circuit 29 outputs "" of the leading signal 26.
The line clock 27 takes in "high" and makes the first line signal 30 "high," and the subsequent line clocks sequentially shift the "high" from the second line signal 31 to the M-th line signal 32. , the outputs of the line shift circuit 29 are all "low" except for one line signal which is "high". 219 is a gate voltage selection circuit, 223 is a gate on voltage, 224 is a gate off voltage, and the gate voltage The select circuit 219 selects and outputs the gate-on voltage for "high" and the gate-off voltage for "low" according to the "high" and "low" of each input line signal. 220 to 222 are The outputs of the gate voltage selection circuit 219 are the first gate line, the second gate line, and the M-th gate line, respectively. 225 is a liquid crystal panel with N pixels in the horizontal direction and M pixels in the vertical direction. is a diagram showing the pixel configuration of the liquid crystal panel 225. In the figure, 226 is an additional gate line that always maintains the same potential as the gate-off voltage 224, 227 is the M-1st line gate line, and 228 is the first line in each row. Line (hereinafter abbreviated as (m, n) for m line and n line) pixel TFT
, 229 is the (1, 1) pixel electrode, 230 is the (1, 1) pixel liquid crystal, 47 is the counter electrode VCOM, , 231 is the (1, 1)
) pixel additional capacitance, 232 is (1,N) pixel TFT, 23
3 is (1,N) pixel electrode, 234 is (1,N) pixel liquid crystal, 235 is (1,N) pixel additional capacitor, 236 is (M,1)
) Pixel TFT, 237 is (M, 1) pixel electrode, 238 is (M, 1) pixel liquid crystal, 239 is (M, 1) pixel additional capacitor, 240 is (M, N) pixel TFT, 241 is (M, N)
Pixel electrode, 242 (M, N) pixel liquid crystal, 243 (M
, N) is the pixel additional capacitance. FIG. 4 is an explanatory diagram of the operation of each gate line, and FIG. 5 is an explanatory diagram of the voltage-transmittance characteristic of the liquid crystal. FIG. 6 is a system diagram of the first pixel of the gate voltage select circuit 22. Reference numerals 244 to 247 are voltage switches, D3 switches to D0 switches, respectively, and decoded data D3 to D0 of the output of the pulse select circuit 18 are gated. V3 to V0 of the multi-level voltage 214 are connected to the drain line, and the voltage switch corresponding to the decoded data that is "high" among the decoded data D3 to D0 is turned on and connected to that switch. The voltage value is output as the first pixel voltage 215. FIG. 7 is a timing chart illustrating the display operation of the liquid crystal panel 225.

Before explaining the operation of the liquid crystal display device, the operation of the liquid crystal panel 225 will be explained using FIGS. 3 to 5. As shown in FIG. 3, the liquid crystal panel 225 has one pixel formed by a TFT.
, a pixel electrode, an additional capacitor, and a liquid crystal, for example (1, 1
) In the pixel, when the first line gate line 220 reaches the gate-on voltage (1, 1), the pixel TFT 228 turns on, and the output voltage of the first pixel voltage 215 is applied to the (1, 1) pixel electrode 229, and this voltage value (1, 1) pixel additional capacitor 231 provided between the additional gate line 226 and
Store in the (1, 1) pixel liquid crystal 230 provided between the VCOM 47 (hereinafter, this operation is referred to as writing)
. When the first gate line 220 reaches the gate-off voltage, the (1, 1) pixel TFT turns off, and the stored voltage is It is retained until the next write. (1, 1) The pixel additional capacitor 231 is provided to compensate for the fact that the liquid crystal capacitance alone is insufficient for this holding operation. The pixel additional capacitance is formed between the gate line of the previous line, but only for the first line, since the previous line does not exist, an additional gate line 226 is specially provided and formed between it. That is, when the first line gate line 220 reaches the gate-on voltage, the N pixel TFTs on the first line turn on, and each pixel receives the first pixel voltage 215.
Writing is performed using the ~Nth pixel voltage 217, and each liquid crystal has a difference voltage between the written voltage and VCOM 47, and each additional capacitance is the difference between the written voltage and the gate-off voltage, which is the voltage of the additional gate line 226. Stores voltage and holds it until the next write. As shown in FIG. 4, after the first line gate line 220 reaches the gate-on voltage, each gate line is connected to the second line gate line 221...M line gate line 2.
In order to shift the gate-on voltage state by one horizontal period in sequence with 22, the N pixels on each line are sequentially written when the gate line is at the gate-on voltage, and each liquid crystal is Each additional capacitor stores the voltage difference between the written voltage and the gate-off voltage, which is the voltage of the gate line of the previous line, and holds it until the next writing. The liquid crystal of each pixel has four levels of transmittance depending on the voltages V0 to V3 as shown in FIG. 5, and displays four gradations. As described above, writing is performed to all pixels in the N row and M line of the liquid crystal panel, and display is performed by repeating this process. Next, the operation of the conventional liquid crystal display device will be explained using FIGS. 2, 6, and 7. Display data latch circuit 20
1 is initialized at the rising edge of the horizontal clock 3, and then the display data 1 and the display data for one horizontal line are sequentially taken in by the data clock 2. The captured display data 1 includes first pixel display data 202, second pixel display data 203,...N
Display data latch circuit 2 as pixel display data 204
01, and the above output is taken into the horizontal latch circuit 205 at the next rising edge of the horizontal clock 3. Also, at this time, the display data latch circuit 201 is initialized again to prepare to capture the next line of display data. First pixel horizontal data 206, second pixel horizontal data 207, ... Nth pixel display data 208, which are the output of the horizontal latch circuit 205.
is applied to the decoding circuit 209, which decodes each 2-bit horizontal data and sets one bit of the decoded data D0 to D3 to "high" according to its value 0 to 3. The data decoded in this way are the first pixel decode data 210 and the second pixel decode data 21, respectively.
1, . . . is outputted from the decoding circuit 209 as decoded data 212 for the Nth pixel. Gate voltage selection circuit 2
13 outputs one voltage out of the multi-level voltages 214 as the first pixel voltage 215 for the first pixel, for example, according to the first pixel decode data 210 as shown in FIG. The same applies to other pixels, and one voltage from among the multi-level voltages 214 is selected based on the value of each decoded data and output as a pixel voltage. Therefore, the data liquid crystal driver 200 outputs a voltage according to the period of the horizontal clock 3, that is, one horizontal period of display data captured in one horizontal period, to the liquid crystal panel 225 as a pixel voltage, and at the same time outputs the next line of display data. By repeating this operation, pixel voltages corresponding to display data are sequentially output line by line. The line driver 218 captures the leading signal 26 using the line clock 27, sets the first line signal 30 output from the line shift circuit 29 to "high", and outputs the remaining line signals to "high".
In order to set the voltage to “low”, the gate voltage selection circuit 219 sets the first gate line 220 to the gate-on voltage 223,
The remaining gate lines are set to a gate-off voltage 224. The line driver 218 sequentially applies the gate-on voltage 224 to the second line gate signals 221, . . . , N according to the line clock 27.
It is shifted with the line gate signal 222. That is, as shown in FIG. 7, when the first line gate line 220 has a gate-on voltage, the data liquid crystal driver 200 has a pixel voltage corresponding to the display data of the first line, for example, the first pixel voltage 2.
15 outputs the V1 voltage, so the liquid crystal panel 225
The pixel voltage of the first line is written in the first line. Furthermore, when the second line gate line 221 is at the gate-on voltage 224, the data liquid crystal driver 200 outputs a pixel voltage according to the second line display data, for example, the first pixel voltage 215 is the V2 voltage. LCD panel 2
The pixel voltage of the second line is written to the second line of 25. Then, when the M-th line gate line 222 is at the gate-on voltage 224, the data liquid crystal driver 200
Since the pixel voltage corresponding to the display data of the line, for example, the first pixel voltage 215 outputs the V3 voltage, the pixel voltage of the M line is written to the M line of the liquid crystal panel 225. By repeating the above writing of pixel voltages to each line, each pixel of the liquid crystal panel 225 is
It becomes possible to write pixel voltages according to the desired gradation to display.

[0006]

[Problems to be Solved by the Invention] The above-mentioned conventional technology realizes multi-gradation display by providing switches with the number of voltages corresponding to the number of gradations desired to be displayed for one pixel, as shown in FIG. There is. However, in the case of a liquid crystal display device, this switch is required for one horizontal display pixel, that is, N pixels, and
Since this is a high voltage circuit, an increase in the number of switches per pixel results in an increase in cost. That is, the multi-gradation display using this method does not take into account the increase in liquid crystal driver cost for displaying eight or more gradations, which is realized by the HD66310. An object of the present invention is to provide a liquid crystal display device that does not increase cost even when displaying eight or more gradations.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention uses a gate driver that selects a gate pulse width based on gradation information of display data, and a drain driver that selects a gate pulse width according to the number of gradations for a selected line. The corresponding voltage was switched and supplied during one horizontal period. Further, the liquid crystal panel was configured such that the drain voltage of the TFT on each line was applied by the output of the drain driver, and the gate of the TFT on each column was driven by the gate driver.

[0008]

[Operation] In the liquid crystal display device according to the present invention, the falling edge of the gate pulse selected based on the gradation information of the display data output by the gate driver is applied to the next voltage after the drain driver supplies the gradation voltage desired to be displayed. This makes it possible to write the gradation voltage indicated by the gradation information to the pixels on the selected line by setting the value immediately before the change to . In addition, the voltage of the non-selected line is the voltage output by the gate driver (
Since the voltage is sufficiently higher than the gate-on voltage and gate-off voltage, the TFTs on the non-selected lines are not turned on and writing does not occur.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 8 to 19. In this embodiment, the display resolution of the liquid crystal panel is assumed to be N pixels in the horizontal direction and M pixels in the vertical direction (N and M are natural numbers of 1 or more), and the number of gradations displayed is four levels. In addition, the gradation level is gradation 1 from the brightest,
They are called gradation 2, gradation 3, and gradation 4. , FIG. 1 is a diagram showing the configuration of an embodiment of a liquid crystal display device to which the present invention is applied.
3, 26, 27, 29-32 are the same as the conventional example. 4
is a gate pulse clock that outputs four pulses in one horizontal period, 5 is a gate-on voltage, 6 is a gate-off voltage,
Reference numeral 7 denotes a gate driver which takes in one horizontal portion of display data 1 and outputs a gate pulse having a pulse width corresponding to the gradation information of the data. Reference numeral 8 denotes a display data latch circuit, which is initialized with the horizontal clock 3 and sequentially takes in display data 1 from the beginning with the data clock 2. 9 to 11 are outputs of the display data latch circuit 8, which are 2-bit first pixel data, second pixel data, and Nth pixel data, respectively. 12 is
A horizontal latch circuit that latches the first pixel data 9, second pixel data 10, ... Nth pixel data 11 with the horizontal clock 3 and holds it for one horizontal period, 13 to 15 are the latched data, each with 2 bits. These are the first pixel horizontal data, the second pixel horizontal data, and the Nth pixel horizontal data. 16 is a pulse generation circuit, 17 is the output of the pulse generation circuit 16 and is a gate pulse having four pulse clocks, and 18 is a pulse selection circuit that outputs horizontal data for each first pixel 13, horizontal data for the second pixel 14, . . . N pixels horizontally. One pulse of the four gate pulse clocks 17 is selected and output based on the 2-bit gradation information of the eye data 15. 19 to 21 are the outputs of the pulse selection circuit 18, which are the first pixel pulse, the second pixel pulse, and N
This is the pixel pulse. 22 is a gate voltage selection circuit that selects a gate-off voltage 6 for "low" of the first pixel pulse 19, the second pixel pulse 20, and the Nth pixel pulse 21.
Gate-on voltage 5 is selected and output for "high". 23 to 25 are the outputs of the gate voltage selection circuit 22, which are the first pixel gate pulse, the second pixel gate pulse, and the Nth pixel gate pulse. 28 is the liquid crystal 33 is a drain driver that instructs the scanning line to be in the selected state of the panel and supplies a selection voltage to the drain line of the selected line and a non-selection voltage to the unselected line.
34 is a drain voltage generation circuit that generates a drain voltage; 35 is a selected drain voltage; and 36 is a non-selected drain voltage. 37 is a drain voltage selection circuit, which selects the "high" level of the first line signal 30 to the M line signal 32.
, "low", select drain voltage 35 is selected for "high", and unselected drain voltage 36 is selected and output for "low". 38 to 40 are the outputs of the drain voltage selection circuit 37, which are the first drain line, the second drain line, and the Mth drain line. 41 is a liquid crystal panel with N pixels in the horizontal direction and M pixels in the vertical direction. Figure 8 shows
It is a diagram showing a pixel configuration of a liquid crystal panel 41, in which 42
is an additional drain line that always maintains the same voltage level as the non-selected drain voltage 36, and 43 is an M-first line drain line. 44 is a pixel TFT in the first row and first line (hereinafter, the mth row and nth line is abbreviated as (m, n)), 45 is a (1,1) pixel additional capacitor, 46 is a (1,1) pixel liquid crystal, and 500 is ( 1,
1) Pixel electrode, 47 is counter electrode VCOM, 48 is (1,
N) Pixel TFT, 49 is (1, N) pixel additional capacitor, 50
is (1,N) pixel liquid crystal, 501 is (1,N) pixel electrode,
51 is (M, 1) pixel TFT, 52 is (M, 1) pixel additional capacitor, 53 is (M, 1) pixel liquid crystal, 502 is (M, 1)
) pixel electrode, 54 is (M,N) pixel TFT, 55 is (M
, N) pixel additional capacitance, 56 is (M, N) pixel liquid crystal, 50
3 is a (M,N) pixel electrode. 9 and 10 show the selected drain voltage 35 which is the output of the drain voltage generation circuit 34.
FIG. 9 shows the output voltage of the selected drain voltage 35 when VCOM47 is at the potential of V0, and FIG. 10 shows the output voltage of the selected drain voltage 35 when the VCOM47 is at the potential of V6. be. FIG. 11 is a diagram explaining the output waveform of the gate pulse of each pixel which is the output of the gate voltage select circuit 22. In the figure, T indicates one horizontal period, V5 is the voltage of the gate-on voltage 5, and V0 is the voltage of the gate-on voltage 5. This is the gate-off voltage 6. Further, the pulses (a) to (d) are gate pulse waveforms corresponding to four levels of gradation 1 to gradation 4 of gradation information of display data, respectively. FIG. 12 is an explanatory diagram of writing to one pixel of the liquid crystal. Figure 1
3 is a system diagram showing the configuration of one embodiment of the pulse generation circuit 16, and 58 to 61 are flip-flop circuits (hereinafter referred to as
F. F. ), 57, 63-66 are inverter circuits, 67-70 are the four gate pulses 17, V1 pulse, V2 pulse, V3 pulse, respectively.
This is a V4 pulse. Figure 14 shows the pulse generation circuit 1 in Figure 13.
FIG. 6 is an explanatory diagram of the operation of No. 6; FIG. 16 is a system diagram of an embodiment for generating the selected drain voltage 35 of the drain voltage generation circuit 34. In the figure, Va to Vd are voltage levels corresponding to four-level display, and 71 is the output of the four-level voltage. Voltage gate generation circuits 72 to 75 control the timing, which are the outputs of the voltage gate generation circuit 71 and have voltage levels Va to Vd, respectively.
76 to 79 are voltage switches, G4 to G1 are connected to the gate lines, and voltages Vd to Va are connected to the drain lines, so that the gate lines become "high" and the switches are switched on. is turned on, and the voltage level connected to that switch is output as the selected drain voltage 35. FIG. 17 is a diagram showing an embodiment of the voltage gate generation circuit 71 of FIG. 16, and 82 to 85 are F. F. , 8
0, 86-89 are inverter circuits. FIG. 18 is an explanatory diagram of the operation of the drain voltage generation circuit 34. FIG. 19 is an explanatory diagram of an AC circuit when driving a liquid crystal with AC, in which 90 is an AC signal that switches between "high" and "low" for each frame, 91 is an inverter circuit, 9
2 and 93 are voltage switches, the output of which is Va.

Before explaining the operation of the liquid crystal display device shown in FIG. 1, the operation of the liquid crystal panel 41 will be explained using FIGS. 8 to 12. The liquid crystal panel 41, as shown in FIG.
It consists of T, pixel electrode, additional capacitance, and liquid crystal. A selected drain voltage 35 is applied to the selected drain line. That is, VCOM47, which is the counter potential of the pixel electrode, is V
When the potential is 0, as shown in FIG. 9, four levels of potential V1 to V4 are applied to each horizontal period T.
Output for periods t0, t1, t2, and T. Also, VCOM4
7 becomes the potential of V6, as shown in FIG.
6-V1 to V6-V4 are output for periods t0, t1, t2, and T for one horizontal period T, respectively. At this time, the first pixel gate pulse 23 to the Nth pixel gate pulse 25 select and output one of the four pulse waveforms shown in FIG. 11 according to the gradation information of the display data of the first line. For example, when displaying gradation 2 on the (1, 1) pixel, the first pixel gate pulse 23 outputs the pulse shown in (b) of FIG. 11. At this time, the (1, 1) pixel TFT 4
4 becomes the voltage V5 during the t1-td period from the beginning of one horizontal period T, so it is in the on state, and the first drain line 38
A voltage applied to the pixel electrode 500 is applied to the pixel electrode 500. That is, the pixel electrode 500 has a t0 period V1 (V6-V
1) The voltage is t1-td-t0 period V2 (V6-V2)
A voltage will be applied to the liquid crystal 46, and VCOM4 will be applied to the liquid crystal 46.
The difference voltage between V0 (V6) and V2, which is the voltage of 7, is stored, and the difference voltage between the voltage of the unselected drain voltage 36 and V2 (V6 - V2) is stored in the additional capacitor 45 (hereinafter , this operation is called writing). When the first pixel gate pulse 23 reaches V0 level, the (1, 1) pixel TF
T44 is turned off and the stored voltage is held until the next write. That is, the voltage of the drain line at the falling edge of the gate pulse is written. At this time, since the voltage of the first drain line 38 is held at the V2 voltage for only the td period thereafter, it is possible to accurately write the V2 voltage even if there is a delay in each drain line or gate line. . Further, the pixel additional capacitor is provided to compensate for the fact that the liquid crystal capacitance alone is insufficient for this holding operation. Therefore, if the holding operation is possible with the capacity of the liquid crystal, there is no need to provide it. The pixel additional capacitor is formed between the drain line of the previous line, but since the previous line does not exist for only the first line, an additional drain line 42 is specially provided and formed between it.

That is, assuming that the first line drain line 38 is in the selected state and the selected drain voltage 35 is output, the gate pulse width of the first pixel gate pulse 23 to the Nth pixel gate pulse 25 is one horizontal N. A desired voltage to be displayed can be written to each pixel. At this time, since the additional drain line 42 is at the voltage level of the unselected drain voltage 36, the additional capacitance stores the difference voltage between that voltage level and the pixel electrode. In the next horizontal period, the second line drain voltage 39 is in the selected state, and the second line N
Write to the pixel. At this time, since the first drain line 38 is at the voltage level of the non-selected drain voltage 36, the additional capacitance stores the difference voltage between that voltage level and the pixel electrode. This is repeated line by line until the Mth line. Display is performed by repeating this operation. Further, the reason why the voltage stored in the liquid crystal is set to the + side and the - side with respect to the VCOM 47 as shown in FIGS. 9 and 10 is that the liquid crystal needs to be driven with alternating current. That is, as shown in FIG. 12, for example, when performing gradation 2 display on the (1, 1) pixel, the V2 voltage is written when the first line is selected in the first frame (scanning period of all M lines). By writing the V6-V2 voltage in the next frame, VCOM47 is changed to V0 and V6 every frame, and the absolute value of the voltage V2 is written to the liquid crystal, and the polarity is switched every frame. can be realized.

Next, the operation of a liquid crystal display device to which the present invention is applied will be explained using FIGS. 1 and 13 to 19. The display data latch circuit 8 is initialized at the rising edge of the horizontal clock 3, and then the display data 1 sequentially captures one horizontal portion of display data using the data clock 2. The captured display data is output from the display data latch circuit 8 as first pixel display data 9, second pixel display data 10, and Nth pixel display data 11, and is outputted from the horizontal latch circuit 12 at the next rising edge of the horizontal clock 3. be taken in. Also, at this time, the display data latch circuit 8 is initialized again and prepares to take in the next line of display data. First pixel display data 13, second pixel display data 14, and Nth pixel display data 14, which are outputs of the horizontal latch circuit 12, are given to a pulse select circuit 18. The pulse generation circuit 16 is shown in FIG.
3, the "high" level of the horizontal clock 3 is inverted by the inverter circuit 57 and set to "low" level. F
．． 58-61, each F. F. Set. That is, as shown in FIG. F. Q of
Set the output to “high” level. Gate pulse clock 4
As shown in FIG. 13, this is a clock that outputs four pulses during one period T of the horizontal clock 3, and at the rising edge of the clock, F. F. 58, F. F. 59,...
…F. F. Set it to 61 and “low”. gate pulse 1
V1 pulse 57 to V4 pulse 7, which are the four pulses of 7
0 is each F. F. Since the QN outputs of each F. in FIG. F. It has the same waveform as the Q output of . The pulse select circuit 18 is
Receives four pulses of gate pulse 17, receives gradation information of first pixel display data 13, second pixel display data 14, and Nth pixel display data 14, V1 pulse 67 for gradation 1 and V2 for gradation 2. Select pulse 68, V1 pulse 69 for gradation 3, V1 pulse 70 for gradation 4, and select pulse 19 for the first pixel.
, the second pixel pulse 20, and the Nth pixel pulse 21. The gate voltage selection circuit 22 selects the first pixel pulse 1.
9. The "high" of the second pixel pulse 20 and the N-th pixel pulse 21 correspond to the gate-on voltage 5, and the "low" correspond to the gate-off voltage 6, respectively. 24, output as the Nth pixel gate pulse 25. In other words, the gate driver 7 takes in one line of display data, and according to the gradation information of the display data, gradation 1 is set to gradation 1 in FIG. 11(a).
), the pulse of Fig. 11(b) for gradation 2, the pulse of gradation 3
For gradation 4, the pulse shown in FIG. 11(c) and the pulse shown in FIG. 11(d) are selected and output. The line shift circuit 29 is shown in FIG.
5, the leading signal 26 is taken in at the rising edge of the line clock 27 and the first line signal 30 is set to "high". Thereafter, at the rising edge of the line clock 27, the "high" state is sequentially shifted to the second line signal 31, . . . the M-th line signal 32. Among the first line signal 30 to the Mth line signal 32, the line that is "high" is the selected state line, and it can be seen from FIG. 15 that there is only one line that is in the selected state. The drain voltage selection circuit 37 selects a selected drain voltage 35, when the first line signal 30 to the Mth line signal 32 are “high”.
A non-selected drain voltage 36 is output in response to "low". The drain voltage generation circuit 34 continues to generate a constant voltage higher than the gate-on voltage 5 for the unselected drain voltage 36. On the other hand, the selected drain voltage 35 is generated by a voltage generation circuit shown in FIG. In the figure, the voltage gate generation circuit 71 inverts the "high" level of the line clock 27 with an inverter circuit 80, as shown in FIG. F. 82 and the remaining F.82. F. 83 to 85 are reset. As a result, G1~
As shown in FIG. 18, G4 becomes "high" when the line clock 27 goes "high", and G1 becomes "high", and G2 to G4 become "low". The drain clock 33, as shown in FIG.
Three pulses are output in one horizontal period, and at the rising edge of the first pulse, G1 is set to "low" and G2 is set to "high". At the subsequent rise of the drain clock 33, the "high" state is shifted to G3 and G4. As a result of the above, G1 to G4 become "high" in order in one horizontal period, and the switches 79 to 76 in FIG. 16 are turned on in order. As a result, as shown in FIG. 18, the selected drain voltage 35
first outputs Va in synchronization with the rise of the line lock 7, and then synchronizes with the rise of the drain clock 33,
Vb, Vc, and Vd are output in this order. Also, V
Each voltage from a to Vd is, for example, Va, as shown in FIG. A switch 93 whose gate is connected to the signal inverted by the circuit 91 is provided, and each switch is connected to V.
1. By connecting the V6-V1 voltage, the switches 92 and 93 are alternately turned on with an AC signal, and the output Va is alternately switched between V1 and V6-V1 every frame. Vc to Vd are V1 in FIG. 19, respectively.
are V2, V3, V4, and V6-V1 is V6-V2, V
By using 6-V3 and V6-V4, alternating current can be similarly realized. By the operation of the drain driver 28 and the drain voltage generation circuit 34, the first line drain signal 38 to the Mth line drain signal 40 are set to a voltage higher than the gate-on voltage 5 when not selected, and when selected, are set to the voltages shown in FIGS. 9 and 10. The voltage waveform shown in FIG.

In the embodiment, the number of gradations has been described as four levels, but the selected drain voltage 35 is assumed to be switched to L level voltage in one horizontal period, and the gate driver is configured to operate L gates with L types of pulse widths. L gradation display can be realized by generating pulses and selecting one pulse from the pulses based on display data. The liquid crystal panel 41 is also provided with an additional drain line 42, as shown in FIG. Although an additional capacitance is formed between the drain line and the counter electrode VCOM47, it is also possible to provide M lines of additional lines having the same potential as the counter electrode VCOM47 and form a capacitance between them. .

[0014]

[Effects of the Invention] According to the present invention, the gate voltage select circuit and the drain voltage select circuit, which have a high breakdown voltage, greatly affect the scale of the circuit, and are required for the number of pixels, are independent of the number of gradations. It can be kept constant, and a multi-gradation liquid crystal display device can be realized even in multi-gradation display without increasing the cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a liquid crystal display device showing an embodiment of the present invention;

[Fig. 2] Block diagram of a conventional liquid crystal display device,

[Figure 3] Pixel system diagram of conventional liquid crystal panel,

[Fig. 4] An explanatory diagram of the operation of the gate line,

[Fig. 5] Explanatory diagram of voltage-transmittance characteristics of liquid crystal,

[Fig. 6] System diagram of the gate voltage selection circuit for the first pixel,

[Fig. 7] An explanatory diagram of the display operation of the liquid crystal panel,

FIG. 8 is a pixel configuration diagram of the liquid crystal panel of the present invention,

FIG. 9 is an explanatory diagram of the drain waveform,

FIG. 10: Explanatory diagram of drain waveform,

FIG. 11 is an explanatory diagram of the operation of gate pulses,

FIG. 12 is an explanatory diagram of writing to pixels;

[Fig. 13] System diagram of pulse generation circuit,

FIG. 14 is an explanatory diagram of the operation of the pulse generation circuit,

FIG. 15 is an explanatory diagram of the operation of the line shift circuit,

[Figure 16] System diagram of drain voltage generation circuit,

[Fig. 17] System diagram of voltage gate generation circuit,

FIG. 18 is an explanatory diagram of the operation of the drain voltage generation circuit,

FIG. 19 is a system diagram of a drain voltage alternating circuit.

[Explanation of symbols]

1...display data, 2...Data clock, 3...Horizontal clock, 4...Gate pulse clock, 7...Gate driver, 8...display data latch circuit, 12...Horizontal latch circuit, 16...Pulse generation circuit, 17...Gate pulse, 18...Pulse selection circuit, 22...gate voltage selection circuit, 23...First pixel gate pulse, 24...Second pixel gate pulse, 25...Nth pixel gate pulse, 27...Line clock, 28...Drain driver, 29...Line shift circuit, 33...Drain clock, 34...Drain voltage generation circuit, 37...Drain voltage selection circuit, 38...First line drain line, 39...Second line drain line, 40...M line drain line, 41...Liquid crystal panel.

Claims (6)

[Claims] 1. A liquid crystal display device in which one dot includes a switching element, a pixel electrode, a counter electrode, and a liquid crystal sealed between the pixel electrode and the counter electrode, when the switching element is turned on, the liquid crystal is transmitted through the switching element. The drain voltage applied to the pixel electrode is switched between N level voltages, controls the gate pulse width for turning on and off the switching element, and turns the switching element on when the drain voltage is at the voltage level desired to be stored in the pixel electrode. A multi-gradation liquid crystal display device that is turned off. 2. In claim 1, the display resolution is N dots in the horizontal direction and M dots in the vertical direction, and M drain lines supplying a common drain voltage to the N dots in the horizontal direction and M dots in the vertical direction. , N gate lines giving a common gate pulse are provided, the gate pulse width of each gate line is determined by each display data of N dots, and an L level voltage is supplied to the display line of N dots. However, a multi-gradation display device supplies a voltage higher than the gate pulse voltage to non-display lines. 3. In claim 2, an additional line with a voltage of the non-display line is always provided, and a capacitance is formed between the dots on the first line and the additional line, and the dots on the second and subsequent lines are is a multi-gradation liquid crystal display device that forms a capacitance between the drain line of the previous line of dots. 4. The multi-gradation liquid crystal display device according to claim 2, further comprising M additional lines having the same voltage level as the counter electrode, and a capacitance being formed between each dot and the additional line. 5. A drive circuit that receives display data and outputs a voltage waveform according to the display data, wherein the horizontal A pulse generation circuit is provided that generates L gate pulses that become a selection voltage level with a clock and sequentially become a non-selection voltage level with the output of the gate pulse clock. Depending on the gradation information of display data, L
A liquid crystal drive circuit characterized in that one pulse is selected and outputted using five gate pulses. 6. In a scanning circuit for instructing an operation line of a liquid crystal display device, a drain selection voltage that switches and outputs an L level voltage in one horizontal period and a drain non-selection voltage of a constant level are inputted, and a drain non-selection voltage of a constant level is inputted. A liquid crystal drive scanning circuit, characterized in that it outputs the drain selection voltage, and outputs the drain non-selection voltage in a non-selective manner for non-selected lines.