KR20140082488A

KR20140082488A - Liquid crystal display device and driving method thereof

Info

Publication number: KR20140082488A
Application number: KR1020120152521A
Authority: KR
Inventors: 박용화; 오대석
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-12-24
Filing date: 2012-12-24
Publication date: 2014-07-02
Also published as: KR102019763B1

Abstract

The present invention relates to a liquid crystal display device. The technical objective of the present invention is to provide a liquid crystal display device, which can be driven in an interlace manner using a gate shift clock consisting of two pulses with different pulse widths and a gate start pulse supplied twice during one frame, and a method for driving the same. To this end, the liquid crystal display device according to the present invention comprises: a gate drive IC for sequentially outputting a gate on signal to a first gate line group during a half frame and sequentially outputting the gate on signal to a second gate line group during the other half frame using a gate shift clock in which two pulses with different pulse widths are repeatedly formed, a gate output enable signal, and a gate start pulse supplied every half frame; and a timing controller for outputting the gate start pulse, the gate output enable signal, and the gate shift clock to the gate drive IC by generating the gate start pulse, the gate output enable signal, and the gate shift clock.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device driven by an interlace method and a driving method thereof.

2. Description of the Related Art As various portable electronic devices such as a mobile communication terminal, a smart phone, a tablet computer, a notebook computer and the like are developed, a demand for a flat panel display device that can be applied to the portable electronic device is gradually increasing. As such a flat panel display device, a liquid crystal display device, a plasma display panel (PDP), a field emission display device, an organic light emitting display device Research. Among the flat panel display devices, liquid crystal display devices are most widely commercialized at present because of advantages of mass production technology, ease of driving means, and realization of high image quality.

The liquid crystal display device drives the liquid crystal panel by various inversion methods in order to prevent the deterioration of the liquid crystal and to improve the display quality. Inversion methods include a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, or a Z-inversion system Z-Inversion System) method.

On the other hand, for low-power driving, most liquid crystal display devices mainly use the Z-inversion method among the above-mentioned inversion methods. However, the Z-inversion method is disadvantageous in that the power consumption is high in the R / G / B monochromatic pattern. In order to solve this problem, an interlace method is applied to a conventional liquid crystal display device.

FIG. 1 is a diagram illustrating waveforms of scan signals output from a conventional interlace gate driver, and FIG. 2 is a diagram illustrating a conventional panel structure for interlace driving. Referring to FIG.

There are two methods of applying the interlace method in the liquid crystal display device.

First, there is a method of using an interlace gate driver IC for outputting a scan signal as shown in FIG.

That is, the scan signal shown in FIG. 1 is a scan signal output from the interlace gate drive IC, and the gate drive IC separates the scan signals output to the odd gate lines and the even gate lines, And shifts the scan signal by one clock using a shift register.

Accordingly, the scan signals are output to the odd gate lines during the 1/2 frame, and the scan signals are output to the even gate lines during the remaining 1/2 frame.

Meanwhile, in order to perform interlaced driving as described above, a conventional general gate drive IC can not be applied, and a separate gate drive IC must be developed and manufactured for interlace driving.

Second, as shown in FIG. 2, there is a method of changing the structure of the gate line formed on the panel to match the interlace method.

That is, in the second method as described above, conventionally used gate drive ICs are respectively mounted on the left and right sides of the panel, and the gate lines are connected to the left gate drive IC and the right gate drive IC by one line .

In this case, the gate drive ICs must be driven by a single feeding method. The single feeding method refers to a method of inputting a scan signal only from one side of a gate line. That is, when a general driving method other than the interlaced method is applied, the two gate drive ICs mounted on the right and left sides of the panel can simultaneously input scan signals into one line (double feeding method) The two gate drive ICs mounted on the right and left sides of the panel can input scan signals only to one gate line, respectively.

That is, although a conventional general gate drive IC can be applied as it is in the second method, a method of forming gate lines and a method of inputting a scan signal into a gate line are changed.

The above-described conventional interlace methods have the following problems.

As in the first method, if a gate drive IC for interlacing is used, a new gate drive IC must be developed and the structure of the panel must be modified to accommodate the newly developed gate drive IC. That is, the cost of development and panel modification of the gate drive IC is increased.

As in the second method, when the interlaced method is applied through the change of the panel structure, not only the cost due to the change of the panel structure but also the increase of the horizontal line dim (line) due to the single feeding of the left / Dim) may cause image quality problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of being driven in an interlaced manner using a gate shift clock formed by two pulses having different pulse widths and a gate start pulse supplied twice during one frame, And a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display device including a gate shift clock, a gate output enable signal, and a gate start pulse supplied every 1/2 frame, wherein two pulses having different pulse widths are repeatedly formed, A gate drive IC for sequentially outputting a gate-on signal to the first gate line group during a half frame and sequentially outputting a gate-on signal to the second gate line group during the remaining half frame; And a timing controller for generating the gate start pulse, the gate output enable signal, and the gate shift clock and outputting the gate start pulse, the gate output enable signal, and the gate shift clock to the gate drive IC.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device including a first gate-start pulse and a first gate-start pulse having a first pulse width and a second pulse- The gate-on signal having a pulse width smaller than the pulse width is output to the gate lines formed in the second gate line group, and the gate-on signal having the pulse width smaller than the pulse width is outputted to the gate lines formed in the second gate line group Blocking; And a gate-on signal having a large pulse width to the gate lines formed in the second gate line group for the remaining 1/2 frame in accordance with the second gate star pulse and the gate shift clock, And blocking a gate-on signal having a smaller pulse width from being output to the gate lines formed in the first gate line group.

According to the present invention, an interlace method can be realized by using a conventional general gate drive IC without a gate drive IC for an interlace method being specifically developed or a panel structure being changed. Therefore, there is no increase in costs for development of a gate drive IC for an interlaced method or panel change.

In addition, according to the present invention, the conventional double feeding method can be applied as it is while using an interlace method, so that there is no image quality problem such as a horizontal line dim.

1 is an exemplary view showing a waveform of a scan signal output from a conventional interlace gate driver;
2 is an exemplary view showing a conventional panel structure for interlace driving.
Fig. 3 is an exemplary view schematically showing a liquid crystal display device according to the present invention. Fig.
4 is an exemplary diagram for explaining a method of driving a liquid crystal display device according to the present invention.
5 is an exemplary view of a shift register applied to a liquid crystal display device according to the present invention.
6 is a diagram for explaining a method of outputting a gate-on signal in a gate drive IC of a liquid crystal display according to the present invention.
7 is an exemplary view showing the timing of various signals applied to the liquid crystal display according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

3 is an exemplary view schematically showing a liquid crystal display device according to the present invention.

The present invention realizes an interlace method using a gate drive IC which has been conventionally used. That is, according to the present invention, by changing the pulse structure of the gate shift clock (GSC) input to the gate drive IC in a state where the interlace gate drive IC is further developed or the structure of the panel is not changed, Can be implemented.

3, a liquid crystal display according to an exemplary embodiment of the present invention includes a panel 100 in which pixels are formed at intersections of gate lines GL1 to GLn and data lines DL1 to DLm, A source drive IC 300 for outputting a data voltage to the data line, a gate drive IC 200 for sequentially outputting a gate-on signal to the gate line, and a gate control IC 200 for outputting a gate control signal and a data control signal to the source drive IC And a timing controller (400) for transferring the image data to the gate drive IC and rearranging the input image data to the source drive IC.

First, the panel 100 includes pixels including a thin film transistor (TFT) and a pixel electrode, which are formed for each region defined by intersections of the gate lines and the data lines DL1 to DLm.

The thin film transistor (TFT) supplies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line. The transmittance of light is adjusted by driving the liquid crystal in which the pixel electrode is located in contact with the common electrode in response to the data voltage.

The liquid crystal mode of the panel applicable to the present invention may be any mode of liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. Further, the liquid crystal display device according to the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

Next, the gate drive IC 200 sequentially supplies a gate-on signal to each of the gate lines using gate control signals (GCS) generated by the timing controller 400.

In particular, the gate drive IC 200 includes a gate shift clock GSC, a gate output enable signal GOE, and a gate start pulse GSP supplied every 1/2 frame in which two pulses of different pulse widths are repeatedly formed, ), Sequentially outputs a gate-on signal to the first gate line group during a half frame, and sequentially outputs a gate-on signal to the second gate line group during the remaining half frame.

Here, the gate-on signal refers to a voltage capable of turning on the switching thin film transistor connected to the gate lines. The voltage capable of turning off the switching thin film transistor is referred to as a gate off signal, and the gate on signal and the gate off signal are generically referred to as a scan signal.

When the thin film transistor is of the N type, the gate on signal is a high level voltage and the gate off signal is a low level voltage. When the thin film transistor is of the P type, the gate on signal is a low level voltage and the gate off signal is a high level voltage.

The gate drive IC 200 may be formed independently of the panel 100 and connected to the panel 100 through a tape carrier package TCP or a flexible printed circuit board (FPCB) As shown in the figure, a gate-in-panel (GIP) method in which the panel 100 is mounted may be used.

The configuration and function of the gate drive IC 200 will be described in detail with reference to FIGS. 5 to 7. FIG.

Next, the source driver IC 300 converts the digital image data transmitted from the timing controller 400 into a data voltage, and supplies the data voltage of one horizontal line for each horizontal period, which is supplied with a scan signal to the gate line, To the data lines.

The source drive IC 300 may be connected to the panel 100 in the form of a chip-on film (COF) as shown in FIG. 3, or may be mounted directly on the panel. The number of the source drive ICs 300 may be variously set according to the size of the panel, the resolution of the panel, and the like.

The source driver IC 300 converts the image data into the data voltage using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the data voltage to the data line. To this end, the source drive IC 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data Data sequentially received from the timing controller 400 and simultaneously outputs the latched digital image data Data to the digital-analog converter (DAC) 330.

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-analog converter uses the gamma voltage supplied from the gamma voltage generator (not shown) to generate the image data according to the polarity control signal POL transmitted from the timing controller 400 Polarity or negative polarity data voltage and outputs the data voltage to the data lines.

The output buffer outputs a positive or negative polarity data voltage transmitted from the digital-analog converter to the data line DL of the panel according to a source output enable signal SOE transmitted from the timing controller 400, .

Lastly, the timing controller 400 uses the timing signals input from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, Generates a data control signal DCS for controlling the operation timing of the source drive ICs 300 and a gate control signal GCS for controlling the operation timings of the source drive ICs 300, And generates image data to be processed.

To this end, the timing controller 400 includes a receiver for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals, A data arrangement unit for outputting rearranged image data Data, and an output unit for outputting the control signals and the image data.

That is, the timing controller 400 rearranges the input image data input from the external system according to the structure and characteristics of the panel 100, and outputs the re-arranged image data to the source drive IC 300 ). Such a function can be executed in the data arrangement section.

The timing controller 400 uses the timing signals transmitted from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, And a gate control signal (GCS) for controlling the gate driver, and transmits the control signals to the source driver IC and the gate driver. This function can be executed in the control signal generation unit.

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL.

The gate control signals GCS generated by the control signal generator 420 include a gate start pulse GSP, a gate start signal VST, a gate shift clock GSC, a gate output enable signal GOE, A signal VST, a gate clock GCLK, and the like.

Particularly, the gate shift clock GSC is formed such that two pulses having different pulse widths are repeatedly output. A pulse having a large pulse width among the two pulses is used to generate a gate-on signal substantially output to the gate line, and a pulse having a small pulse width among the two pulses is used as a gate-on signal .

The gate start pulse GSP and the gate start signal VST are all signals for starting the process of outputting the gate-on signal by the gate drive IC, and the gate drive IC is an IC Or in the form of a GIP. Therefore, in the following description, the two signals are simply referred to as a gate start pulse (GSP). The gate start pulse (GSP) is output to the gate drive IC twice during one frame. That is, the gate start pulse GSP is output to the gate drive IC 200 every half frame.

The gate output enable signal GOE is supplied to the gate drive IC 200 when a pulse having a small pulse width is supplied to the gate drive IC 200 from among the two pulses forming the gate shift clock GSC, When the gate drive IC 200 is supplied with a pulse having a large pulse width among the two pulses, the gate drive IC 200 is supplied with the gate drive IC, And is supplied to the gate drive IC so as to output a gate-on signal from the gate drive IC 200. That is, when a pulse having a large pulse width is supplied to the gate drive IC 200 from among the two pulses forming the gate shift clock GSC, the timing controller 400 controls the gate drive IC To the gate drive IC 200, a pulse having a small pulse width is output to the gate drive IC 200. The gate drive IC 200 outputs a gate output enable signal GOE for outputting a gate- The gate drive IC 200 transmits the gate output enable signal for preventing the gate drive IC 200 from outputting a gate on signal.

4 is a diagram for explaining a method of driving a liquid crystal display device according to the present invention.

In the liquid crystal display according to the present invention configured as described above, the gate-on signals are sequentially output to the gate lines formed on the liquid crystal panel in the order shown in FIG.

That is, in FIG. 4, when the odd gate lines are referred to as a first gate line group and the even gate lines are referred to as a second gate line group, gate start pulses The gate-on signal is sequentially output to the odd gate lines formed in the first gate line groups by the first gate start pulse GSP1. The odd gate lines formed in the first gate line groups are shown by solid lines in Fig.

The gate-on signal is sequentially output to the even-numbered gate lines formed in the second gate line groups by the second gate-start pulse GSP2 outputted to the gate drive IC 200 during the remaining 1/2 frame do. The even gate lines formed in the second gate line groups are shown by dashed lines in Fig.

In this case, the gate drive IC 200 includes a first non-display area 110 of the liquid crystal panel and a second non-display area 120 (see FIG. 3) facing the first non- Respectively. Therefore, the liquid crystal panel 100 may be driven by a double feeding method rather than a single feeding method.

That is, in the liquid crystal display device according to the present invention, the gate lines are driven in the same manner as in the conventional liquid crystal display device in which the gate lines are driven by the interlace method.

In the above description, the first gate line group is connected to the odd gate lines and the second gate line group is connected to the even gate lines. However, the present invention is not limited thereto. Therefore, the first gate line group may be connected to the even gate lines, and the second gate line group may be connected to the odd gate lines.

5 is an illustration of a shift register applied to a liquid crystal display device according to the present invention.

The gate drive IC 200 applied to the liquid crystal display according to the present invention includes a plurality of shift registers 210 for outputting a gate-on signal to each gate line, as shown in FIG.

That is, the gate-on signal output to each of the gate lines in FIG. 4 is generated in the shift register 210 of the gate drive IC 200.

The first shift register among the shift registers 210 starts driving by the gate start pulse GSP and outputs a signal corresponding to the gate shift clock GSC as a gate ON signal.

For this purpose, the gate shift clock GSC is sequentially supplied to the shift registers 210.

At this time, the two pulses forming the gate shift clock GSC are alternately input to the shift registers connected to the first gate line group and the shift registers connected to the second gate line group do.

On the other hand, the pulse having a large pulse width and the pulse having a small pulse width are input to the shift register and used for outputting a gate-on signal. That is, since the gate-on signal is output by both the pulse having the large pulse width and the pulse having the small pulse width, the shift registers 210 can be sequentially driven.

In detail, the gate shift clock GSC is for causing the shift registers 210 to sequentially output a gate-on signal. The gate shift clock GSC is a clock signal having a gate- The pulse width can be changed.

FIG. 5 shows an example of the first shift register 210 to which the gate start pulse GSP is input, among the shift registers 210.

That is, the first shift register 210 receives the gate start pulse GSP transmitted from the timing controller 400, and starts driving to output a gate-on signal corresponding to the gate shift clock GSC . Therefore, the pulse width of the gate-on signal output to the output terminal (Vout) of the first shift register 210 can be changed according to the magnitude of the pulse width of the gate shift clock GSC.

The gate-on signal output from the first shift register is used as a gate start pulse of the second shift register. That is, the second shift register receives a gate-on signal transmitted from the first shift register as a gate-start pulse (GSP) and starts driving to output a gate-on signal corresponding to the gate shift clock GSC .

Meanwhile, the shift register 210 shown in FIG. 5 shows an example of a shift register that can be applied to the present invention. The shift register 210 can be applied as it is in the currently used configuration. Therefore, the detailed description of the shift register 210 will be omitted.

FIG. 6 is a view for explaining a method of outputting a gate-on signal in the gate drive IC of the liquid crystal display according to the present invention, and FIG. 7 is a diagram illustrating timing of various signals applied to the liquid crystal display according to the present invention. .

A method of driving a liquid crystal display according to the present invention will now be described with reference to FIGS. 6 and 7. FIG.

First, when a half frame starts, a first gate start pulse GSP is supplied from the timing controller 400 to the first shift register 210 of the gate drive IC, and the first shift register 210, .

When the first shift register (Shift Register 1) is driven, the first shift register 210 outputs the first gate-on signal 290 using the gate clock GSC, , The first gate-on signal 290 drives a second shift register (Shift Register 2).

Here, the gate shift clocks GSC have different widths. For example, as shown in FIG. 6, a large pulse width and a small pulse width may have a ratio of 3: 1. The ratio of the pulse width may be variously changed so that the large pulse width and the small pulse width may be asymmetric with each other.

The reason why the respective pulse widths of the gate shift clock GSC are set to 3: 1 as described above is to make the pulse width of the gate-on signal outputted to the odd gate lines and the even gate lines 3: 1 .

As described above, since the pulse width of the gate-on signal corresponds to the pulse width of the gate shift clock GSC, the pulse width of the gate-on signal output by the pulse having a small pulse width is Is smaller than the pulse width of the gate-on signal output by the gate-on signal.

In the present invention, among the asymmetrically formed gate-on signals, a gate-on signal having a small pulse width is prevented from being output to the gate line, and only gate-on signals having a large pulse width are substantially output to the gate line So that the switching transistor can be turned on.

That is, in the present invention, the pulse width of the gate shift clock GSC is formed asymmetrically as described above in order to maximally broaden the pulse width of the gate-on signal finally output to the gate line.

The above process will be described in detail.

For example, when a first pulse having a large pulse width is input to a first shift register (Shift Register 1) connected to a first gate line group, a pulse width successive to the first pulse The second pulse is inputted to a second shift register (Shift Register 2) connected to the second gate line group, and the third pulse having a large pulse width continuous to the second pulse is connected to the first gate line group And a fourth pulse having a pulse width successive to the third pulse is input to a fourth shift register (Shift Register 4) connected to the second gate line group . The above process is repeated for 1/2 frame.

5, the first shift register (Shift Register 1) outputs a gate-on signal 290 having a large pulse width, and the second shift register (Shift Register 2) The third shift register 3 outputs a gate on signal having a large pulse width and the fourth shift register 4 outputs a gate on signal 290 having a small pulse width, And outputs a signal.

Next, when the 1/2 frame passes and the remaining half frames start, the order of the gate shift clocks is changed and input to each of the shift registers.

That is, when a first pulse having a small pulse width among the two pulses is input to a first shift register (Shift Register 1) connected to the first gate line group, 2 pulses are input to a second shift register (Shift Register 2) connected to a second gate line group, and a third pulse having a continuous pulse width smaller than that of the second pulse is connected to the first gate line group A fourth pulse having a large pulse width successive to the third pulse is input to a fourth shift register (Shift Register 4) connected to the second gate line group . The above process is repeated for the remaining 1/2 frame.

Therefore, the first shift register (Shift Register 1) outputs a gate-on signal having a small pulse width as shown in FIG. 5, and the second shift register (Shift Register 2) The third shift register 3 outputs a gate-on signal having a small pulse width, and the fourth shift register 4 outputs a gate-on signal having a large pulse width.

That is, during the 1/2 frame, the shift registers (shift registers 1, 3, 5 ... n-1, n are even numbers) connected to the first gate line group receive the gate- And the shift registers (Shift Register 2, 4, 6 ... n) connected to the second gate line group sequentially generate a gate-on signal having a small pulse width.

The shift registers (shift registers 1, 3, 5 ... n-1, n are even) connected to the first gate line group during the remaining 1/2 frame are connected to the first gate line group And the shift registers (Shift Register 2, 4, 6 ... n) connected to the second gate line group sequentially generate the gate-on signals having the large pulse width.

In this case, the shift registers (shift registers 1, 3, 5 ... n-1, n are even) connected to the first gate line group during the 1/2 frame are connected to one of the two pulses (Shift Registers 2, 4, 6, ..., n) connected to the second gate line group, a pulse having a small pulse width among the two pulses Are sequentially input.

During the remaining 1/2 frame, the shift registers 1, 3, 5 ... n-1, and n are even numbers, which are connected to the first gate line group, And the pulse having a large pulse width is sequentially input to the shift registers 2, 4, 6, ..., n connected to the second gate line group.

On the other hand, the present invention implements the interlace method by blocking the output of the gate-on signal having a small pulse width output by the pulse having the small pulse width to the gate line.

That is, if the gate-on signal having a small pulse width outputted from the shift registers (Shift Register 2, 4, 6 ... n) connected to the second gate line group is blocked during the 1/2 frame, During the 1/2 frame, the gate-on signals (1, 3, 5, ..., n-1 and n are even numbers) having a large pulse width outputted from the shift registers Vgate1, Vgate3, Vgate5, ..., Vgate (n-1) are sequentially output to the odd gate lines.

Also, during the 1/2 frame, a pulse width of a gate-on signal having a small pulse width output from the shift registers (Shift Register 1, 3, 5 ... n-1, n is an even number) connected to the first gate line group The gate-on signals having a large pulse width outputted from the shift registers 2, 4, 6, ..., n connected to the second gate line group, (Vgate2, Vgate4, Vgate6 ... Vgate (n)) are sequentially output to the even-numbered gate lines.

Therefore, the liquid crystal panel can be driven in an interlaced manner.

The gate drive IC uses the gate output enable signal GOE transmitted from the timing controller 400 to prevent the gate-on signals having a small pulse width from being output to the gate line.

5, the gate drive IC 200 includes switching units 220 connected to the shift register on a one-to-one basis, and each of the switching units 220 includes a switching unit 220, When the gate-on signal having a large pulse width is inputted from the shift register, the gate-on signal having the large pulse width is output to the gate line by the gate output enable signal GOE, When the gate-on signal is input from the shift register, the gate-on signal with the small pulse width is blocked by the gate output enable signal.

The method of driving a liquid crystal display according to the present invention as described above will be described below with reference to FIG.

First, the data voltage Data is output to the data lines by the data enable DE and other control signals DE_Out and SOE.

At this time, when the first gate start pulse GSP2 is input to the gate drive IC 200, the gate drive IC 200 starts driving, and during the 1/2 frame, the gate shift clock GSC and (GCLK1, GCLK3, GCLK5 ... GCLK (n-1)) to the first gate line group, that is, the odd gate lines in accordance with the gate output enable signal GOE.

After the 1/2 frame passes and the remaining half frame starts and the second gate start pulse GSP2 is input to the gate drive IC 200, the gate drive IC 200 starts driving again The gate-on signals GCLK2, GCLK4, and GCLK2 to the second gate line group, that is, even-numbered gate lines, in accordance with the gate shift clock GSC and the gate output enable signal GOE, GCLK6 ... GCLK (n).

That is, according to the present invention, as described above, the interlace gate drive IC can be newly developed, or the liquid crystal display can be driven in an interlaced manner using a gate drive IC generally used without changing the structure of the liquid crystal panel .

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal display panel 200: gate drive IC
300: Source drive IC 400: Timing controller

Claims

A gate shift clock, a gate output enable signal, and a gate start pulse supplied every ½ frame in which two pulses of different pulse widths are repeatedly formed are used and a gate on signal is supplied to the first gate line group during 1/2 frame A gate drive IC for sequentially outputting a gate-on signal to the second gate line group during the remaining 1/2 frame; And
And a timing controller for generating the gate start pulse, the gate output enable signal, and the gate shift clock and outputting the gate start pulse, the gate output enable signal, and the gate shift clock to the gate drive IC.

The method according to claim 1,
Wherein the gate drive IC is formed in a first non-display area of the liquid crystal panel and a second non-display area facing the first non-display area, respectively.

The method according to claim 1,
The timing controller includes:
When a pulse having a large pulse width is supplied to the gate drive IC from among the two pulses forming the gate shift clock, the gate output enable signal for causing the gate drive IC to output a gate- To the gate drive IC,
When a pulse having a small pulse width is supplied to the gate drive IC, the gate output enable signal for preventing the gate drive signal from being output from the gate drive IC is transmitted to the gate drive IC And the liquid crystal display device.

The method according to claim 1,
The gate drive IC includes shift registers connected one-to-one with the gate lines,
During the 1/2 frame, the shift registers connected to the first gate line group sequentially generate a gate-on signal having a large pulse width, and the shift registers connected to the second gate line group generate pulse widths Sequentially generates these small gate-on signals,
The shift registers connected to the first gate line group sequentially generate a gate-on signal having a small pulse width during the remaining 1/2 frame, and the shift registers connected to the second gate line group, And sequentially generates the gate-on signal having the large pulse width.

5. The method of claim 4,
Wherein the two pulses are alternately inputted to shift registers connected to the first gate line group and shift registers connected to the second gate line group.

5. The method of claim 4,
During the 1/2 frame, a pulse having a larger pulse width is sequentially input to the shift registers connected to the first gate line group, and a shift register connected to the second gate line group A pulse having a small pulse width among the two pulses is sequentially input,
During the remaining 1/2 frame, the pulse having the small pulse width is sequentially input to the shift registers connected to the first gate line group, and as the shift registers connected to the second gate line group, And a pulse having a large width is sequentially inputted.

5. The method of claim 4,
The gate drive IC includes:
And blocks the gate-on signals having a small pulse width from being output to the gate lines according to the gate output enable signal.

5. The method of claim 4,
The gate drive IC includes:
And switching units connected one-to-one with the shift register,
Each of the switching units includes:
On signal having a large pulse width is output to the gate line by the gate output enable signal when the gate-on signal having a large pulse width is inputted from the shift register,
On signal having a small pulse width is blocked by the gate output enable signal when the gate-on signal having a small pulse width is input from the shift register.

The method according to claim 1,
The timing controller includes:
Generates the gate start pulse, outputs it to the gate drive IC at intervals of 1/2 frame,
The gate drive IC includes:
A gate-on signal having a large pulse width is outputted as the gate lines formed in the first gate line group according to the first gate start pulse, the shift clock and the gate output enable signal during the 1/2 frame, On signal having a pulse width smaller than the pulse width is prevented from being outputted to the gate lines formed in the second gate line group,
A gate-on signal having a large pulse width is output to the gate lines formed in the second gate line group in accordance with the second gate start pulse, the shift clock, and the gate output enable signal during the remaining 1/2 frame And a gate-on signal having a pulse width smaller than the pulse width is prevented from being output to the gate lines formed in the first gate line group.

A gate-on signal having a large pulse width is output as the gate lines formed in the first gate line group for 1/2 frame in accordance with the first gate start pulse and the gate shift clock in which two pulses having different pulse widths are repeatedly formed Blocking a gate-on signal having a pulse width smaller than the pulse width from being output to the gate lines formed in the second gate line group; And
A gate-on signal having a large pulse width is output to the gate lines formed in the second gate line group during the remaining 1/2 frame in accordance with the second gate star pulse and the gate shift clock, And blocking a gate-on signal having a small pulse width from being output to gate lines formed in the first gate line group.