KR101147091B1 - Apparatus for driving liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving device and a driving method of a liquid crystal display device to improve the image quality by minimizing the vertical dim.

An apparatus for driving a liquid crystal display according to the present invention has a plurality of data lines and a plurality of gate lines, an odd-numbered pixel column connected to a first side and an odd-numbered gate line of each of the data lines, and a first of the respective data lines. A liquid crystal panel comprising an image display portion having an even-numbered pixel column connected to two sides and an even-numbered gate line; A gate driver configured to supply gate pulses having different widths to the odd-numbered gate lines and the even-numbered gate lines, and a plurality of data integrated circuits to supply positive or negative data voltages to the data lines; And a timing controller for supplying and controlling a data signal to supply the positive or negative data voltage to each of the data lines, and controlling the gate driver.

By such a configuration, the present invention can improve the image quality by minimizing the vertical dim.

Description

Driving device for liquid crystal display {APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE}

1A and 1B illustrate line inversion according to the related art.

FIG. 2 is a waveform diagram showing polarities and gate pulses of data voltages supplied to respective pixels shown in FIGS. 1A and 1B.

3 is a diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a waveform diagram illustrating first to fourth gate shift clocks generated by the timing controller illustrated in FIG. 3.

5 is a driving waveform diagram illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

16, 116 pixels 110: liquid crystal panel

112: image display unit 120: printed circuit board

122: timing controller 130: TCP

140: data integrated circuit 150: first gate driving circuit

160: second gate driving circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device and a driving method of a liquid crystal display device capable of improving image quality by minimizing vertical dim.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Among such flat panel display devices, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

For this purpose, an active matrix liquid crystal display using a TFT (Thin Film Transistor) as a switching element is known. This active matrix type liquid crystal display device arranges gate lines and data lines in a matrix shape, and forms a liquid crystal material between a TFT array substrate having TFTs arranged at intersections thereof and an opposing substrate disposed at predetermined intervals from the substrate. It encloses and controls the voltage applied to this liquid crystal material by TFT, and enables display using the electro-optical effect of a liquid crystal.

As the number of pixels with high definition of the active matrix type liquid crystal display increases, the number of gate lines and data lines increases with increasing number of pixels, and the number of driving integrated circuits increases, thereby increasing costs. It is causing. In addition, the pitch between the driving integrated circuit and the pads for connection in the array substrate is narrowed, making it difficult to connect with each other, thereby lowering the yield of the connection work.

In order to solve this problem at the same time, Korean Patent Publication No. 2005-0000105 (published date, January 03, 2005) discloses a data driving integrated circuit by supplying potentials from one data line to two adjacent pixels in time division. A liquid crystal display and a driving method thereof are proposed which can reduce cost by reducing the number.

In Korean Patent Publication No. 2005-0000105, in order to prevent degradation of a liquid crystal and to improve display quality, the polarity of the data voltage is inverted to one of a frame, a line, and a dot, and a gate pulse is 1/2 horizontal for one horizontal period. Overlapping for each period is supplied to the gate line.

FIG. 2 is a waveform diagram illustrating polarities and gate pulses of data voltages supplied to each pixel illustrated in FIGS. 1A and 1B.

First, the polarity of the data voltage is supplied to be inverted in units of horizontal lines, and the gate pulse is supplied so that a half horizontal period overlaps with the gate pulse supplied to the previous gate line GL. At this time, the gate pulse supplied to the gate line GL has the same width.

Accordingly, each pixel 16 pre-charges the data voltage during the first period overlapping with the gate pulse supplied to the previous gate line GL during one horizontal period, and actually performs the second period. It will charge the data voltage.

2 will be described in detail with reference to FIGS. 1A and 1B.

First, odd-numbered pixels 16 connected to the first gate line GL1 during a period before the first period of the first horizontal period are each formed by a gate pulse overlapping the gate pulse supplied to the Nth gate line GLn. It is preliminarily charged by the negative data voltage supplied to each pixel 16 of the last horizontal line from the data line DL.

Then, the odd numbered pixels 16 connected to the first gate line GL1 precharged with the negative data voltage during the first period of the first horizontal period are each data line DL by the gate pulse. Data voltage of the positive polarity (+) for the odd-numbered pixels from &quot;

At the same time, the even-numbered pixel 16 connected to the second gate line GL2 during the first period of the first horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the first gate line GL1. The data voltage of the positive polarity (+) for odd-numbered pixels from each data line DL is precharged.

Subsequently, the odd-numbered pixel 16 connected to the second gate line GL2 precharged with the data voltage of the positive polarity (+) for the odd-numbered pixels during the second period of the first horizontal period is each data by the gate pulse. The data voltage of the positive polarity (+) for the even pixels from the line DL is charged.

At the same time, the odd-numbered pixel 16 connected to the third gate line GL3 during the second period of the first horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the second gate line GL2. The data voltage of the positive polarity (+) for even-numbered pixels from each data line DL is precharged.

Accordingly, the odd-numbered and even-numbered pixels 16 connected to the left and right sides of each data line DL charge the positive data voltage in the first horizontal period.

Then, the odd-numbered pixels 16 connected to the third gate line GL3 precharged with the positive data voltage during the first period of the second horizontal period are each data line DL by the gate pulse. Data voltage of the negative polarity (-) for the odd-numbered pixels from &quot;

At the same time, the even-numbered pixel 16 connected to the fourth gate line GL4 during the first period of the second horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the third gate line GL3. The data voltage of the negative polarity (-) for the odd pixel from each data line DL is precharged.

Subsequently, the even-numbered pixel 16 connected to the fourth gate line GL4 precharged with the negative-voltage data voltage for the odd-numbered pixels during the second period of the second horizontal period is generated by the gate pulse. The data voltage of the negative polarity (−) for the even pixels from the line DL is charged.

At the same time, the odd-numbered pixel 16 connected to the fifth gate line GL5 during the second period of the second horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the fourth gate line GL4. The data voltage of the negative polarity (−) for even-numbered pixels from each data line DL is precharged.

Accordingly, the odd-numbered and even-numbered pixels 16 connected to the left and right sides of each data line DL in the second horizontal period charge the negative data voltage.

As described above, the gate pulses having the same width are supplied to the gate lines GL to the pixels 16 during the third to Nth horizontal periods in the same manner as the first and second horizontal periods, and at the same time, the positive polarity is applied to each data line. The data voltages of the positive and negative polarities are supplied.

Accordingly, Korean Patent Publication No. 2005-0000105 is intended to drive a liquid crystal display by a line inversion driving method.

However, Korean Patent Publication No. 2005-0000105 described above supplies the gate pulses of the same width sequentially to each gate line GL, so that the first side of each data line DL and the odd-numbered gate lines GL1, GL3, Between the odd-numbered pixel column Po connected to ..., the second side of each data line DL, and the even-numbered pixel column Pe connected to the even-numbered gate lines GL2, GL4, ... There is a problem in that a vertical dim occurs due to a luminance difference.

Specifically, the odd pixel column Po is precharged with the polarity opposite to the data voltage of the actual polarity, while the even pixel column Pe is precharged with the same polarity as the data voltage of the actual polarity. That is, the odd-numbered pixel column Po is precharged with negative polarity (-) and then charged with a positive data voltage, or precharged with positive polarity (+) and then with a negative data voltage. Is charged. On the other hand, the even-numbered pixel column Pe is precharged with negative polarity (-) and then charged with a negative data voltage or precharged with positive polarity (+) and then with a positive data voltage. Is charged. As a result, the polarities of the data voltages applied to the odd-numbered pixel columns Po and the even-numbered pixel columns Pe during preliminary charging are different.

Therefore, the above-described Korean Patent Publication No. 2005-0000105 discloses the actual data voltage charged in each pixel 16 of the odd pixel column Po and the actual data charged in each pixel 16 of the even pixel column Pe. There is a problem that the image quality is degraded by the vertical dim due to the difference between the data voltage.

Accordingly, in order to solve the above problems, the present invention is to provide a driving device and a driving method of the liquid crystal display device to improve the image quality by minimizing the vertical dim.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention has a plurality of data lines and a plurality of gate lines, and includes a first side and an odd numbered gate line of each data line. A liquid crystal panel comprising an odd-numbered pixel column and an even-numbered pixel column connected to a second side of each data line and an even-numbered gate line; A gate driver configured to supply gate pulses having different widths to the odd-numbered gate lines and the even-numbered gate lines, and a plurality of data integrated circuits to supply positive or negative data voltages to the data lines; And a timing controller configured to supply and control a data signal to supply the positive or negative data voltage to each of the data lines, and to control the gate driver.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention includes an odd-numbered pixel column having a plurality of data lines and a plurality of gate lines, and connected to a first side and an odd-numbered gate line of each data line, respectively. A liquid crystal display comprising an image display having an even pixel column connected to a second side of a data line and an even gate line, wherein the odd-numbered gate line and the even-numbered gate line are provided with gate pulses having different widths. And supplying a positive or negative data voltage to each of the data lines so as to be synchronized with the gate pulse.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

3 is a diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention has a plurality of data lines DL and a plurality of gate lines GL, and a first side of each data line DL and an odd number. The odd pixel column Po connected to the first gate line GL1, GL3, ..., the second side of each data line DL, and the even gate line GL2, GL4, ... A liquid crystal panel 110 including an image display unit 112 having an even pixel column Pe; A gate driver for supplying gate pulses having different widths to odd-numbered gate lines GL1, GL3,..., And even-numbered gate lines GL2, GL4,. A plurality of data integrated circuits (140) for supplying a positive (+) or a negative (-) data voltage to each data line DL; A timing control unit 140 is provided to supply and control a data signal to supply a positive (+) or a negative (-) data voltage to each data line DL, and to control the gate driver.

In addition, the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention includes a timing controller 122 and a printed circuit board 120 on which a power circuit (not shown) is mounted, and each data integrated circuit 140. And a plurality of tape carrier packages (hereinafter, referred to as TCP) 130 connected between the printed circuit board 120 and the liquid crystal panel 110.

In addition, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, the gate driving part 150 supplies a gate pulse having a first width to the odd-numbered gate lines GL1, GL3,... )Wow; A second gate driving circuit 160 is provided to supply gate pulses of a second width different from the first width to the even-numbered gate lines GL2, GL4,...

The image display unit 112 displays the actual image by adjusting the light transmittance of each pixel according to the gate pulse supplied to each gate line GL and the data voltage supplied to each pixel column Po and Pe.

Each TCP 130 is electrically connected between the printed circuit board 120 and the liquid crystal panel 110 by a tape automated bonding (TAB) method. In this case, input pads of each TCP 130 are electrically connected to the printed circuit board 120, and output pads are electrically connected to the liquid crystal panel 110.

The timing controller 122 aligns the source data supplied from the driving system with the driving of the liquid crystal panel 110 according to the vertical, horizontal synchronizing signal and the data enable signal supplied from an external driving system so that each data integrated circuit ( 140).

In addition, the timing controller 122 may control a source start pulse (SSP) for controlling the driving timing of each data integrated circuit 140 using the vertical and horizontal synchronization signals and the data enable signal supplied from the driving system. A data control signal including a source shift clock (SSC), a polarity control signal (POL), and a source output enable signal SOE is generated and supplied to each data integrated circuit 140. At this time. The timing controller 122 generates the polarity control signal POL such that the polarity pattern of the image supplied to the image display unit 112 is inverted, that is, line inverted, in units of horizontal lines.

In addition, the timing controller 122 uses the vertical and horizontal synchronizing signals and the data enable signal supplied from the driving system to control the gate timing of each of the first and second gate driving circuits 150 and 160. First and second gate driving circuits by generating a gate control signal including a gate start pulse (GSP), a plurality of gate shift clocks (GSCs), and a gate output enable signal (GOE); (150, 160) to each supply.

The timing controller 122 generates a plurality of gate shift clocks according to the number of gate shift clocks for driving the shift registers configuring the first and second gate driving circuits 150 and 160. In this case, it is assumed that each of the first and second gate driving circuits 150 and 160 generates a gate pulse using two gate shift clocks.

Accordingly, the timing controller 122 may include the first and third gate shift clocks CLK1 and CLK3 having the first width W1 shown in FIG. 4 by using the vertical and horizontal synchronization signals and the data enable signal. The second and fourth gate shift clocks CLK2 and CLK4 having the second width W2 different from the first width W1 are generated. Here, the first width W1 is set to be larger than the second width W2, and preferably, the second width W2 is set at a ratio of 10: 7 to the first width W1.

In addition, the timing controller 122 sequentially delays the phases of the first to fourth gate shift clocks CLK1, CLK2, and CLK4 having the first and second widths W1 and W2 by one-half horizontal period. To be supplied to the first and second gate driving circuits 150 and 160. In this case, the first and third gate shift clocks CLK1 and CLK3 of the first width W1 are supplied to the first gate driving circuit 150, and the second and fourth gate shift clocks of the second width W2 are provided. CLK2 and CLK4 are supplied to the second gate driving circuit 160.

Each data integrated circuit 140 converts a data signal from the timing controller 122 into an analog data voltage in accordance with a data control signal input from the timing controller 122 through an input pad of the TCP 130. The output pads are supplied to the data lines DL of the liquid crystal panel 110. At this time, each data integrated circuit 140 generates a positive (+) or a negative (-) data voltage according to the polarity control signal POL from the timing controller 122 to generate a source from the timing controller 122. The data is supplied to each data line DL according to the output enable signal SOE.

The first gate driving circuit 150 is directly formed on one side of the liquid crystal panel 110 and electrically connected to the odd-numbered gate lines GL1, GL3, and GLn-1 of the image display unit 112. The first gate driving circuit 150 is driven by the gate start pulse GSP from the timing controller 122 and according to the first and third gate shift clocks CLK1 and CLK3 from the timing controller 122. Generates a gate pulse of a first width W1 in which the phase is sequentially delayed in units of one horizontal period, and according to the gate output enable signal GOE from the timing controller 122, a gate pulse of the first width W1. Are sequentially supplied to odd-numbered gate lines GL1, GL3 to GLn-1.

The second gate driving circuit 160 is directly formed on the other side of the liquid crystal panel 110 and electrically connected to the even-numbered gate lines GL2, GL4, and GLn of the image display unit 112. The second gate driving circuit 160 is driven by the gate start pulse GSP from the timing controller 122 and according to the second and fourth gate shift clocks CLK2 and CLK4 from the timing controller 122. Generates a gate pulse of a second width W2 in which the phases are sequentially delayed in units of one horizontal period, and according to the gate output enable signal GOE from the timing controller 122, a gate pulse of the second width W2. Are sequentially supplied to the even-numbered gate lines GL2 and GL4 to GLn.

Accordingly, the first and second gate driving circuits 150 and 160 are sequentially supplied with the gate pulses to the gate lines GL of the image display unit 112 so that the first and second gate driving circuits 150 and 160 overlap each other.

5 is a driving waveform diagram illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

First, polarities of the data voltages shown in FIG. 5 are inverted in units of horizontal lines (one horizontal period). Gate pulses of the first and second widths W1 and W2 overlapping during the 1/2 horizontal period are sequentially supplied.

Accordingly, each pixel 116 pre-charges the data voltage during the first period overlapping the gate pulse supplied to the previous gate line GL during one horizontal period, and the actual data in the remaining second period. It will charge the voltage. In this case, the data voltage charging time of the odd-numbered pixel column Po by the gate pulse of the first width W1 is longer than the even-numbered pixel column Pe by the gate pulse of the second width W2.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 5 as follows.

First, the odd-numbered pixel 116 connected to the first gate line GL1 in the previous period of the first horizontal period may overlap the gate pulse of the second width W2 supplied to the N-th gate line GLn. It is assumed that the data voltage of negative polarity (−) is precharged by the gate pulse of the first width W1 supplied from the first gate driving circuit 150.

Accordingly, in the first horizontal period, the second gate driving circuit 160 may overlap the gate pulse of the first width W1 supplied from the first gate driving circuit 150 to the first gate line GL1. The gate pulse of the second width W2 is supplied to the second gate line GL2. Accordingly, the gate pulse of the first width W1 supplied to the first gate line GL1 and the gate pulse of the second width W2 supplied to the second gate line GL2 overlap each other. During the first period, the odd-numbered pixels 116 connected to the first gate line GL1 precharged with the negative data voltage are each data line DL by the gate pulse of the first width W1. The odd-numbered pixel 116 connected to the second gate line GL2 is charged with each data line DL by the gate pulse of the second width W2. The preliminary charging of the data voltage of the positive polarity (+) for the odd-numbered pixels is performed.

Thereafter, the first gate driving circuit 150 may overlap the gate pulse of the second width W2 supplied from the second gate driving circuit 160 to the second gate line GL2. The gate pulse of the first width W1 is supplied to the gate. Accordingly, the gate pulse of the second width W2 supplied to the second gate line GL2 and the gate pulse of the first width W1 supplied to the third gate line GL3 overlap each other. During the second period, even-numbered pixels 116 connected to the second gate line GL2 precharged with the positive data voltage are each data line DL by gate pulses of the second width W2. The odd-numbered pixel 116 connected to the third gate line GL3 and charged to the even-numbered positive (+) data voltages from the N-th data lines DL by the gate pulse of the first width W1. Precharges the positive data voltage for the even-numbered pixels from.

Accordingly, odd-numbered and even-numbered pixels 16 connected to left and right sides of each data line DL charge the positive data voltage during the first horizontal period. In this case, the even-numbered pixel 116 precharged with the positive data voltage is the odd-numbered pixel 116 precharged with the negative data voltage by the gate pulse of the second width W2. The positive data voltage is charged for a time shorter than the charging time.

Then, in the second horizontal period, the second gate driving circuit 160 is overlapped with the gate pulse of the first width W1 supplied from the first gate driving circuit 150 to the third gate line GL3. The gate pulse of the second width W2 is supplied to the gate line GL4. Accordingly, in the second horizontal period in which the gate pulse of the first width W1 supplied to the third gate line GL3 and the gate pulse of the second width W2 supplied to the fourth gate line GL4 overlap each other. During the first period, the odd-numbered pixels 116 connected to the third gate line GL3 precharged with the positive data voltage are each data line DL by the gate pulse of the first width W1. The odd-numbered pixel 116 connected to the fourth gate line GL4 is charged with each data line DL by a gate pulse of the second width W2. The data voltage of the negative polarity (-) for odd-numbered pixels from () is precharged.

Subsequently, the first gate driving circuit 150 is connected to the fifth gate line GL5 to overlap the gate pulse of the second width W2 supplied from the second gate driving circuit 160 to the fourth gate line GL4. The gate pulse of the first width W1 is supplied. Accordingly, a second horizontal period in which the gate pulse of the second width W2 supplied to the fourth gate line GL4 and the gate pulse of the first width W1 supplied to the fifth gate line GL5 overlap each other. During the second period, the even-numbered pixels 116 connected to the fourth gate line GL4 precharged with the negative data voltage are each data line DL by the gate pulse of the second width W2. The odd-numbered pixel 116 connected to the fifth gate line GL5 and charged to the even-numbered negative polarity (−) data voltage from each of the data lines DL by the gate pulse of the first width W1. Precharge is performed for the even-numbered pixel negative polarity (−).

Accordingly, the odd-numbered and even-numbered pixels 16 connected to the left and right sides of each data line DL charge the negative data voltage during the second horizontal period. At this time, the even-numbered pixel 116 precharged with the negative data voltage is the odd-numbered pixel 116 precharged with the positive data voltage by the gate pulse of the second width W2. The negative data voltage is charged for a time shorter than the charging time.

The gates of the first width W1 in the odd-numbered gate lines GL1 and GL3 to GLn-1 in each pixel 116 during the third to Nth horizontal periods in the same manner as the first and second horizontal periods. The pulse and the gate gates of the second width W2 are supplied to the even-numbered gate lines GL2 and GL4 to GLn so as to overlap each other in a half horizontal period, and at the same time, the positive and negative polarities are applied to each data line. Supply the data voltage of.

Therefore, the driving device and the driving method of the liquid crystal display according to the embodiment of the present invention are odd by changing the charging time of each of the odd-numbered pixel columns Po and the even-numbered pixel columns Pe according to gate pulses having different widths. The vertical dim generated by the luminance difference between the first pixel column Po and the even pixel column Pe may be minimized.

Specifically, the odd pixel column Po is precharged with a polarity opposite to that of the actual data voltage, while the even pixel column Pe is precharged with the same polarity as the polarity of the actual data voltage. That is, the odd-numbered pixel column Po is precharged with negative polarity (-) and then charged with a positive data voltage or precharged with positive polarity (+) and then charged with a negative data voltage. do. On the other hand, the even-numbered pixel column Pe is precharged with negative polarity (-) and then charged with a negative data voltage or precharged with positive polarity (+) and then with a positive data voltage. Is charged.

Accordingly, the present invention uses the gate pulse of the first width W1 to charge the data voltage in the odd pixel column Po, while the gate pulse of the second width W2 smaller than the first width W1 is used. The data voltage is charged in the even-numbered pixel columns Pe using. That is, according to the present invention, since the other polarity is charged during precharging in the odd pixel column Po, the charging time of the actual data voltage is lengthened using the gate pulse of the first width W1, while the even pixel column is increased. In the case of (Pe), since the same polarity is charged during the preliminary charging, the charging time of the actual data voltage is shortened by using the gate pulse of the second width W2.

Therefore, the driving device and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention differ by varying the widths W1 and W2 of the gate pulses supplied to the odd-numbered pixel columns Po and the even-numbered pixel columns Pe. The vertical dim generated during the line inversion driving of the image display unit 112 can be minimized.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is a technology that the various substitutions, modifications and changes that can be made within the scope without departing from the spirit of the present invention It will be apparent to those skilled in the art.

The driving device and driving method of the liquid crystal display according to the embodiment of the present invention as described above are precharged by varying the widths of the gate pulses supplied to the odd-numbered pixel columns and the even-numbered pixel columns on both sides of the same data line during line inversion driving. When the actual data voltages of the odd-numbered pixel columns and the even-numbered pixel columns of different polarities are changed at different charging times, the image quality may be improved by minimizing the vertical dim.

Claims (17)

An odd-numbered pixel column having a plurality of data lines and a plurality of gate lines and connected to a first side and an odd-numbered gate line of each data line, and an even number connected to a second-side and even-numbered gate line of each data line A liquid crystal panel including an image display unit having a second pixel column; A gate driver configured to supply gate pulses having different widths to the odd-numbered gate lines and the even-numbered gate lines; A plurality of data integrated circuits for supplying a positive or negative data voltage to each of the data lines; A timing controller for supplying and controlling a data signal to supply the positive or negative data voltage to each data line, and for controlling the gate driver; The timing controller may include first and third gate shift clocks having a first width and repeating phases in units of one horizontal period, and a phase delay in units of one horizontal period having a second width different from the first width. Generating and supplying repeated second and fourth gate shift clocks to the gate driver; The gate driver, A first gate driving circuit for supplying a gate pulse of a first width to the odd-numbered gate lines using the first and third gate shift clocks of the first width; A second gate driving circuit for supplying a gate pulse of a second width to the even-numbered gate line using the second and fourth gate shift clocks of the second width; The second width relative to the first width is 10: 7; The gate pulses of the first width and the gate pulses of the second width are sequentially output, and the gate pulses of the first width and the gate pulses of the second width adjacent to each other overlap each other; The period in which the nth gate pulse of the first width and the n-1th gate pulse of the second width overlap each other is less than 1/2 horizontal period, and the nth gate pulse of the first width and n + 1 of the second width The period in which the first gate pulse overlaps corresponds to 1/2 horizontal period; And the plurality of data integrated circuits invert the polarities of the data voltages in units of one horizontal period. delete delete delete delete delete delete delete The method of claim 1, And the gate driver is formed in the liquid crystal panel. delete delete delete delete delete delete delete delete

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