KR20060096859A - Liquid crystal display and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, the apparatus comprising: a substrate, a plurality of gate lines formed on the substrate and transferring gate signals, and a plurality of data formed on the substrate and crossing the gate lines and transferring data voltages; A plurality of pixels connected to the line, the gate line, and the data line, first and second gate drivers disposed at both ends of the substrate and connected to odd and even gate lines, respectively, to supply a gate signal, and a data voltage. It includes a data driver for supplying. In this case, pixels of the same color are arranged along the gate line, pixels of different colors are arranged along the data line, and the first and second gate drivers overlap the gate signal and emit the overlapping gate signal. According to the present invention, the gate driving margin can be secured by providing the gate driver at both ends of the display panel while adopting the horizontal stripe pixel structure, and the degradation of image quality can be minimized even if one horizontal period is shortened by applying the three row inversion method or the thermal inversion method. have.

Liquid Crystal Display, Gate Driver, Horizontal Stripe, Invert Polarity, Horizontal Cycle

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

5 is a timing diagram of an input / output signal of a gate driver according to an exemplary embodiment of the present invention.

6 is a timing diagram of an output signal and a data voltage of a gate driver according to an exemplary embodiment of the present invention.

7 is a diagram illustrating an example of an inversion driving method of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 8 is a diagram illustrating a relationship between a data voltage and a common voltage of the inversion driving method shown in FIG. 7.

9 is a diagram illustrating an example of an inversion driving method of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 10 is a diagram illustrating a relationship between a data voltage and a common voltage of the inversion driving method shown in FIG. 9.

The present invention relates to a liquid crystal display and a driving method thereof.

In general, a liquid crystal display (LCD) includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

A liquid crystal display generally has a vertical stripe pixel structure in which R, G, and B pixels are sequentially formed in a horizontal direction, and a pair of R, G, and B pixels displays one image, that is, Used as a dot.

In order to drive R, G, and B pixels in a vertical stripe pixel structure, three output channels of the data driver IC are required, one for each pixel. However, since data driver ICs are expensive, the number of output channels increases the cost.

Accordingly, in order to reduce the number of output channels of the data driver IC, a liquid crystal display device having a horizontal stripe pixel structure has been developed. The horizontal stripe pixel structure is a structure in which R, G, and B pixels are sequentially formed in the vertical direction, and only pixels of the same color are arranged in one pixel row.

In the horizontal stripe pixel structure, the data line is reduced by one third compared to the vertical stripe pixel structure, while the gate line is increased three times. Therefore, the gate driving frequency is increased by three times, so that one horizontal period (“1H”), which is a time for applying one row of data voltages, becomes 1/3. 1 If the horizontal period is short, there is no time for various signals to operate normally, resulting in poor image quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of stably operating various signals while employing a horizontal stripe pixel structure.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a substrate, a plurality of gate lines formed on the substrate and transmitting a gate signal, and intersecting the gate lines formed on the substrate to cross a data voltage. A plurality of data lines to be transferred, a plurality of pixels connected to the gate line and the data line, and first and second ends respectively disposed at both ends of the substrate and connected to odd and even gate lines to supply the gate signal; A second gate driver and a data driver for supplying the data voltage, wherein pixels of the same color are arranged along the gate line, pixels of different colors are arranged along the data line, The second gate driver overlaps the gate signal and emits the overlapped gate signal.

It is preferable that the pulse width of the gate signal is substantially 2H.

The gate signals may overlap substantially in 1H units.

Before the data voltage corresponding to the pixel is applied, the data voltage of the previous pixel row may be applied to the pixel.

The first and second gate drivers may include a plurality of stages that emit the gate signals according to a plurality of control signals, and the stages may be integrated on the substrate.

The polarities of the data voltages of one pixel row may be the same.

The data driver may invert the polarity of the data voltage every pixel row of a predetermined unit.

The predetermined unit may be three.

The polarities of the data voltages of one pixel column may be the same.

The data driver may invert the polarity of the data voltage for each pixel column.

A plurality of gate lines, a plurality of data lines, the gate lines, and the data lines according to another embodiment of the present invention are arranged in the same color along the gate lines and in different colors along the data lines. A driving method of a liquid crystal display device including a plurality of pixels includes: applying a data voltage to the data line, applying a first gate signal to the gate line, and applying the gate line to a gate line adjacent to the gate line. Applying a second gate signal overlapping the first gate signal.

The polarity of the data voltage of one pixel row may be the same, and the method may further include inverting the polarity of the data voltage every pixel row of a predetermined unit.

The polarity of the data voltage of one pixel column is the same, and the method may further include inverting the polarity of the data voltage for at least one pixel column.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a driving method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is a schematic diagram of a liquid crystal display device which concerns on an example.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair of gate drivers 400L and 400R, and a data driver 500 connected thereto. ), A gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _2n , D ₁ -D _m , and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _2n and D ₁ -D _m in an equivalent circuit. .

The display signal lines G ₁ -G _2n and D ₁ -D _m are a plurality of gate lines G ₁ -G _2n transmitting gate signals (also called “scan signals”) and a data line D transferring data signals. ₁ -D _m ). The gate lines G ₁ -G _2n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _2n , D ₁ -D _m , a liquid crystal capacitor C _LC , and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q, such as a thin film transistor, is provided in the lower panel 100, and the control terminal and the input terminal are three-terminal elements, respectively, with gate lines G ₁ -G _2n and data lines D ₁ -D _m . The output terminal is connected to a liquid crystal capacitor (C _LC ) and a holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays the primary colors according to time (time division) so that the spatial and temporal combination of these primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue.

2 and 3 show that each pixel includes a color filter 230 representing one of the primary colors in a region corresponding to the pixel electrode 190 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The pair of gate drivers 400L and 400R are disposed at the left and right sides of the liquid crystal panel assembly 300, respectively, and the odd-numbered gate lines G ₁ , G ₃ , .. G _2n-1 and the even _- numbered gate lines G ₂ , G ₄ , .. G _2n ), and a gate signal formed of a combination of the gate-on voltage Von and the gate-off voltage Voff from the outside is applied to the gate lines G ₁ -G _2n . These gate drivers 400L and 400R include a plurality of stages arranged substantially in a row as a shift register. In FIG. 3, the gate drivers 400L and 400R are positioned in an area covered by the light blocking film 220 and are formed and integrated in the same process as the switching element Q of the pixel Px. However, it may be mounted in the form of an integrated circuit (IC).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The data driver 500 may be mounted directly on the liquid crystal panel assembly 300 in the form of a plurality of driving integrated circuit chips, or may be mounted on a flexible printed circuit film (not shown) to form a tape carrier package. ) May be attached to the liquid crystal panel assembly 300. Alternatively, the data driver 500 may be integrated in the liquid crystal panel assembly 300 like the gate driver 400. Alternatively, as shown in FIG. 3, the data driver 500 may be integrated into one integrated IC 900 together with the gray voltage generator 800 and the signal controller 600. The integrated IC 900 is mounted at one end of the liquid crystal panel assembly 300.

The liquid crystal panel assembly 300 structurally includes a lower panel 100, an upper display panel 200, and a light shielding film 220 defining the display area 210, and includes pixels and signal lines G ₁ -G _2n ,. Most of D ₁ -D _m is located in the display area 210. Since the upper panel 200 is smaller than the lower panel 100, a portion of the lower panel 100 is exposed, and the integrated IC 900 is mounted on the lower panel 100.

As shown in FIG. 3, each pixel Px has a horizontal stripe structure. That is, R, G, and B pixels are arranged in the column direction in order, and pixels of the same color are arranged in the row direction. A pair of R, G, and B pixels adjacent in the column direction form one dot to display one image. However, the color arrangement order of the pixels in the column direction is not limited thereto, and various changes may be made as necessary, such as B, R, G, or G, B, R, and the like.

According to the horizontal stripe pixel structure, the number of channels of the data driver 500 is reduced to 1/3 compared to the vertical stripe pixel structure, thereby reducing the manufacturing cost of the liquid crystal display.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. The signal controller 600 properly processes the image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate drivers 400L and 400R, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500).

The gate control signal CONT1 includes scan start signals STV1 and STV2 that indicate the start of scanning of the gate-on voltage Von, and at least one clock signal that controls the output of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal sync start signal STH for transmitting data of one pixel row, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage Vcom. And the inversion signal RVS and the data clock signal HCLK for inverting the polarity of the data voltage with respect to (hereinafter, referred to as "polarity of the data voltage" by reducing "polarity of the data voltage with respect to the common voltage").

The data driver 500 receives the image data DAT for one row of pixels according to the data control signal CONT2 from the signal controller 600, and displays each image among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to the data DAT, the image data DAT is converted into the corresponding data voltage and then applied to the data lines D ₁ -D _m .

The gate drivers 400L and 400R apply the gate-on voltage Von to the gate lines G ₁ -G _2n according to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G. _The switching element Q connected to _2n ) is turned on, and accordingly, a data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or " 1H ") (one period of the horizontal synchronization signal Hsync and the data enable signal DE), the data driver 500 and the gate drivers 400L and 400R are configured for the pixels in the next row. Repeat the same operation. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G ₁ -G _2n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarities of the data voltages flowing through one data line are changed according to the characteristics of the inversion signal RVS even in one frame (eg, inverted rows and inverted dots) or the polarities of the data voltages applied to one pixel row are also different from each other. (Eg: nirvana, point inversion).

Next, the gate driver and the timing of the gate signal and the data voltage according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention, FIG. 5 is a timing diagram of an input / output signal of the gate driver according to an exemplary embodiment of the present invention, and FIG. A timing diagram of an output signal and a data voltage of the gate driver.

First, the gate driver 400L will be described. The gate drivers 400L are arranged in a row and connected to odd-numbered gate lines G ₁ , G ₃ ,..., G _2n-1 , respectively. As a shift register including (SL ₁ -SL _n ), scan start signals STV1 and clock signals CLK1 and CLK2 are input. In addition, the gate driver 400L may separately receive the gate on voltage Von and the gate off voltage Voff.

Each stage SL ₁ -SL _n has a clock input terminal CLK, first and second signal input terminals IN1 and IN2, and an output terminal OUT.

Each stage SL ₁ -SL _n , for example, the i th stage SL _i , receives one of the clock signals CLK1 and CLK2 through the clock input terminal CLK, and receives the signal input terminals IN1 and IN2. ), the gate output signal (V _2i-3) of each of the front end stage (SL _i-1) through (hereinafter referred to as the "previous gate output") and the rear end stage (gate output signal (V _{2i + 1} of the SL _{i + 1)} ) (Hereinafter referred to as "back gate output"). The gate output signal V _2i-1 is output through the output terminal OUT.

However, the scan start signal STV1 is input to the first signal input terminal IN1 of the first stage SL ₁ and the second signal input terminal NI2 of the last stage SL _n of the gate driver 400L. . Further, the first clock signal CLK1 is supplied to the clock input terminal CLK of the odd-numbered stages SL ₁ , SL ₃ , ..., and the clock input of the even-numbered stages SL ₂ , SL ₄ , ... The second clock signal CLK2 is input to the terminal CLK.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage Von when the voltage level is high and the gate-off voltage Voff when the voltage level is high so as to drive the switching element Q of the pixel. Do. As shown in Fig. 5, each clock signal CLK1 and CLK2 has a period of 2T, a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 is 180 degrees.

In the initial state in which the front gate output V _2i-3 and the rear gate output V _{2i + 1} are both low, the gate output V _2i-1 is low. Then, when the rear gate output V _{2i + 1} remains low, and the front gate output V _2i-3 becomes high and then becomes low again, the gate output V _2i-1 becomes high. When the front gate output V _2i-3 remains low and the rear gate output V _{2i + 1} becomes high, the gate output V _2i-1 becomes low.

In other words, each gate output (V _2i-1 ) is at a high level in synchronization with the rising edge of the corresponding clock signal. However, as shown in FIG. 5, when the second clock signal CLK2 is input to the second stage SL ₂ , the first clock signal CLK1 is input to the front and rear stages SL ₁ and SL ₃ . Since the front and rear gate outputs V ₁ and V ₅ become high in synchronization with the rising edge of the first clock signal CLK1, the gate outputs V ₁ and V ₅ become high in synchronization with the falling edge of the second clock signal CLK2. . The high level holding time T of each gate output is 2H, and the front, present and rear gate outputs V _2i-3 , V _2i-1 , and V _{2i + 1} are continuously changed to a high state.

Meanwhile, the stages SL ₁ -SL _n include a plurality of thin film transistors (not shown). Although the internal circuit is not shown in the present specification, various circuit structures are possible.

Next, the gate driver 400R will be described. The gate drivers 400R are arranged in a row and connected to the even-numbered gate lines G ₂ , G ₄ ,..., G _2n , respectively. As the shift register including SR ₁ -SR _n , scan start signals STV2 and clock signals CLK3 and CLK4 are input. In addition, the gate driver 400R may separately receive a gate on voltage Von and a gate off voltage Voff.

Each stage SR ₁ -SR _n and its connection relationship is substantially the same as the stages SL ₁ -SL _n described above, and thus a detailed description thereof is omitted.

Each clock signal CLK3 and CLK4 also has a period of 2T, a 50% duty ratio, and a phase difference of the two clock signals CLK3 and CLK4 is 180 degrees. However, as shown in FIG. 5, the scan start signal STV2 is delayed in phase by 90 ° from the scan start signal STV1, and similarly, the clock signals CLK3 and CLK4 are also lower than the clock signals CLK1 and CLK2, respectively. The phase is delayed by 90 °.

The gate output V _2i of each stage SR ₁ -SR _n becomes high level in synchronization with the rising edge of the corresponding clock signal. The high level holding time T of each gate output is 2H, and the front, present and rear gate outputs V _2i-2 , V _2i , and V _{2i + 2} continuously change to a high state.

Therefore, referring to FIG. 6, the output signals V ₁ -V _2n of the gate drivers 400L and 400R have a pulse width of 2H and are sequentially applied to the gate lines G ₁ -G _2n by overlapping by 1H section. do. On the other hand, the data voltage Vd is applied to the data lines D ₁ -D _m every 1H. Therefore, data voltages of two pixel rows are sequentially applied to one pixel row at intervals of 1H. However, as soon as the data voltage applied first is charged as the data voltage for the previous pixel row, the data voltage of the pixel row is immediately applied again, so that the image of the previous pixel row is not displayed and does not affect the image display of the pixel row at all. .

In this way, the gate pulse width can be increased by overlapping the pulses of the gate signal, and the driving margin of the gate-on voltage is increased.

Next, the inversion driving method of the liquid crystal display will be described in detail with reference to FIGS. 7 to 10.

FIG. 7 is a diagram illustrating an example of an inversion driving method of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 8 is a diagram illustrating a relationship between a data voltage and a common voltage of the inversion driving method shown in FIG. 7. to be. 9 is a diagram illustrating an example of an inversion driving method of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 10 is a diagram illustrating a relationship between a data voltage and a common voltage of the inversion driving method shown in FIG. 9. to be.

First, referring to FIGS. 7 and 8, the liquid crystal display according to the present exemplary embodiment is driven by three row inversion in which the polarities of the data voltages of one pixel row are all the same and the polarity is inverted every three pixel rows. The common voltage Vcom swings the high voltage Vh and the low voltage Vl every 3H, and the polarity of the data voltage Vd is changed to positive and negative polarities every 3H.

As an example, as shown in FIG. 8, the common voltage Vcom is the low voltage Vl in the first to third pixel rows, and the magnitude of the data voltage Vd is larger than that, so that the polarity of the data voltage Vd is positive. The common voltage Vcom is the high voltage Vh in the next three pixel rows, and the magnitude of the data voltage Vd is smaller than that, so that the polarity of the data voltage Vd becomes negative.

For example, in the case of a liquid crystal display having a wide quarter video graphics array (WQVGA) resolution (480 * 234), the number of gate lines G ₁ -G _n is 702 in the horizontal stripe pixel structure of the present embodiment. do. Therefore, the length of 1H is approximately 20 ms, which is very short compared to 60 ms in the case of the vertical stripe pixel structure. However, if the three-row inversion scheme is adopted as in the present embodiment, the polarity inversion may have a time margin, and thus stable polarity inversion may be realized. Thus, even if one horizontal period is shortened, image quality does not deteriorate.

If necessary, you can invert every line larger or smaller than three.

By performing the inversion driving, the data driver 500 can be driven in a low voltage manner, and thus, the data driver 500 with low breakdown voltage can be used, thereby reducing the cost.

Next, referring to FIGS. 9 and 10, the liquid crystal display according to the present exemplary embodiment inverts the polarity of the data voltages descending on the neighboring data lines D ₁ -D _m in one frame and inverts the polarity of the data voltages. The polarities of the data voltages flowing along D ₁ -D _m ) are the same. The frame is then flipped on the next frame.

For example, the polarity of the data voltage Vd of the first pixel column R1, G1, B1, R2, G2, ... is positive, and the polarity of the data voltage Vd of the second pixel column is negative. The polarity of the data voltage Vd of the first pixel columns R1, G1, B1, R2, G2, ... of the next frame is negative.

For example, a liquid crystal display device having a video graphics array (VGA) resolution (640 * 480) or a super VGA (SVGA) resolution (800 * 600) has a gate line ( The number of G ₁ -G _n ) is 1,440 to 1,800. Therefore, the length of 1H is approximately 10 ms, which is very short compared to 30 ms in the case of the vertical stripe pixel structure. Therefore, inversion driving methods such as point inversion do not have time margin due to polarity inversion and the charging rate of the data voltage is low. Therefore, when the thermal inversion method is adopted as in the present exemplary embodiment, data voltages having the same polarity flow through the same data line, so that even if one horizontal period is short, time is allowed to charge the data voltage, thereby stably displaying an image. . In addition, the charging rate of the data voltage is also increased. In this case, the data driver 500 is driven in a high voltage manner.

As described above, according to the present invention, the gate driving margin can be secured by providing the gate driver at both ends of the display panel while adopting the horizontal stripe pixel structure. Can be.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (13)

Board, A plurality of gate lines formed on the substrate and transferring gate signals; A plurality of data lines formed on the substrate and crossing the gate lines to transfer data voltages; A plurality of pixels connected to the gate line and the data line, First and second gate drivers disposed at both ends of the substrate and connected to odd and even gate lines, respectively, to supply the gate signal; and A data driver supplying the data voltage Including; Pixels of the same color are arranged along the gate line, and pixels of different colors are arranged along the data line. The first and second gate drivers may overlap the gate signal. Liquid crystal display. In claim 1, And a pulse width of the gate signal is substantially 2H. In claim 2, The gate signal is substantially overlapped in units of 1H. In claim 3, And a data voltage of a previous pixel row is applied to the pixel before the data voltage corresponding to the pixel is applied. In claim 4, And the first and second gate drivers include a plurality of stages configured to emit the gate signals according to a plurality of control signals, and the stages are integrated on the substrate. In claim 1, And a polarity of the data voltage of one pixel row is the same. In claim 6, And the data driver inverts the polarity of the data voltage every pixel row of a predetermined unit. In claim 7, The predetermined unit is a liquid crystal display device. In claim 1, A liquid crystal display device having the same polarity of the data voltage of one pixel column. In claim 9, And the data driver inverts the polarity of the data voltage for each pixel column. And a plurality of pixels connected to the plurality of gate lines, the plurality of data lines, the gate line, and the data line, and arranged in the same color along the gate line and arranged in different colors along the data line. As a driving method of a liquid crystal display device, Applying a data voltage to the data line; Applying a first gate signal to the gate line, and Applying a second gate signal overlapping the first gate signal to a gate line adjacent to the gate line Method of driving a liquid crystal display comprising a. In claim 11, The polarities of the data voltages in one pixel row are the same, And inverting the polarity of the data voltage for every pixel row of a predetermined unit. In claim 11, The polarities of the data voltages of one pixel column are the same, And inverting the polarity of the data voltage for at least one pixel column.

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