CN109872675B - Serial peripheral interface circuit, display panel and driving method - Google Patents

Serial peripheral interface circuit, display panel and driving method Download PDF

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CN109872675B
CN109872675B CN201910324123.3A CN201910324123A CN109872675B CN 109872675 B CN109872675 B CN 109872675B CN 201910324123 A CN201910324123 A CN 201910324123A CN 109872675 B CN109872675 B CN 109872675B
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shift register
circuit
latch
data
line control
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CN109872675A (en
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袁丽君
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to PCT/CN2020/079147 priority patent/WO2020215923A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The application discloses a serial peripheral interface circuit, a display panel and a driving method. The serial peripheral interface circuit provides two groups of grid line control sub-circuits, and data are written into the pixel groups from different directions respectively. According to the scheme provided by the embodiment, data are written into the pixel groups in the pixel rows in different orders, so that the delay effect is offset, and the display quality is improved.

Description

Serial peripheral interface circuit, display panel and driving method
Technical Field
The present disclosure relates to display technologies, and particularly to a serial peripheral interface circuit, a display panel and a driving method.
Background
Currently, wearable products are increasingly popular, and for products with low resolution, in order to improve compatibility with a system, an SPI (Serial Peripheral Interface) circuit is generally used. The SPI Circuit is manufactured on the display panel (for example, by an LTPS (Low Temperature polysilicon) process), so that the IC (Integrated Circuit) cost can be saved, the system compatibility can be improved, and the frame can be reduced, which is widely used at present. The display panel with the SPI circuit integrated therein in the related art has a problem of display unevenness, and needs to be improved.
Disclosure of Invention
At least one embodiment of the invention provides a serial peripheral interface circuit, a display panel and a driving method, which can improve the display quality.
To achieve the above object, at least one embodiment of the present invention provides a serial peripheral interface circuit, including: the display device comprises a first grid line control sub-circuit, a second grid line control sub-circuit, a first shift register, a shift register group comprising a plurality of second shift registers and a latch group comprising a plurality of latches, wherein the first grid line control sub-circuit is connected with pixel groups in part of pixel rows in a display area, the second grid line control sub-circuit is connected with pixel groups in other pixel rows in the display area, the latches are in one-to-one correspondence with the second shift registers, and the latches are in one-to-one correspondence with the pixel groups of the pixel rows, wherein:
the first grid line control sub-circuit is used for controlling the opening of a corresponding pixel row according to data written in the first shift register, and generating a first opening signal to the shift register group to open the shift register group after the pixel row is opened;
the second grid line control sub-circuit is used for controlling the opening of the corresponding pixel row according to the data written in the first shift register, and generating a second opening signal to the shift register group to open the shift register group after the pixel row is opened;
the shift register group is used for controlling the plurality of second shift registers to sequentially generate second clock signals according to a first sequence under the control of a first clock signal and a first starting signal and outputting the second clock signals to corresponding latches; under the control of the first clock signal and the second starting signal, the plurality of second shift registers are controlled to sequentially generate second clock signals according to a second sequence and output the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence;
the first shift register is used for writing data into the first grid line control sub-circuit and the second grid line control sub-circuit under the control of a first clock signal, and sequentially writing data into the plurality of latches of the latch group under the control of a second clock signal;
and the latch group is used for sequentially writing the data in the latches into corresponding pixel groups in the started pixel rows under the control of a second clock signal.
In one embodiment, the first gate line control sub-circuit includes a first latch and a first decoder connected to each other, the first decoder connecting pixel groups in a part of pixel rows in the display region;
the first shift register writing data to the first gate line control sub-circuit includes: the first shift register writes data into the first latch;
the first latch is used for generating the first starting signal after the first shift register writes data into the first latch;
the first decoder is used for decoding data in the first latch and controlling the opening of the corresponding pixel row according to the decoded data.
In one embodiment, the second gate line control sub-circuit includes a second latch and a second decoder connected to each other, the second decoder connecting the pixel groups in the remaining pixel rows in the display area, wherein,
the first shift register writing data to the second gate line control sub-circuit includes: the first shift register writes data to the second latch;
the second latch is used for generating the second opening signal after the first shift register writes data into the second latch;
the second decoder is used for decoding the data in the second latch and controlling the opening of the corresponding pixel row according to the decoded data.
In one embodiment, the first order is from left to right and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
In one embodiment, the first gate line control sub-circuit is connected to the pixel groups in a part of the pixel rows in the display region as follows: the first grid line control sub-circuit is connected with the pixel groups in the odd-numbered pixel rows in the display area;
the second grid line control sub-circuit is connected with the pixel groups in the rest pixel rows in the display area as follows: and the second grid line control sub-circuit is connected with the pixel group in the even pixel row in the display area.
In one embodiment, the serial peripheral interface circuit further comprises a mode latch, and the first shift register is further configured to write data to the mode latch before writing the data to the first gate line control sub-circuit or the second gate line control sub-circuit under control of the first clock signal.
In one embodiment, the serial peripheral interface circuit further comprises a mode latch, and the first shift register is further configured to, under control of a first clock signal, write data into the mode latch before writing the data into the first gate line control sub-circuit or the second gate line control sub-circuit;
the first grid line control sub-circuit comprises a first latch and a first decoder which are connected, and the first decoder is connected with the pixel group in the odd pixel row in the display area;
the first shift register writing data to the first gate line control sub-circuit includes: the first shift register writes data into the first latch;
the first latch is used for generating the first starting signal after the first shift register writes data into the first latch;
the first decoder is used for decoding data in the first latch and controlling the opening of a corresponding pixel row according to the decoded data;
the second gate line control sub-circuit includes a second latch and a second decoder connected to each other, the second decoder connecting the pixel groups in the even-numbered pixel rows in the display area, wherein,
the first shift register writing data to the second gate line control sub-circuit includes: the first shift register writes data to the second latch;
the second latch is used for generating the second opening signal after the first shift register writes data into the second latch;
the second decoder is used for decoding the data in the second latch and controlling the opening of the corresponding pixel row according to the decoded data.
An embodiment of the present invention provides a display panel including the serial peripheral interface circuit according to any embodiment.
An embodiment of the present invention provides a driving method applied to a display panel according to any embodiment, including:
writing data of the first shift register into the first gate line control sub-circuit and the second gate line control sub-circuit based on control of a first clock signal;
controlling the opening of a corresponding pixel row according to data written into a first grid line control sub-circuit by a first shift register, and generating a first opening signal to the shift register group after the pixel row is opened;
controlling the plurality of second shift registers to sequentially generate second clock signals according to a first sequence through the first clock signal and the first opening signal, and outputting the second clock signals to corresponding latches; sequentially writing the data of the first shift register into a plurality of latches of the latch group under the control of the second clock signal, and writing the data in the latches into corresponding pixel groups in the opened pixel rows;
controlling the opening of a corresponding pixel row according to data written into the second grid line control sub-circuit by the first shift register, and generating a second opening signal to the shift register group after the pixel row is opened;
controlling the plurality of second shift registers to sequentially generate second clock signals according to a second sequence through the first clock signal and a second starting signal, and outputting the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence;
and sequentially writing the data of the first shift register into a plurality of latches of the latch group based on the control of the second clock signal, and sequentially writing the data in the latches into corresponding pixel groups in the opened pixel rows.
In one embodiment, the first order is from left to right and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
Compared with the prior art, an embodiment of the invention includes a serial peripheral interface circuit, which includes a first gate line control sub-circuit, a second gate line control sub-circuit, a first shift register, a shift register group including a plurality of second shift registers, and a latch group including a plurality of latches, and writes data into pixel groups in different pixel rows through different sequences, so that the delay effect is cancelled, and the display quality is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic diagram of an SPI circuit provided in the related art;
FIG. 2 is a schematic diagram of an SPI circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an SPI circuit according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of an SPI circuit according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of an SPI circuit according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of an SPI circuit according to another embodiment of the present invention;
FIG. 7 is a schematic view of a display panel according to an embodiment of the present invention;
FIG. 8 is a flowchart of a driving method according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of an SPI circuit provided in accordance with an illustrative embodiment of the present invention;
fig. 10 is a timing diagram according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Taking resolution 176 x 3 x 176 as an example, fig. 1 is a schematic diagram of an SPI circuit in the related art. In the SPI circuit provided in the related art, as shown in fig. 1, SI is sequentially written into 12-bit Shift registers and latched under the control of SCLK, data in the 12-bit Shift registers is first written into 6-bit Mode, then written into 8-bit Vdriver, and finally written into 44 12-bit LATs (Hdriver 12-bit LAT 1-Hdriver 12-bit LAT44) under the control of 44-bit Shift registers (Hdriver Shift registers 1-Hdriver Shift registers 44). In the circuit, Vdriver generates an STV signal of a 44-Bit shift register, under the control of SCLK, the 44-Bit shift register sequentially generates 44 clock signals from left to right, data in 12-Bit LAT and 44 12-Bit LAT are controlled to be sequentially written into 12 sub-pixels corresponding to 4 pixels from left to right under the control of 44 clocks, P1-P4 are written into the first, and P173-P176 are written into the last, and due to RC Delay, P173-P176 may have insufficient charge and cannot display a target gray scale. The left side is charged sufficiently and the right side is charged insufficiently for the entire panel, resulting in uneven display on the left and right sides. In the related art, pixel data of the SPI circuit is written in 4 pixels from the data latched by the Hdriver 12bit LAT module, and is sequentially written from left to right under the control of the Hdriver Shift Register, and the P173 to P176 pixels are written in the last, and may not display a target gray scale due to insufficient charging caused by transmission delay.
Fig. 2 is a schematic diagram of an SPI circuit according to an embodiment of the present invention. As shown in fig. 2, includes: a first gate line control sub-circuit 21, a second gate line control sub-circuit 22, a first shift register 23, a second shift register (24) comprising a plurality of second shift registers1～24N) Comprises a plurality of latches (25)1～25N) The latch group 25 of (1), wherein the first gate line control sub-circuit 21 is connected to the pixel groups in a part of the pixel rows in the display area, the second gate line control sub-circuit 22 is connected to the pixel groups in the remaining pixel rows in the display area, and the pixel rows include G1 to GNEach pixel row comprises M pixel groups (pixel group 1 to pixel group M), each pixel group comprises one or more pixels, for example 4 pixels, and the latches are in one-to-one correspondence with the second shift register (second shift register 24)iCorresponding to the latches i), the latches correspond to the pixel groups of the pixel rows one by one (for example, the latch 1 corresponds to the pixel group 1, the latch 2 corresponds to the pixel group 2, and so on), and it should be noted that fig. 2 shows that the first gate line control sub-circuit 21 is connected to the pixel group of the pixel row of the odd-numbered row, and the second gate line control sub-circuit 22 is connected to the pixel group of the pixel row of the even-numbered row, that is, cross-connected in a single row, but the present application is not limited thereto, and cross-connected in a unit of 2 rows, that is, the pixel group of the pixel row of 1,2, 5, 6, 9,10 …, and so on is connected to the first gate line control sub-circuit, and the pixel group of the pixel row of 3,4,7,8 …, and so on is connected to the second gate line control sub-circuit 22, or, the pixel rows of 1,2,4,5,7,8, and so on are connected to the, pixel rows 3,6, etc. connect to the second gate line control sub-circuit 22, and so on, where:
the first gate line control sub-circuit 21 is configured to control the turn-on of the corresponding pixel row according to the data written by the first shift register 23, and generate a first turn-on signal L _ STV to the shift register group 24 to turn on the shift register group 24 after the pixel row is turned on;
the second gate line control sub-circuit 22 is configured to control the on of the corresponding pixel row according to the data written by the first shift register 23, and generate a second on signal R _ STV to the shift register group 24 to turn on the shift register group 24 after the pixel row is turned on;
the shift register group 24 is used for controlling the plurality of second shift registers to sequentially generate the second clock signals according to the first sequence under the control of the first clock signal SCLK and the first start signal L _ STV, and output the second clock signals to corresponding latches (for example, the second shift registers 24)1The generated second clock signal is output to the latch 251A second shift register 242The generated second clock signal is output to the latch 252(ii) a Under the control of the first clock signal SCLK and the second opening signal R _ STV, controlling the plurality of second shift registers to sequentially generate second clock signals according to a second sequence and output the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence; taking the first sequence as left to right and the second sequence as right to left as an example, the second shift register 24 is controlled by the first clock signal SCLK and the first turn-on signal L _ STV1To 24MSequentially generating a second clock signal; the second shift register 24 is controlled by the first clock signal SCLK and the second turn-on signal R _ STVMTo 241In turn, generates a second clock signal.
The first shift register 23 is configured to write data into the first gate line control sub-circuit 21 and the second gate line control sub-circuit 22 under the control of a first clock signal SCLK, and to sequentially write data into the plurality of latches of the latch group under the control of a second clock signal SCLK; the writing of data into the first gate line control sub-circuit 21 and the second gate line control sub-circuit 22 may be cross writing, that is, data is first written into the first gate line control sub-circuit 21, then data is written into the second gate line control sub-circuit, then data is written into the first gate line control sub-circuit 21, and so on. Of course, data may be written to the first gate line control sub-circuit 21 and the second gate line control sub-circuit 22 in the refresh order of the pixel rows, and so on. The refresh sequence may be row-by-row refresh or otherwise.
The latch group 25 is configured to sequentially write the data in the latches into corresponding pixel groups in the turned-on pixel rows under the control of the second clock signal. For example, pixel row G1When the pixel is started, the data in the latch of the latch group is written into the pixel row G1Pixel group 1 through pixel group M. When the second clock signals in the latch group are sequentially generated in the first order, data are written in the pixel group 1 to the pixel group M in the first order, and when the second clock signals in the latch group are sequentially generated in the second order, data are written in the pixel group 1 to the pixel group M in the second order. For example, when the first order is from left to right, the pixel group 1 is written first, and the pixel group M is written last, and when the second order is from right to left, the pixel group M is written first, and the pixel group 1 is written last.
The SPI circuit that this embodiment provided writes into the pixel group in the pixel row with data through different orders to make the delay effect offset, improved the display quality.
In one embodiment, as shown in fig. 3, the first gate line control sub-circuit includes a first latch 211 and a first decoder 212 connected, and the first decoder 212 connects pixel groups in a part of pixel rows in the display area;
the writing of data into the first gate line control sub-circuit 21 by the first shift register 23 includes: the first shift register 23 writes data into the first latch 211;
the first latch 211 is configured to generate the first enabling signal after the first shift register 23 writes data into the first latch 211;
the first decoder 212 is configured to decode data in the first latch 211, and control the turning on of a pixel row connected thereto according to the decoded data.
In one embodiment, as shown in fig. 4, the second gate line control sub-circuit 22 includes a second latch 221 and a second decoder 222 connected to each other, the second decoder 222 connects the pixel groups in the remaining pixel rows in the display area, wherein,
the writing of data into the second gate line control sub-circuit 22 by the first shift register 23 includes: the first shift register 23 writes data to the second latch 221;
the second latch 221 is configured to generate the second open signal after the first shift register 23 writes data into the second latch 221;
the second decoder 222 is configured to decode the data in the second latch 221, and control the opening of the corresponding pixel row according to the decoded data.
In one embodiment, the first order is from left to right and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
In one embodiment, as shown in fig. 2 to 4, the first gate line control sub-circuit 21 connects the pixel groups in a part of the pixel rows in the display region as follows: the first gate line control sub-circuit 21 is connected to the pixel groups in the odd pixel rows in the display region;
the second gate line control sub-circuit 22 connects the pixel groups in the remaining pixel rows in the display region as follows: the second gate line control sub-circuit 22 connects the pixel groups in the even pixel rows in the display area. In this embodiment, by the odd-even line interleave driving, the odd-numbered line pixel data is transferred in one direction, the even-numbered line data is transferred in the other direction, and the odd-even line delay effects cancel each other out, thereby improving the display quality. It should be noted that this connection manner is merely an example. Other connection means are possible.
In one embodiment, as shown in fig. 5, the serial peripheral interface circuit further includes a mode latch 26, and the first shift register 23 is further configured to write data into the mode latch 26 before writing data into the first gate line control sub-circuit 21 or the second gate line control sub-circuit 22 under the control of the first clock signal.
In one embodiment, as shown in fig. 6, the serial peripheral interface circuit further includes a mode latch 26, and the first shift register 23 is further configured to, under the control of the first clock signal, write data into the mode latch 26 before writing data into the first gate line control sub-circuit 21 or the second gate line control sub-circuit 22;
the first gate line control sub-circuit 21 includes a first latch 211 and a first decoder 212 connected to each other, the first decoder 212 connecting the pixel groups in the odd pixel rows in the display region; the second gate line control sub-circuit 22 includes a second latch 221 and a second decoder 222 connected to each other, the second decoder 222 connecting the pixel groups in the even pixel rows in the display area, wherein,
the first shift register 23 writes data into the first latch 211 and the second latch 221; note that, here, the first shift register 23 writes data into the first latch 211 at a certain time and writes data into the second latch 221 at another time, and for example, data may be written into the first latch 211 and the second latch 221 in a cross-write manner, or data may be written into the first latch 211 and the second latch 221 in a refresh order of a pixel row, respectively.
The first latch 211 is configured to generate the first enabling signal after the first shift register 23 writes data into the first latch 211;
the first decoder 212 is configured to decode data in the first latch 211, and control the corresponding pixel row to be turned on according to the decoded data;
the second latch 221 is configured to generate the second open signal after the first shift register 23 writes data into the second latch 221;
the second decoder 222 is configured to decode data in the second latch 221, and control the opening of a corresponding pixel row according to the decoded data.
According to the same inventive concept, as shown in fig. 7, an embodiment of the present invention provides a display panel 70 including the serial peripheral interface circuit 71 according to any one of the embodiments. According to the display panel provided by the embodiment, the writing of the pixel rows is performed through different sequences, the delay effects of different pixel rows can be offset, and the display quality is improved.
An embodiment of the present invention provides a driving method, as shown in fig. 8, applied to the display panel, including:
step 801, writing data of the first shift register into the first gate line control sub-circuit and the second gate line control sub-circuit based on a first clock signal;
step 802, controlling the opening of a corresponding pixel row according to data written into a first gate line control sub-circuit by a first shift register, and generating a first opening signal to the shift register group after the pixel row is opened;
step 803, controlling the plurality of second shift registers to sequentially generate second clock signals according to a first sequence through the first clock signal and the first start signal, and outputting the second clock signals to corresponding latches; sequentially writing the data of the first shift register into a plurality of latches of the latch group under the control of the second clock signal, and writing the data in the latches into corresponding pixel groups in the opened pixel rows;
step 804, controlling the opening of the corresponding pixel row according to the data written into the second gate line control sub-circuit by the first shift register, and generating a second opening signal to the shift register group after the pixel row is opened;
step 805, controlling the plurality of second shift registers to sequentially generate second clock signals according to a second sequence through the first clock signal and a second start signal, and outputting the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence;
step 806, sequentially writing the data of the first shift register into a plurality of latches of the latch group based on the control of the second clock signal, and sequentially writing the data in the latches into corresponding pixel groups in the turned-on pixel rows.
The driving method provided by the embodiment writes data of different pixel rows from different orders, so that the delay effect is offset, and the display quality is improved.
In one embodiment, the first order is from left to right and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
The invention is further illustrated by the following specific example. Taking resolution 176 × 3 × 176 as an example for explanation, fig. 9 is a schematic diagram of an SPI circuit according to an embodiment of the present invention. As shown in fig. 9, in the present embodiment, the 12-bit Shift Register1 is a first Shift Register, the Mode 6-bit LAT is a Mode Register, the Shift Register group includes 44 Shift registers (Hdriver Shift Register 1-Hdriver Shift Register44), the left Vdriver 8bit LAT1 is a first latch, the left Vdriver Decoder1 is a first Decoder, the right Vdriver 8bit LAT2 is a second latch, the right Vdriver Decoder2 is a second Decoder, and the latch group includes 44 latches (Hdriver 12-bit LAT 1-Hdriver 12-bit LAT 44). Pixel rows G1-G176, each row comprising 44 pixel groups, each pixel group comprising 4 pixels. For example, pixels P1 through P4 form pixel group 1, pixels P5 through P8 form pixel group 2, pixels P169 through P172 form pixel group 43, and pixels P173 through P176 form pixel group 44.
The pixel writing process in this embodiment is described below.
The SI is written into 12-bit Shift Register and latched in turn under SCLK (clock signal) control, the data in 12-bit Shift Register1 is written into Mode 6bit LAT first, then written into Vdrive 8-bit LAT1 on the left side and latched, the data latched by Vdrive 8-bit LAT1 on the left side is decoded by Vdrive Decoder1 on the left side, each pixel group connected with the grid line G1 is opened, the Vdrive 8-bit LAT1 sends L-STV signals to Hdrive Shift Register1, Hdrive Shift Register1 is opened, Hdrive Shift Register 1-Hdrive Register44 generate 44 clock signals in turn under SCLK control, and the data in 12-bit Shift Register 2 is controlled to be written into 44 bits of Hdrive 12-bit LAT1 (Hdrive 12-bit LAT) in turn. Under the control of 44 clocks, data in 44 12Bit LATs are sequentially written into 12 sub-pixels corresponding to 4 pixels of a pixel line G1 from left to right, the first writing of P1-P4 is carried out, and the last writing of P173-P176 is carried out;
then the data in the 12-bit Shift Register1 is written into the right Vriver 8-bit LAT2, the data latched by the right Vriver 8-bit LAT2 is decoded by the right Vriver Decoder2, each pixel group connected with the grid line G2 is opened, the Vriver 8-bit LAT2 sends an R-STV signal to the Hdriver Shift Register44, the Hdriver Shift Register44 is opened, the Hdriver Shift Register44 to Hdriver Shift Register1 sequentially generate 44 clock signals under SCLK control, and the data in the 12-bit Shift Register1 is controlled to be sequentially written into 44 12-bit LATs (Hdriver 12-bit LAT44 to Hdriver 12-bit LAT 1). Under the control of 44 clocks, data in 44 12Bit LATs are sequentially written into 12 sub-pixels corresponding to 4 pixels of a pixel line G2 from right to left, the first writing of P1-P4 is carried out, and the last writing of P173-P176 is carried out;
the other pixel rows are similar, that is, the shift register group generates 44 clock signals from left to right when the odd rows are driven, the corresponding pixels are written in sequence from left to right, and the shift register group generates 44 clock signals from right to left when the even rows are driven, and the corresponding pixels are written in sequence from right to left.
In the scheme provided by this embodiment, two sets of Vdriver 8bit LATs and two sets of Vdriver decoders are designed, which correspond to Gate odd-even row cross driving, and generate two sets of STV signals to drive 44bit shift register sets. 44bit shift register group produced 44 clock signal from a left side to the right during odd line drive, and corresponding pixel writes in from a left side to the right side in proper order, produces 44 clock signal from a right side to the left during even line, and corresponding pixel writes in from a right side to the left side in proper order to during the odd line, the left side charges fully, and the right side charges insufficiently, and during the even line, the right side charges fully, and the left side charges insufficiently, and odd-even line delay effect offsets each other, has improved the display quality.
FIG. 10 is a timing diagram of data transmission. As shown in FIG. 10, SI is the data line, SCLK is the clock line, and SCS is the chip select signal. The SI sequentially transmits 6-bit Mode data (transmitted to the Mode 6-bit LAT), 10-bit V-driver (2-bit redundancy data (transmitted to the Vdrive 8-bit LAT) and H-driver data (transmitted to the Hdriver 12-bit LAT 1-Hdriver 12-bit LAT44), and then 16CLK (16 clock periods) is used as dummy for data transmission.
The SPI circuit that this embodiment provided can save the IC cost as display panel's interface circuit, improves product competitiveness.
The embodiment of the invention provides a novel SPI circuit which can be used for solving the problem of uneven display caused by transmission delay of the existing circuit and improving the display quality. In the related art, pixel data of the SPI circuit is written in 4 pixels from the data latched by the Hdriver 12bit LAT module, and is sequentially written from left to right under the control of the Hdriver Shift Register, and the rightmost pixel is written in the last, and the target gray scale cannot be displayed because of insufficient charging caused by transmission delay. In this embodiment, the odd-numbered rows and the even-numbered rows are driven to be crossed with each other, and the odd-numbered rows and the even-numbered rows are driven to be crossed with each other.
The following points need to be explained:
(1) the drawings of the embodiments of the invention only relate to the structures related to the embodiments of the invention, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present invention and features of the embodiments may be combined with each other to arrive at new embodiments.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A serial peripheral interface circuit, comprising: the display device comprises a first grid line control sub-circuit, a second grid line control sub-circuit, a first shift register, a shift register group comprising a plurality of second shift registers and a latch group comprising a plurality of latches, wherein the first grid line control sub-circuit is connected with pixel groups in part of pixel rows in a display area, the second grid line control sub-circuit is connected with pixel groups in other pixel rows in the display area, the latches are in one-to-one correspondence with the second shift registers, and the latches are in one-to-one correspondence with the pixel groups of the pixel rows, wherein:
the first grid line control sub-circuit is used for controlling the opening of a corresponding pixel row according to data written in the first shift register, and generating a first opening signal to the shift register group to open the shift register group after the pixel row is opened;
the second grid line control sub-circuit is used for controlling the opening of the corresponding pixel row according to the data written in the first shift register, and generating a second opening signal to the shift register group to open the shift register group after the pixel row is opened;
the shift register group is used for controlling the plurality of second shift registers to sequentially generate second clock signals according to a first sequence under the control of a first clock signal and a first starting signal and outputting the second clock signals to corresponding latches; under the control of the first clock signal and the second starting signal, the plurality of second shift registers are controlled to sequentially generate second clock signals according to a second sequence and output the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence;
the first shift register is used for writing data into the first grid line control sub-circuit and the second grid line control sub-circuit under the control of a first clock signal, and sequentially writing data into the plurality of latches of the latch group under the control of a second clock signal;
and the latch group is used for sequentially writing the data in the latches into corresponding pixel groups in the started pixel rows under the control of a second clock signal.
2. The serial peripheral interface circuit of claim 1, wherein the first gate line control sub-circuit comprises a first latch and a first decoder coupled to connect groups of pixels in a portion of rows of pixels in the display area;
the first shift register writing data to the first gate line control sub-circuit includes: the first shift register writes data into the first latch;
the first latch is used for generating the first starting signal after the first shift register writes data into the first latch;
the first decoder is used for decoding data in the first latch and controlling the opening of the corresponding pixel row according to the decoded data.
3. The serial peripheral interface circuit of claim 1, wherein the second gate line control sub-circuit comprises a second latch and a second decoder coupled to each other, the second decoder coupling groups of pixels in remaining rows of pixels in the display area, wherein,
the first shift register writing data to the second gate line control sub-circuit includes: the first shift register writes data to the second latch;
the second latch is used for generating the second opening signal after the first shift register writes data into the second latch;
the second decoder is used for decoding the data in the second latch and controlling the opening of the corresponding pixel row according to the decoded data.
4. The serial peripheral interface circuit of claim 1, wherein the first order is from left to right and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
5. The serial peripheral interface circuit of claim 1,
the first grid line control sub-circuit is connected with pixel groups in a part of pixel rows in the display area as follows: the first grid line control sub-circuit is connected with the pixel groups in the odd-numbered pixel rows in the display area;
the second grid line control sub-circuit is connected with the pixel groups in the rest pixel rows in the display area as follows: and the second grid line control sub-circuit is connected with the pixel group in the even pixel row in the display area.
6. The serial peripheral interface circuit of any of claims 1 to 5, further comprising a mode latch, wherein the first shift register is further configured to write data to the mode latch prior to writing data to the first gate line control sub-circuit or the second gate line control sub-circuit under control of the first clock signal.
7. The serial peripheral interface circuit of claim 1,
the serial peripheral interface circuit further comprises a mode latch, and the first shift register is further configured to, under control of a first clock signal, write data into the mode latch before writing the data into the first gate line control sub-circuit or the second gate line control sub-circuit;
the first grid line control sub-circuit comprises a first latch and a first decoder which are connected, and the first decoder is connected with the pixel group in the odd pixel row in the display area;
the first shift register writing data to the first gate line control sub-circuit includes: the first shift register writes data into the first latch;
the first latch is used for generating the first starting signal after the first shift register writes data into the first latch;
the first decoder is used for decoding data in the first latch and controlling the opening of a corresponding pixel row according to the decoded data;
the second gate line control sub-circuit includes a second latch and a second decoder connected to each other, the second decoder connecting the pixel groups in the even-numbered pixel rows in the display area, wherein,
the first shift register writing data to the second gate line control sub-circuit includes: the first shift register writes data to the second latch;
the second latch is used for generating the second opening signal after the first shift register writes data into the second latch;
the second decoder is used for decoding the data in the second latch and controlling the opening of the corresponding pixel row according to the decoded data.
8. A display panel comprising the serial peripheral interface circuit according to any one of claims 1 to 7.
9. A driving method applied to the display panel according to claim 8, comprising:
writing data of the first shift register into the first gate line control sub-circuit and the second gate line control sub-circuit based on control of a first clock signal;
controlling the opening of a corresponding pixel row according to data written into a first grid line control sub-circuit by a first shift register, and generating a first opening signal to the shift register group after the pixel row is opened;
controlling the plurality of second shift registers to sequentially generate second clock signals according to a first sequence through the first clock signal and the first opening signal, and outputting the second clock signals to corresponding latches; sequentially writing the data of the first shift register into a plurality of latches of the latch group under the control of the second clock signal, and writing the data in the latches into corresponding pixel groups in the opened pixel rows;
controlling the opening of a corresponding pixel row according to data written into the second grid line control sub-circuit by the first shift register, and generating a second opening signal to the shift register group after the pixel row is opened;
controlling the plurality of second shift registers to sequentially generate second clock signals according to a second sequence through the first clock signal and a second starting signal, and outputting the second clock signals to corresponding latches, wherein the second sequence is different from the first sequence;
and sequentially writing the data of the first shift register into a plurality of latches of the latch group based on the control of the second clock signal, and sequentially writing the data in the latches into corresponding pixel groups in the opened pixel rows.
10. The driving method according to claim 9, wherein the first order is from left to right, and the second order is from right to left; or, the first order is from right to left, and the second order is from left to right.
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