CN108206001B - Shift register, driving method, grid driving device and display device - Google Patents
Shift register, driving method, grid driving device and display device Download PDFInfo
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- CN108206001B CN108206001B CN201810003148.9A CN201810003148A CN108206001B CN 108206001 B CN108206001 B CN 108206001B CN 201810003148 A CN201810003148 A CN 201810003148A CN 108206001 B CN108206001 B CN 108206001B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a shift register, a driving method, a grid driving device and a display device. The shift register comprises an input module, a first voltage module, a second voltage module, an output module, a first node, a second node and a self-reset module. Compared with the prior art that the reset of the shift register depends on the feedback signal of the next-stage shift register, the self-reset module is arranged, the self-reset module has more stable work, saves the wiring space, is beneficial to the design of a narrow frame, and avoids the problems of picture flicker and the like caused by the influence on the reset of the previous-stage shift register when the shift register of a certain stage is abnormal.
Description
Technical Field
The invention relates to the technical field of display panels. And more particularly, to a shift register, a driving method, a gate driving apparatus, and a display apparatus.
Background
The GOA (gate driver On array) circuit realizes the shift register function, when designing the GOA circuit, a reset module is needed to be arranged, the control signal of the existing reset module is provided by the output signal of the next stage shift register, when one stage shift register is abnormal, the previous circuit can not be reset, the display is abnormal, and the bad phenomena such as picture flicker are generated.
Disclosure of Invention
In order to solve at least one of the above technical problems, an aspect of the present invention provides a shift register including an input block, a first voltage block, a second voltage block, an output block, a first node, a second node, and a self reset block;
the first voltage module is used for writing a first level of a first voltage end into a second node;
the input module is used for writing an input signal of a first level from the signal input end into a first node;
the output module outputs a first clock signal from a first clock signal terminal to the signal output terminal in response to a first level of a first node, and outputs a second level of a second voltage terminal to the signal output terminal in response to a first level of a second node;
the self-reset module responds to a control signal of the reset control end and an output signal of the signal output end and outputs a second clock signal from the second clock end to the second voltage module;
the second voltage module writes a second level of the second voltage terminal to the second node in response to the first level of the first node and writes the second level of the second voltage terminal to the first node in response to the second clock signal.
In a preferred embodiment, the first voltage module comprises a first switching element and a second switching element;
the first end and the control end of the first switch element are connected with a first voltage end, the first end of the second switch element is connected with the first voltage end, the second end of the first switch element is connected with the control end of the second switch element, and the second end of the second switch element is connected with a second node;
and/or
The second voltage module includes third to sixth switching elements;
wherein a control terminal of the third switching element is connected to an output terminal of the self-reset module, a control terminal of the fourth switching element is connected to the second node, first terminals of the third and fourth switching elements are connected to the first node, and second terminals thereof are connected to the second voltage terminal;
a first end of the fifth switching element is connected to the control end of the third element, a second end of the fifth switching element is connected to the second voltage end, a first end of the sixth switching element is connected to the second node, a second end of the sixth switching element is connected to the second voltage end, and control ends of the fifth and sixth switching elements are connected to the first node.
In another preferred embodiment, the output module includes a seventh switching element and an eighth switching element;
a first end of the seventh switching element is connected with the first clock signal end, a second end of the seventh switching element is connected with the output end of the output module, and a control end of the seventh switching element is connected with the first node;
the first end of the eighth switching element is connected with the second voltage end, the second end of the eighth switching element is connected with the output end of the output module, and the control end of the eighth switching element is connected with the second node.
In yet another preferred embodiment, the self-reset module includes a ninth switching element and a tenth switching element;
a first end of the ninth switching element is connected with an output end of the output module, a second end of the ninth switching element is connected with a control end of the tenth switching element, and the control end of the ninth switching element is connected with the first voltage end and is written into the first level;
a first end of the tenth switching element is connected with the second clock signal end, and a second end of the tenth switching element is connected with the control end of the third switching element;
alternatively, the first and second electrodes may be,
a first end of the ninth switching element is connected with an output end of the output module, a second end of the ninth switching element is connected with a control end of the tenth switching element, and the control end of the ninth switching element is connected with a first clock signal end and is written with a first clock signal;
a first terminal of the tenth switching element is connected to the second clock signal line, and a second terminal thereof is connected to a control terminal of the third switching element.
In a further preferred embodiment, the shift register further comprises a first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is connected with the signal output end.
In yet another preferred embodiment, the self-reset module includes a second capacitor;
one end of the second capacitor is connected with the control end of the tenth switching element, and the other end of the second capacitor is connected with the second voltage end.
Another aspect of the present invention provides a method of a shift register as in any of the above embodiments, the method comprising:
the first stage is as follows:
the input module writes a first level from a signal input end into a first node;
the second voltage module writes a second level of a second voltage terminal into a second node in response to the first level of the first node;
the output module outputs a first clock signal from a first clock signal terminal to a signal output terminal in response to a first level of a first node;
and a second stage:
the self-reset module responds to a control signal of the reset control end and an output signal of the signal output end and outputs a second clock signal from the second clock end to the second voltage module;
the second voltage module responds to a second clock signal to write a second level of a second voltage end into the first node;
the first voltage module writes a first level of a first voltage end into a second node;
the output module outputs a second level of the second voltage terminal to the signal output terminal in response to the first level of the second node.
In a preferred embodiment, the control signal input by the reset control terminal is a first level from the first voltage terminal or a first clock signal from the first clock signal terminal.
In a further aspect, the present invention provides a gate driving device, which includes a plurality of cascaded shift registers, wherein each stage of shift register is the shift register as described in any one of the above embodiments,
the signal input end of the first stage shift register is connected with the initial signal end, and the signal input ends of all stages of shift registers except the first stage are connected with the signal output end of the shift register of the previous stage.
A further aspect of the invention provides a display device comprising a gate driving device as described in the previous aspect.
The invention has the following beneficial effects:
compared with the prior art that the reset of the shift register depends on the feedback signal of the shift register at the next stage, the self-reset module provided by the invention has the advantages that the work is more stable, the wiring space is saved, the narrow-frame design is facilitated, and the problems of image flicker and the like caused by the influence on the reset of the shift register at the previous stage when the shift register at a certain stage is abnormal are avoided.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a shift register in the prior art.
Fig. 2 shows respective signal timing charts of the shift register shown in fig. 1.
Fig. 3 shows a cascade diagram of the shift register of fig. 1.
FIG. 4 is a circuit diagram of a shift register according to one embodiment of an aspect of the present invention.
FIG. 5 is a timing diagram of signals in a shift register according to an embodiment of an aspect of the present invention.
FIG. 6 is a cascade diagram of a shift register according to one embodiment of an aspect of the present invention.
Fig. 7 shows a circuit schematic of a shift register of another embodiment of an aspect of the present invention.
FIG. 8 shows a circuit schematic of a shift register of an embodiment of another aspect of the invention.
Fig. 9 shows a flowchart of a driving method of the shift register in fig. 8.
Fig. 10 shows a flowchart of a driving method of the shift register in fig. 4.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
Various cross-sectional views in accordance with the disclosed embodiment of the invention are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, unless specified otherwise, the expression "element a is connected to element B" means that element a is connected "directly" or "indirectly" to element B via one or more other elements.
In the existing LCD panel (panel) technology, in order to achieve low cost and narrow frame, most products adopt the goa (gate driver On array) technology, that is, a gate driving device is integrated inside the panel through a thin film transistor process, thereby achieving the advantages of narrow frame and reducing IC and assembly costs. In addition, the Gate driving device is manufactured on the panel by a thin film transistor process, so that the Gate bias time of each thin film transistor in the Gate driving device is mainly considered during design, and the failure of the Gate driving device caused by overlarge threshold voltage shift (Vth shift) is prevented, so that the working life cannot meet the design requirement. Otherwise, the gate driving device is prone to failure and the lifetime of the gate driving device is reduced.
The gate driving device includes a plurality of cascaded shift registers, and the shift registers are used for providing a pulse signal with a certain width to all gate lines row by row in one frame, the time width of the pulse signal is generally one to several times of the charging time allocated to each row, and the waveform of the pulse signal is generally square wave. The source electrode driving device can provide correct video signal voltage for each pixel line by matching with the generation time of the grid line pulse, thereby realizing the normal display of the picture. A single-side driving mode is generally adopted for medium and small-size display products such as mobile phones and tablet computers, a shift register is used for driving corresponding to grid lines of each row, one side drives the grid lines of odd rows, the other side drives the grid lines of even rows, and the two sides are alternately opened. For medium and large size display products, such as Note Book, Monitor, TV, etc., a bilateral driving method is generally adopted, i.e., one line of grid lines is driven by using a left shift register and a right shift register, and the shift registers on the two sides simultaneously output identical pulse signals to the grid lines, so as to reduce the delay time of output.
Fig. 1 shows a circuit schematic of a shift register in the prior art. Fig. 2 shows respective signal timing charts of the shift register shown in fig. 1. Fig. 3 shows a cascade diagram of the shift register of fig. 1.
As shown in the figure, in a general shift register, after the output of the output signal of the current stage is completed, the output signal of the shift register of the next stage is needed, and a pull-Up node (PU node for short) of the shift register of the current stage is Reset (Reset) to prevent the output signal from being output again when the clock signal (CLK) connected to the current line is high again at the subsequent time, so that the pixels corresponding to the current line are mistakenly charged with other data voltages, and the image display is abnormal.
However, this design has a disadvantage that, if a shift register of a certain stage is abnormal and cannot normally output, the previous shift register cannot be reset, and the non-resettable shift register continues to output. Thereby causing poor image flicker, causing excessive current in severe cases, and protecting the module from power failure. In addition, if the reset circuit at the end of the gate driving device malfunctions, the shift registers of the last rows to which the reset signal is supplied by the reset circuit cannot be reset, and thus a display abnormality occurs.
Fig. 4 is a circuit diagram of a shift register according to an embodiment of an aspect of the present invention, as shown in fig. 4, including an input module 1, a first voltage module 2, a second voltage module 3, an output module 5, a first node (pull-up node PU), a second node (pull-down node PD), and a self-reset module 4.
The input module 1 is used for writing an input signal of a first level from a signal input terminal into a first node.
When the shift register is in the first stage, the input module 1 is connected to the start signal end, so that the input signal is the start signal, and when the shift register is in the other stage, the input end of the input module 1 is connected to the signal output end of the output module 5 in the previous stage, so that the input signal is the output signal of the previous stage.
Referring to fig. 4 and 5, the input block 1 writes a high level signal of a start signal or an output signal of a previous stage into the first node. I.e., the timing diagram of the PU in the figure rises to a high level for a first time.
Optionally, the shift register further includes a first capacitor C1, where one end of the first capacitor C1 is connected to the pull-up node PU, and the other end is connected to the signal output terminal. Since the pull-up node PU is connected to one end of the first capacitor C1, when the voltage of the pull-up node PU rises, the first capacitor C1 charges the first capacitor C1 due to the voltage difference between the two ends becoming large.
Alternatively, as shown in fig. 4, the input module 1 may include an eleventh switching element M11, wherein a first terminal and a control terminal of the eleventh switching element M11 are connected to the signal first terminal, and a second terminal thereof is connected to the pull-up node PU.
The first voltage module 2 is used for writing the first level of the first voltage terminal into the second node (also referred to as pull-down node PD).
Optionally, the first voltage module 2 includes a first switching element M1 and a second switching element M2; the first terminal and the control terminal of the first switching element M1 are connected to the first voltage terminal, the first terminal of the second switching element M2 is connected to the first voltage terminal, the second terminal of the first switching element M1 is connected to the control terminal of the second switching element M2, and the second terminal of the second switching element M2 is connected to the second node.
The second voltage module 3 is configured to write a second level of the second voltage terminal to the second node in response to the first level of the first node, and write the second level of the second voltage terminal to the first node in response to the second clock signal.
The second voltage module 3 includes third to sixth switching elements M6; a control end of the third switching element M3 is connected to an output end of the self-reset module 4, a control end of the fourth switching element M4 is connected to the second node, first ends of the third switching element M3 and the fourth switching element M4 are connected to the first node, and second ends of the third switching element M3 and the fourth switching element M4 are connected to the second voltage terminal; a first terminal of the fifth switching element M5 is connected to the control terminal of the second switching element M2, a second terminal thereof is connected to the second voltage terminal, a first terminal of the sixth switching element M6 is connected to the second node, a second terminal thereof is connected to the second voltage terminal, and control terminals of the fifth switching element M5 and the sixth switching element M6 are connected to the first node.
The output module 5 outputs a first clock signal from the first clock signal terminal to the signal output terminal in response to the first level of the first node, and outputs a second dot level of the second voltage terminal to the signal output terminal in response to the first level of the second node.
The output module 5 includes a seventh switching element M7 and an eighth switching element M8;
a first end of the seventh switching element M7 is connected to the first clock signal end, a second end thereof is connected to the output end of the output module 5, and a control end thereof is connected to the first node;
the eighth switching element M8 has a first terminal connected to the second voltage terminal, a second terminal connected to the output terminal of the output module 5, and a control terminal connected to the second node.
In order to turn the pull-up node PU to a low level, thereby turning off the first clock signal (CLK1) and preventing a threshold voltage shift phenomenon from occurring due to a second high level of the first clock signal in one cycle, the self reset block 4 outputs the second clock signal (CLK2) from the second clock terminal to the second voltage block 3 in response to the control signal of the reset control terminal and the output signal of the signal output terminal, thereby enabling the output block 5 to output the second dot level of the second voltage terminal to the signal output terminal at this time in response to the first level of the second node.
Optionally, the second clock signal is opposite in phase to the first clock signal.
Optionally, in an embodiment, the control signal input by the reset control terminal is a first clock signal from a first clock signal terminal.
In this embodiment, the self-reset module 4 includes a ninth switching element M9 and a tenth switching element M10; a first end of the ninth switching element M9 is connected to the output end of the output module 5, a second end thereof is connected to the control end of the tenth switching element M10, and a control end thereof is connected to the first clock signal end; a first terminal of the tenth switching element M10 is connected to the second clock signal terminal, and a second terminal thereof is connected to the control terminal of the third switching element M3.
It should be noted that, in the embodiment of the present invention, the first to tenth switching elements are NMOS transistors, i.e., high-level turn-on transistors. While the NMOS transistor may be a field effect transistor or a bipolar transistor.
The method of driving the shift register provided in the present aspect is discussed below. In conjunction with fig. 9, the method includes:
the first stage is as follows:
s101: the input module writes a first level from the signal input end into a first node;
s102: the output module outputs a first clock signal from a first clock signal terminal to a signal output terminal in response to a first level of a first node;
s103: the second voltage module writes a second level of the second voltage terminal into the second node in response to the first level of the first node;
and a second stage:
s104: the self-reset module responds to a first clock signal of the first clock signal end and an output signal of the signal output end and outputs a second clock signal from the second clock end to the second voltage module;
s105: the second voltage module responds to a second clock signal to write a second level of a second voltage end into the first node;
s106: the first voltage module writes a first level of a first voltage end into a second node;
s107; the output module outputs a second level from the second voltage terminal to the signal output terminal in response to the first level of the second node.
For convenience of explanation, in the embodiment of the present invention, 1/4 cycles are taken as one time period, that is, the first time T1 is the 1 st 1/4 cycle, the second time T2 is the 2 nd 1/4 cycle, and the fourth time T4 is the 4 th 1/4 cycle, and it is specified that the first time T1 and the second time T2 are defined as the first stage, and the third time T3 and the fourth time T4 are defined as the second stage.
Specifically, please refer to fig. 5, which shows a timing diagram of the shift register:
in the first time T1, the input signal is at a high level, the output module 5 can respond to the voltage of the pull-up node PU, and the pull-up node PU turns on the corresponding control terminal, so that the first clock signal is output to the signal output terminal.
During the second time T2, the input signal is low, and the first clock signal output at the first time T1 is a low level signal, so the voltage difference between the two ends of the first capacitor C1 decreases, resulting in discharging the first capacitor C1. During the discharging process of the first capacitor C1, the voltage of the first capacitor C1 rises at the beginning of the discharging process due to the "bootstrap effect", so that the voltage of the pull-up node PU rises again, so that during the discharging process, the pull-up node PU is still at a high level and the voltage is higher than the last time voltage. The first clock signal is still output to the signal output terminal. During the second time T2, the first clock signal is high, and the output signal is high. One terminal of the first capacitor C1 is at a high level, and when the discharging is finished, the voltage difference across the first capacitor C1 should be 0 or close to 0, and therefore, when the first clock signal is turned on, the pull-up node should be consistent with the level signal of the first clock signal.
Since the pull-up node PU is at a high level during the second time T2, the pull-up node PU also serves as a control terminal for the fifth and sixth switching elements M5 and M6, and thus the pull-down node PD is at a low level during the second time T2. At this time, the second voltage block 3 is disconnected from the pull-up node PU.
It is obvious to those skilled in the art that a switching element such as a transistor has a parasitic capacitance, and thus, a "delay time" after the transistor receives a high level can be adjusted according to the magnitude of the parasitic capacitance. Specifically, in the embodiment of the present invention, the parasitic capacitances of the first to ninth switching elements are small, and the delay time is small, and this delay time is set to "0 delay" for convenience of description. The parasitic capacitance value of the tenth switching element M10 is large, so that the tenth switching element M10 has a delay of 1/4 cycles, and when the high level output signal is output during the second time T2, the tenth switching element M10 is charged, so that the tenth switching element M10 is turned on during the third time T3.
In view of this, in this aspect, there is also provided a preferred embodiment of the shift register, and as shown in fig. 7, the self-reset module further includes a second capacitor C2, and the second capacitor C2 is configured such that one end is connected to the gate of the tenth switching element M10, and the other end is connected to the second voltage terminal.
In the preferred embodiment, no additional process is required for the tenth switching element M10, the manufacturing process is reduced, and the delay function in the previous embodiment is also achieved, so that the tenth switching element M10 is turned on during the third time T3.
Due to the above-mentioned "delay" action, the tenth switch element M10 is turned on at the third time T3, the second clock signal is at the high level at the third time T3, so that the self-reset module 4 outputs a high level signal to the second voltage module 3, so that the second voltage module 3 is turned on with the pull-up node PU, so that the high level signal of the pull-up node PU becomes a low level signal, the pull-up node PU is connected with the control terminals of the fifth switch element M5 and the sixth switch element M6, so that the fifth switch element M5 and the sixth switch element M6 are turned off, the pull-down node PD is thus written with a high level through the second switch element M2, the pull-down node PD is connected with the control terminal of the eighth switch element M8 of the output module 5, and when the pull-down node PD is at the high level, the eighth switch element M8 is turned on, and outputs a low level to the output terminal of the output module 5.
At the fourth time T4, the pull-down node PD is at a high level, the fourth switching element M4 is turned on, the pull-up node PU is still at a low level at this time, the seventh switching element M7 is turned off, the eighth switching element M8 is turned on by the pull-down node PD, and the output terminal of the output module 5 outputs a low level signal from the second voltage module 3. Therefore, in the second stage, the output signal of the output module 5 is a low level signal, and the problem that when the first clock signal connected in the current stage is high level in the second stage for the second time, the output signal is a high level signal, which causes the corresponding pixel to be charged with other data voltages by mistake, and causes abnormal pictures is avoided.
Compared with the prior art in which the reset of the shift register depends on the feedback signal of the next shift register, the reset function of the shift register depends on the output signal of the current shift register and the second clock signal as the control signal of the low-voltage module, so that the operation of the shift register is more stable, the wiring space is saved, the narrow-frame design is facilitated, and the problems of image flicker and the like caused by the influence on the reset of the previous shift register when the shift register of a certain stage is abnormal are avoided.
In addition, in another aspect of the present invention, there is also provided an implementation of a shift register, which is different from the shift register provided in the previous aspect in that the control signal input by the reset control terminal is a high level signal from the first voltage terminal, that is, as shown in fig. 8, the first terminal of the ninth switching element M9 is connected to the first voltage terminal.
Compared to the previous embodiment in which the control signal input from the reset control terminal is the first clock signal from the first clock signal terminal, the shift register of the present embodiment uses the first level of the first voltage terminal as the control signal of the ninth switching element M9, which has the advantage of reducing the load of the first clock signal, so that the power consumption is reduced. This has the disadvantage that the time for the ninth switching element M9 to be high is increased, thus causing the bias time to be increased and the Vth drift to be increased.
Further, in the present aspect, there is also provided a driving method corresponding to the shift register in the embodiment of the present aspect, and specifically, as shown in fig. 10, differently from the driving method in the above aspect, the self reset block 4 outputs the second clock signal from the second clock terminal to the second voltage block 3 in response to the high level signal from the first voltage terminal and the output signal of the signal output terminal.
In addition, in another aspect of the present invention, there is provided a gate driving device, comprising a plurality of cascaded shift registers, wherein each stage of the shift register is the shift register of any one of the above embodiments,
the signal input end of the first stage shift register is connected with the initial signal end, and the signal input ends of all stages of shift registers except the first stage are connected with the signal output end of the shift register of the previous stage.
Specifically, in the gate driving device having m stages of shift registers, the signal input terminal of the 1 st stage of shift register is connected to the start signal terminal. The signal output terminal of the ith stage (i is greater than 1 and less than m) shift register is connected to the signal input terminal of the (i +1) th stage shift register, and the output signal OUT (i) thereof is used as the input signal IN (i +1) of the (i +1) th stage shift register. The output signal of the m-th stage shift register is OUT (m), and the next stage is not output to the shift register any more.
In addition, in another aspect of the present invention, the present invention provides a display device, which is a product having any display function, such as a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, and a navigator, including the above gate driving device.
The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or may alternatively include other gas steps or elements inherent to such process, method, or apparatus.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (10)
1. A shift register is characterized by comprising an input module, a first voltage module, a second voltage module, an output module, a first node, a second node and a self-reset module;
the first voltage module is used for writing a first level of a first voltage end into a second node;
the input module is used for writing an input signal of a first level from the signal input end into a first node;
the output module outputs a first clock signal from a first clock signal terminal to the signal output terminal in response to a first level of a first node, and outputs a second level of a second voltage terminal to the signal output terminal in response to a first level of a second node;
the self-reset module responds to a control signal of a reset control end and an output signal of a signal output end and outputs a second clock signal from a second clock end to a second voltage module, wherein the control signal input by the reset control end is a first level from the first voltage end or a first clock signal of the first clock signal end;
the second voltage module writes a second level of the second voltage terminal to the second node in response to the first level of the first node and writes the second level of the second voltage terminal to the first node in response to the second clock signal.
2. The shift register of claim 1,
the first voltage module comprises a first switching element and a second switching element;
the first end and the control end of the first switch element are connected with a first voltage end, the first end of the second switch element is connected with the first voltage end, the second end of the first switch element is connected with the control end of the second switch element, and the second end of the second switch element is connected with a second node;
and/or
The first voltage module includes a first switching element and a second switching element, and the second voltage module includes third to sixth switching elements;
wherein a control terminal of the third switching element is connected to an output terminal of the self-reset module, a control terminal of the fourth switching element is connected to the second node, first terminals of the third and fourth switching elements are connected to the first node, and second terminals thereof are connected to the second voltage terminal;
a first terminal of the fifth switching element is connected to the control terminal of the second switching element, a second terminal thereof is connected to the second voltage terminal, a first terminal of the sixth switching element is connected to the second node, a second terminal thereof is connected to the second voltage terminal, and control terminals of the fifth and sixth switching elements are connected to the first node.
3. The shift register according to claim 1, wherein the output module includes a seventh switching element and an eighth switching element;
a first end of the seventh switching element is connected with the first clock signal end, a second end of the seventh switching element is connected with the output end of the output module, and a control end of the seventh switching element is connected with the first node;
the first end of the eighth switching element is connected with the second voltage end, the second end of the eighth switching element is connected with the output end of the output module, and the control end of the eighth switching element is connected with the second node.
4. The shift register according to claim 2, wherein the self reset module includes a ninth switching element and a tenth switching element;
a first end of the ninth switching element is connected with an output end of the output module, a second end of the ninth switching element is connected with a control end of the tenth switching element, and the control end of the ninth switching element is connected with the first voltage end and is written into the first level;
a first end of the tenth switching element is connected with the second clock signal end, and a second end of the tenth switching element is connected with the control end of the third switching element;
alternatively, the first and second electrodes may be,
a first end of the ninth switching element is connected with an output end of the output module, a second end of the ninth switching element is connected with a control end of the tenth switching element, and the control end of the ninth switching element is connected with a first clock signal end and is written with a first clock signal;
a first terminal of the tenth switching element is connected to the second clock signal line, and a second terminal thereof is connected to a control terminal of the third switching element.
5. The shift register of claim 1,
the shift register also comprises a first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is connected with the signal output end.
6. The shift register according to claim 4,
the self-reset module comprises a second capacitor;
one end of the second capacitor is connected with the control end of the tenth switching element, and the other end of the second capacitor is connected with the second voltage end.
7. A method of driving a shift register according to any one of claims 1 to 6, the method comprising:
the first stage is as follows:
the input module writes a first level from the signal input end into a first node;
the second voltage module writes a second level of a second voltage terminal into a second node in response to the first level of the first node;
the output module outputs a first clock signal from a first clock signal terminal to a signal output terminal in response to a first level of a first node;
and a second stage:
the self-reset module responds to a control signal of the reset control end and an output signal of the signal output end and outputs a second clock signal from the second clock end to the second voltage module;
the second voltage module responds to a second clock signal to write a second level of a second voltage end into the first node;
the first voltage module writes a first level of a first voltage end into a second node;
the output module outputs a second level of the second voltage terminal to the signal output terminal in response to the first level of the second node.
8. The method of claim 7, wherein the control signal inputted from the reset control terminal is a first level from the first voltage terminal or a first clock signal from the first clock signal terminal.
9. A gate driving device comprising a plurality of cascaded shift registers, wherein each shift register stage is a shift register according to any one of claims 1 to 6,
the signal input end of the first stage shift register is connected with the initial signal end, and the signal input ends of all stages of shift registers except the first stage are connected with the signal output end of the shift register of the previous stage.
10. A display device comprising the gate driving device according to claim 9.
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| CN109166542A (en) | 2018-09-26 | 2019-01-08 | 合肥鑫晟光电科技有限公司 | Shift register cell and driving method, gate driving circuit, display device |
| CN109817182B (en) * | 2019-04-10 | 2021-04-23 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN109872675B (en) * | 2019-04-22 | 2021-03-02 | 京东方科技集团股份有限公司 | Serial peripheral interface circuit, display panel and driving method |
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