CN109872675A - A kind of Serial Peripheral Interface (SPI) circuit, display panel and driving method - Google Patents
A kind of Serial Peripheral Interface (SPI) circuit, display panel and driving method Download PDFInfo
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- CN109872675A CN109872675A CN201910324123.3A CN201910324123A CN109872675A CN 109872675 A CN109872675 A CN 109872675A CN 201910324123 A CN201910324123 A CN 201910324123A CN 109872675 A CN109872675 A CN 109872675A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
This application discloses a kind of Serial Peripheral Interface (SPI) circuit, display panel and driving methods.The Serial Peripheral Interface (SPI) circuit provides two groups of grid lines and controls sub-circuit, realizes write data into pixel group from different directions respectively.Scheme provided in this embodiment improves display quality so that carryover effects are offset by the pixel group that different order writes data into pixel column.
Description
Technical field
This application involves display technology, espespecially a kind of Serial Peripheral Interface (SPI) circuit, display panel and driving method.
Background technique
Current wearable product increased popularity, for the not high product of resolution ratio, to improve the compatibility with system, generally
Using SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) circuit.SPI circuit is made in display panel
Upper (for example being made by LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon) technique), can save IC
(Integrated Circuit, integrated circuit) cost improves system compatibility, reduces frame, is widely adopted at present.It is related
The display panel for being integrated with SPI circuit in technology, which exists, shows uneven problem, it is necessary to improve.
Summary of the invention
A present invention at least embodiment provides a kind of Serial Peripheral Interface (SPI) circuit, display panel and driving method, improves
Display quality.
In order to reach the object of the invention, a present invention at least embodiment provides a kind of Serial Peripheral Interface (SPI) circuit, comprising:
First grid line traffic control sub-circuit, second gate line traffic control sub-circuit, the first shift register, including multiple second shift registers
Shift register group, the latch group including multiple latch, wherein the first grid line traffic control sub-circuit connects display area
Pixel group in middle part pixel column, the second gate line traffic control sub-circuit connect the pixel in display area in rest of pixels row
Group, the latch and second shift register correspond, and the pixel group of the latch and pixel column corresponds,
Wherein:
The first grid line traffic control sub-circuit is used for, and controls corresponding pixel according to the data of the first shift register write-in
Capable unlatching, and after opening pixel column, it generates the first open signal to the shift register group and opens the shift LD
Device group；
The second gate line traffic control sub-circuit is used for, and controls corresponding pixel according to the data of the first shift register write-in
Capable unlatching, and after opening pixel column, it generates the second open signal to the shift register group and opens the shift LD
Device group；
The shift register group is used for, and under the control of the first clock signal and the first open signal, is controlled described more
A second shift register is sequentially generated second clock signal by the first sequence, is output to corresponding latch；And described
Under the control of first clock signal and the second open signal, controls the multiple second shift register and successively produced by the second sequence
Raw second clock signal, is output to corresponding latch, wherein second sequence is different from the first sequence；
First shift register is used for, and under the control of the first clock signal, writes data into first grid line traffic control system
Circuit and second gate line traffic control sub-circuit, and, under the control of second clock signal, successively write data into the latch
Multiple latch of group；
The latch group is used for, and under the control of second clock signal, has successively been opened the data write-in in latch
Corresponding pixel group in the pixel column opened.
In one embodiment, the first grid line traffic control sub-circuit includes connected the first latch and the first decoder,
First decoder connects the pixel group in the display area in the pixel column of part；
It includes: first shift register that first shift register, which writes data into first grid line traffic control sub-circuit,
Write data into first latch；
First latch is used for, and after first shift register writes data into first latch, is produced
Raw first open signal；
First decoder is used for, and decodes the data in first latch, according to data decoded control pair
The unlatching for the pixel column answered.
In one embodiment, the second gate line traffic control sub-circuit includes the second latch being connected with each other and the second decoding
Device, second decoder connect the pixel group in display area in rest of pixels row, wherein
It includes: first shift register that first shift register, which writes data into second gate line traffic control sub-circuit,
Write data into second latch；
Second latch is used for, and after first shift register writes data into second latch, is produced
Raw second open signal；
Second decoder is used for, and decodes the data in second latch, according to data decoded control pair
The unlatching for the pixel column answered.
In one embodiment, first sequence is that from left to right, second sequence is from right to left；Alternatively, described
First sequence is that from right to left, second sequence is from left to right.
In one embodiment, the pixel group in first grid line traffic control sub-circuit connection display area in the pixel column of part
Are as follows: the pixel group in first grid line traffic control sub-circuit connection display area in odd number pixel rows；
Pixel group in second gate line traffic control sub-circuit connection display area in rest of pixels row are as follows: the second gate
Line traffic control sub-circuit connects the pixel group in display area in even pixel row.
In one embodiment, the Serial Peripheral Interface (SPI) circuit further includes mode latch, first shift register
It is also used to, under the control of the first clock signal, is writing data into first grid line traffic control sub-circuit or second gate line traffic control system electricity
Lu Qian writes data into the mode latch.
In one embodiment, the Serial Peripheral Interface (SPI) circuit further includes mode latch, first shift register
It is also used to, under the control of the first clock signal, is writing data into first grid line traffic control sub-circuit or second gate line traffic control system electricity
Lu Qian writes data into the mode latch；
The first grid line traffic control sub-circuit includes connected the first latch and the first decoder, first decoder
Connect the pixel group in the display area in odd number pixel rows；
It includes: first shift register that first shift register, which writes data into first grid line traffic control sub-circuit,
Write data into first latch；
First latch is used for, and after first shift register writes data into first latch, is produced
Raw first open signal；
First decoder is used for, and decodes the data in first latch, according to data decoded control pair
The unlatching for the pixel column answered；
The second gate line traffic control sub-circuit includes the second latch and the second decoder being connected with each other, second solution
Pixel group in code device connection display area in even pixel row, wherein
It includes: first shift register that first shift register, which writes data into second gate line traffic control sub-circuit,
Write data into second latch；
Second latch is used for, and after first shift register writes data into second latch, is produced
Raw second open signal；
Second decoder is used for, and decodes the data in second latch, according to data decoded control pair
The unlatching for the pixel column answered.
One embodiment of the invention provides a kind of display panel, including Serial Peripheral Interface (SPI) circuit described in any embodiment.
One embodiment of the invention provides a kind of driving method, applied to display panel described in any embodiment, comprising:
Based on the control of the first clock signal, by the data write-in first grid line traffic control sub-circuit of the first shift register and
Second gate line traffic control sub-circuit；
The unlatching of corresponding pixel column is controlled according to the data that first grid line traffic control sub-circuit is written in the first shift register,
And after opening pixel column, the first open signal is generated to the shift register group；
It is suitable by first that the multiple second shift register is controlled by first clock signal and the first open signal
Sequence is sequentially generated second clock signal, is output to corresponding latch；By the control of the second clock signal successively by institute
Multiple latch of the latch group are written in the data for stating the first shift register, and, the data in latch are written
Corresponding pixel group in the pixel column having turned on；
The unlatching of corresponding pixel column is controlled according to the data that second gate line traffic control sub-circuit is written in the first shift register,
And after opening pixel column, the second open signal is generated to the shift register group；
It is suitable by second that the multiple second shift register is controlled by first clock signal and the second open signal
Sequence is sequentially generated second clock signal, is output to corresponding latch, wherein it is suitable that second sequence is different from described first
Sequence；
Successively the latch is written in the data of first shift register by the control based on the second clock signal
Multiple latch of device group, and, corresponding pixel group in the pixel column for successively having turned on the data write-in in latch.
In one embodiment, first sequence is that from left to right, second sequence is from right to left；Alternatively, described
First sequence is that from right to left, second sequence is from left to right.
Compared with the relevant technologies, one embodiment of the invention includes a kind of Serial Peripheral Interface (SPI) circuit, which includes first
Grid line controls sub-circuit, second gate line traffic control sub-circuit, the first shift register, the displacement including multiple second shift registers
Register group, the latch group including multiple latch write data into the pixel group in different pixels row by different order,
So that carryover effects are offset, display quality is improved.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is a kind of SPI circuit schematic diagram provided in the related technology；
Fig. 2 is a kind of SPI circuit schematic diagram that one embodiment of the invention provides；
Fig. 3 be another embodiment of the present invention provides a kind of SPI circuit schematic diagram；
Fig. 4 be another embodiment of the present invention provides a kind of SPI circuit schematic diagram；
Fig. 5 be another embodiment of the present invention provides a kind of SPI circuit schematic diagram；
Fig. 6 be another embodiment of the present invention provides a kind of SPI circuit schematic diagram；
Fig. 7 is the display panel schematic diagram that one embodiment of the invention provides；
Fig. 8 is the driving method flow chart that one embodiment of the invention provides；
Fig. 9 is the SPI circuit schematic diagram that a specific example of the invention provides；
Figure 10 is the time diagram that one embodiment of the invention provides.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
Unless otherwise defined, the technical term or scientific term that the disclosure uses should be tool in fields of the present invention
The ordinary meaning for thering is the personage of general technical ability to be understood." first ", " second " used in the disclosure and similar word are simultaneously
Any sequence, quantity or importance are not indicated, and are used only to distinguish different component parts." comprising " or "comprising" etc.
Similar word means that the element or object before the word occur covers the element or object for appearing in the word presented hereinafter
And its it is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " is not limited to physics
Or mechanical connection, but may include electrical connection, it is either direct or indirectly."upper", "lower",
"left", "right" etc. is only used for indicating relative positional relationship, and after the absolute position for being described object changes, then the relative position is closed
System may also correspondingly change.
It is illustrated by taking resolution ratio 176*3*176 as an example, Fig. 1 is SPI circuit schematic diagram in the related technology.In related skill
In the SPI circuit that art provides, as shown in Figure 1, SI is sequentially written in 12-bit Shift Register under SCLK control and locks
It deposits, 6bit Mode is first written in data in 12-bit Shift Register, and 8bit Vdriver is written later, finally exists
Under 44bit shift register (Hdriver Shift Register1~Hdriver Shift Register44) control, successively
It is written in 44 12bit LAT (Hdriver 12-bit LAT1~Hdriver 12-bit LAT44).In circuit
Vdriver generates the STV signal of 44bit shift register, and under SCLK control, 44Bit shift register is from left to right successively
44 clock signals are generated, control 12Bit LAT, the data in 44 12Bit LAT are under 44 clock controls, from left to right
It being sequentially written in 12 sub-pixels corresponding to 4 pixels, P1~P4 first write-in, P173~P176 is ultimately written, due to
RC Delay (RC delay), there may be undercharges by P173~P176, and are unable to displaying target grayscale.With regard to entire panel
Speech, left side charging is sufficient, right side undercharge, shows so as to cause left and right sides uneven.The pixel number of SPI circuit in the related technology
According to being that the data for latching Hdriver 12bit LAT module are written in 4 pixels, in Hdriver Shift Register
It is sequentially written in from left to right under (shift register) control, P173~P176 pixel is ultimately written, since transmission delay may
Lead to undercharge, is unable to displaying target grayscale.
Fig. 2 is the SPI circuit schematic diagram that one embodiment of the invention provides.As shown in Figure 2, comprising: first grid line traffic control system
Circuit 21, second gate line traffic control sub-circuit 22, the first shift register 23 including multiple second shift registers (241~24N)
Shift register group 24 including multiple latch (251~25N) latch group 25, wherein the first grid line traffic control system
Circuit 21 connects the pixel group in display area in the pixel column of part, and the second gate line traffic control sub-circuit 22 connects display area
Pixel group in middle rest of pixels row, pixel column include G1 to GN, each pixel column includes M pixel group (pixel group 1 to pixel
Group M), each pixel group includes one or more pixels, for example including 4 pixels, the latch is posted with second displacement
Storage corresponds (the second shift register 24iThe pixel group of corresponding latch i), the latch and pixel column corresponds
(for example, 1 respective pixel group 1 of latch, 2 respective pixel group 2 of latch, etc.), it should be noted that shown in Figure 2 to be
First grid line traffic control sub-circuit 21 connects the pixel group of the pixel column of odd-numbered line, and second gate line traffic control sub-circuit 22 connects even number line
Pixel column pixel group, i.e., interconnection is carried out with uniline, but the application is without being limited thereto, can also carry out with 2 behavior units
Interconnection, i.e., 1,2,5,6,9,10 ... wait the pixel group of pixel columns to connect first grid line traffic control sub-circuit, 3,4,7,8 ... iseikonias
The pixel group of plain row connects second gate line traffic control sub-circuit 22, alternatively, unbalanced can also be spaced, for example, pixel column 1,2,4,
5,7,8 equal connection first grid line traffic control sub-circuits 21, pixel column 3,6 wait connection second gate line traffic control sub-circuit 22, etc.,
In:
The first grid line traffic control sub-circuit 21 is used for, corresponding according to the data control of the first shift register 23 write-in
The unlatching of pixel column, and after opening pixel column, the first open signal L_STV is generated to the shift register group 24 unlatching institute
State shift register group 24；
The second gate line traffic control sub-circuit 22 is used for, corresponding according to the data control of the first shift register 23 write-in
The unlatching of pixel column, and after opening pixel column, the second open signal R_STV is generated to the shift register group 24 unlatching institute
State shift register group 24；
The shift register group 24 is used for, under the control of the first clock signal SCLK and the first open signal L_STV,
It controls the multiple second shift register and is sequentially generated second clock signal by the first sequence, be output to corresponding latch
(for example, the second shift register 241The second clock signal of generation is output to latch 251, the second shift register 242It generates
Second clock signal be output to latch 252；And in the first clock signal SCLK and the second open signal R_STV
Control under, control the multiple second shift register by the second sequence and be sequentially generated second clock signal, be output to correspondence
Latch, wherein second sequence be different from first sequence；It is that from left to right, the second sequence is from the right side with the first sequence
To for a left side, under the control of the first clock signal SCLK and the first open signal L_STV, the second shift register 241To 24M
It is sequentially generated second clock signal；Under the control of the first clock signal SCLK and the second open signal R_STV, the second displacement is posted
Storage 24MTo 241It is sequentially generated second clock signal.
First shift register 23 is used for, and under the first clock signal SCLK control, writes data into the first grid line
Sub-circuit 21 and second gate line traffic control sub-circuit 22 are controlled, and, under the control of second clock signal, successively write data into
Multiple latch of the latch group；Wherein, first grid line traffic control sub-circuit 21 and second gate line traffic control system are write data into
Circuit 22 can be intersection write-in, i.e., first write data into first grid line traffic control sub-circuit 21, then write data into second gate
Then line traffic control sub-circuit writes data into first grid line traffic control sub-circuit 21 again, and so on.It is of course also possible to according to picture
The refresh sequence of plain row writes data into first grid line traffic control sub-circuit 21 and second gate line traffic control sub-circuit 22, etc..Refresh
Sequence can be refreshing or other modes line by line.
The latch group 25 is used for, under the control of second clock signal, successively by the data write-in in latch
Corresponding pixel group in the pixel column of unlatching.For example, pixel column G1When unlatching, picture is written in the data in the latch of latch group
Plain row G1Pixel group 1 to pixel group M.When the second clock signal in latch group is sequentially generated by the first sequence, then press
First sequence writes data into pixel group 1 to pixel group M, when the second clock signal in latch group is successively given birth to by the second sequence
Cheng Shi then writes data into pixel group 1 to pixel group M by the second sequence.For example, when the first sequence is from left to right, pixel group 1
It is written at first, pixel group M is ultimately written, and when the second sequence is from right to left, pixel group M is written at first, and pixel group 1 is finally write
Enter.
SPI circuit provided in this embodiment writes data into the pixel group in pixel column by different order, so that
Carryover effects are offset, and display quality is improved.
In one embodiment, as shown in figure 3, the first grid line traffic control sub-circuit includes the first connected latch 211
With the first decoder 212, first decoder 212 connects the pixel group in the display area in the pixel column of part；
It includes: that first displacement is posted that first shift register 23, which writes data into first grid line traffic control sub-circuit 21,
Storage 23 writes data into first latch 211；
First latch 211 is used for, and writes data into first latch in first shift register 23
After 211, first open signal is generated；
First decoder 212 is used for, and the data in first latch 211 is decoded, according to data decoded
Control the unlatching of the pixel column of its connection.
In one embodiment, as shown in figure 4, the second gate line traffic control sub-circuit 22 includes that second to be connected with each other is latched
Device 221 and the second decoder 222, second decoder 222 connect the pixel group in display area in rest of pixels row,
In,
It includes: that first displacement is posted that first shift register 23, which writes data into second gate line traffic control sub-circuit 22,
Storage 23 writes data into second latch 221；
Second latch 221 is used for, and writes data into second latch in first shift register 23
After 221, second open signal is generated；
Second decoder 222 is used for, and the data in second latch 221 is decoded, according to data decoded
Control the unlatching of corresponding pixel column.
In one embodiment, first sequence is that from left to right, second sequence is from right to left；Alternatively, described
First sequence is that from right to left, second sequence is from left to right.
In one embodiment, as shown in figs. 2 to 4, the first grid line traffic control sub-circuit 21 connects part in display area
Pixel group in pixel column are as follows: the first grid line traffic control sub-circuit 21 connects the pixel in display area in odd number pixel rows
Group；
The second gate line traffic control sub-circuit 22 connects the pixel group in display area in rest of pixels row are as follows: described second
Grid line controls the pixel group in the connection of sub-circuit 22 display area in even pixel row.In the embodiment, intersected by parity rows
Driving, the one direction transmission of odd-line pixels data, even number of lines are transmitted according to from another direction, and parity rows carryover effects are mutual
It offsets, to improve display quality.It should be noted that the connection type is merely illustrative.It can be other connection types.
In one embodiment, as shown in figure 5, the Serial Peripheral Interface (SPI) circuit further includes mode latch 26, described
One shift register 23 is also used to, the first clock signal control under, write data into first grid line traffic control sub-circuit 21 or
Before second gate line traffic control sub-circuit 22, the mode latch 26 is write data into.
In one embodiment, as shown in fig. 6, the Serial Peripheral Interface (SPI) circuit further includes mode latch 26, described
One shift register 23 is also used to, the first clock signal control under, write data into first grid line traffic control sub-circuit 21 or
Before second gate line traffic control sub-circuit 22, the mode latch 26 is write data into；
The first grid line traffic control sub-circuit 21 includes the first latch 211 and the first decoder 212 being connected with each other, institute
It states the first decoder 212 and connects pixel group in the display area in odd number pixel rows；The second gate line traffic control sub-circuit
22 include the second latch 221 and the second decoder 222 being connected with each other, and second decoder 222 connects in display area
Pixel group in even pixel row, wherein
First shift register 23 writes data into first latch 211 and the second latch 221；It needs
It is bright, the first latch 211 is at a time write data into referred to herein as the first shift register 23, another moment will count
According to the second latch 221 of write-in, for example, can be by the way of intersecting write-in, it can also be according to the refresh sequence to pixel column
Data are respectively written into the first latch 211 and the second latch 221, etc..
First latch 211 is used for, and writes data into first latch in first shift register 23
After 211, first open signal is generated；
First decoder 212 is used for, and the data in first latch 211 is decoded, according to data decoded
Control the unlatching of corresponding pixel column；
Second latch 221 is used for, and writes data into second latch in first shift register 23
After 221, second open signal is generated；
Second decoder 222 is used for, and the data in second latch 221 is decoded, according to the decoded number
According to the unlatching for controlling corresponding pixel column.
According to same inventive concept, as shown in fig. 7, one embodiment of the invention provides a kind of display panel 70, including any
Serial Peripheral Interface (SPI) circuit 71 described in embodiment.Display panel provided in this embodiment carries out pixel column by different order
Write-in, the carryover effects of different pixels row can be offset, and display quality is improved.
One embodiment of the invention provides a kind of driving method, as shown in figure 8, being applied to the display panel, comprising:
Step 801, the data of the first shift register are written by first grid line traffic control sub-circuit based on the first clock signal
With second gate line traffic control sub-circuit；
Step 802, corresponding pixel is controlled according to the data that first grid line traffic control sub-circuit is written in the first shift register
Capable unlatching, and after opening pixel column, the first open signal is generated to the shift register group；
Step 803, the multiple second shift register is controlled by first clock signal and the first open signal
It is sequentially generated second clock signal by the first sequence, is output to corresponding latch；Pass through the control of the second clock signal
The data of first shift register are successively written to multiple latch of the latch group, and, it will be in latch
Corresponding pixel group in the pixel column that data write-in has turned on；
Step 804, corresponding pixel is controlled according to the data that second gate line traffic control sub-circuit is written in the first shift register
Capable unlatching, and after opening pixel column, the second open signal is generated to the shift register group；
Step 805, the multiple second shift register is controlled by first clock signal and the second open signal
It is sequentially generated second clock signal by the second sequence, is output to corresponding latch, wherein second sequence is different from described
First sequence；
Step 806, successively the data of first shift register are written for the control based on the second clock signal
Multiple latch of the latch group, and, it is corresponding in the pixel column for successively having turned on the data write-in in latch
Pixel group.
Driving method provided in this embodiment is sequentially written in the data of different pixels row from difference, so that carryover effects go out
It now offsets, improves display quality.
In one embodiment, first sequence is that from left to right, second sequence is from right to left；Alternatively, described
First sequence is that from right to left, second sequence is from left to right.
Below by a specific example, the invention will be further described.It is carried out so that resolution ratio is 176*3*176 as an example
Illustrate, Fig. 9 is the SPI circuit schematic diagram that one embodiment of the invention provides.As shown in figure 9, in the present embodiment, 12-bit Shift
Register1 is the first shift register, and it includes 44 shiftings in shift register group that Mode 6-bit LAT, which is mode register,
Bit register (Hdriver Shift Register 1~Hdriver Shift Register 44), the Vdriver in left side
8bit LAT1 is the first latch, and the Vdriver Decoder1 in left side is the first decoder, the Vdriver 8bit on right side
LAT2 is the second latch, and the Vdriver Decoder2 on right side is the second decoder, and latch group includes 44 latch
(Hdriver 12-bit LAT1~Hdriver 12-bit LAT44).Pixel column G1~G176, every row include 44 pixels
Group, each pixel group include 4 pixels.For example, pixel P1~P4 constitutes pixel group 1, pixel P5~P8 constitutes pixel group 2, as
Plain P169~P172 constitutes pixel group 43, and pixel P173~P176 constitutes pixel group 44.
Illustratively pixel writing process in the embodiment below.
SI is sequentially written in 12-bit Shift Register under SCLK (clock signal) control and latches, 12-bit
Mode 6bit LAT is first written in data in Shift Register1, later the Vdriver 8-bit LAT1 lock in write-in left side
It deposits, the data that left side Vdriver 8-bit LAT1 is latched are decoded by the Vdriver Decoder1 in left side, open grid line G1 institute
Each pixel group of connection, Vdriver 8-bit LAT1 issue L-STV signal to Hdriver Shift Register 1, open
Hdriver Shift Register 1, under SCLK control, Hdriver Shift Register1~Hdriver Shift
Register44 is sequentially generated 44 clock signals, and the data controlled in 12-bit Shift Register1 are sequentially written in 44
In 12bit LAT (Hdriver 12-bit LAT1~Hdriver 12-bit LAT44).Data in 44 12Bit LAT
Under 44 clock controls, it is sequentially written in 12 sub-pixels corresponding to 4 pixels of pixel column G1 from left to right, P1~P4
First write-in, P173~P176 are ultimately written；
The Vdriver 8-bit LAT2 on the data write-in right side in 12-bit Shift Register1 later, right side
The data that Vdriver 8-bit LAT2 is latched are decoded by the Vdriver Decoder2 on right side, and unlatching grid line G2 is connected each
Pixel group, Vdriver 8-bit LAT2 issue R-STV signal to Hdriver Shift Register 44, open Hdriver
Shift Register 44, under SCLK control, Hdriver Shift Register44~Hdriver Shift
Register1 is sequentially generated 44 clock signals, and the data controlled in 12-bit Shift Register1 are sequentially written in 44
In 12bit LAT (Hdriver 12-bit LAT44~Hdriver 12-bit LAT1).Data in 44 12Bit LAT
Under 44 clock controls, it is sequentially written in 12 sub-pixels corresponding to 4 pixels of pixel column G2 from right to left, P1~P4
First write-in, P173~P176 are ultimately written；
Other each pixel columns are similar, that is, odd-numbered line drives shift register group to generate 44 clock letters from left to right
Number, respective pixel is sequentially written in from left to right, generate 44 clock signals from right to left when even number line drives, respective pixel from
Right-to-left is sequentially written in.
Scheme provided in this embodiment designs two groups of Vdriver 8bit LAT and two groups of Vdriver Decoder, corresponding
Gate parity rows cross-drive, and generate two groups of STV signals and drive 44bit shift register group.44bit when odd-numbered line drives
Shift register group generates 44 clock signals from left to right, and respective pixel is sequentially written in from left to right, and when even number line generates
44 clock signals from right to left, respective pixel are sequentially written in from right to left, so that left side charging is sufficient, right when odd-numbered line
Side undercharge, when even number line, right side charging is sufficient, and left side undercharge, parity rows carryover effects offset each other, improve aobvious
Show quality.
Figure 10 is data transmission time sequence schematic diagram.As shown in Figure 10, wherein SI is data line, and SCLK is clock line, SCS
For chip selection signal.SI successively transmits 6bit Mode data (being transferred to Mode 6bit LAT), 10bit V-driver (wherein
2bit redundancy) data (being transferred to Vdriver 8bit LAT), H-driver data (be transferred to Hdriver 12bit LAT1~
Hdriver 12bit LAT44), there is 16CLK (16 clock cycle) as dummy for carrying out data transmission later.
SPI circuit provided in this embodiment can be used as the interface circuit of display panel, save IC cost, and it is competing to improve product
Strive power.
The embodiment of the present invention proposes a kind of novel SPI circuit, can be used for improving available circuit since transmission delay causes
Display unevenness problem, improve display quality.The pixel data of SPI circuit is by Hdriver 12bit LAT in the related technology
The data that module latches are written in 4 pixels, are sequentially written in from left to right under Hdriver Shift Register control,
The pixel of rightmost is ultimately written, and since transmission delay may result in undercharge, is unable to displaying target grayscale.The present embodiment
In, by parity rows cross-drive, odd-line pixels data are transmitted from left to right, and even rows data are transmitted from right to left,
Parity rows carryover effects offset each other, to improve display quality.
There is the following to need to illustrate:
(1) attached drawing of the embodiment of the present invention is related only to the present embodiments relate to the structure arrived, and other structures can refer to
It is commonly designed.
(2) in the absence of conflict, the feature in the embodiment of the present invention and embodiment can be combined with each other to obtain
New embodiment.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of Serial Peripheral Interface (SPI) circuit, comprising: first grid line traffic control sub-circuit, second gate line traffic control sub-circuit, first move
Bit register, the shift register group including multiple second shift registers, the latch group including multiple latch, wherein
Pixel group in first grid line traffic control sub-circuit connection display area in the pixel column of part, the second gate line traffic control system electricity
Road connects the pixel group in display area in rest of pixels row, and the latch and second shift register correspond,
The pixel group of the latch and pixel column corresponds, in which:
The first grid line traffic control sub-circuit is used for, and controls corresponding pixel column according to the data that the first shift register is written
It opens, and after opening pixel column, generates the first open signal to the shift register group and open the shift register group；
The second gate line traffic control sub-circuit is used for, and controls corresponding pixel column according to the data that the first shift register is written
It opens, and after opening pixel column, generates the second open signal to the shift register group and open the shift register group；
The shift register group is used for, and under the control of the first clock signal and the first open signal, controls the multiple the
Two shift registers are sequentially generated second clock signal by the first sequence, are output to corresponding latch；And described first
Under the control of clock signal and the second open signal, the multiple second shift register is controlled by the second sequence and is sequentially generated the
Two clock signals are output to corresponding latch, wherein second sequence is different from the first sequence；
First shift register is used for, and under the control of the first clock signal, writes data into first grid line traffic control sub-circuit
With second gate line traffic control sub-circuit, and, under the control of second clock signal, successively write data into the latch group
Multiple latch；
The latch group is used for, and under the control of second clock signal, is successively had turned on the data write-in in latch
Corresponding pixel group in pixel column.
2. Serial Peripheral Interface (SPI) circuit according to claim 1, which is characterized in that the first grid line traffic control sub-circuit packet
Connected the first latch and the first decoder are included, first decoder connects in the display area in the pixel column of part
Pixel group；
It includes: that first shift register will count that first shift register, which writes data into first grid line traffic control sub-circuit,
According to write-in first latch；
First latch is used for, and after first shift register writes data into first latch, generates institute
State the first open signal；
First decoder is used for, and decodes the data in first latch, is controlled according to data decoded corresponding
The unlatching of pixel column.
3. Serial Peripheral Interface (SPI) circuit according to claim 1, which is characterized in that the second gate line traffic control sub-circuit packet
The second latch and the second decoder being connected with each other are included, in the second decoder connection display area in rest of pixels row
Pixel group, wherein
It includes: that first shift register will count that first shift register, which writes data into second gate line traffic control sub-circuit,
According to write-in second latch；
Second latch is used for, and after first shift register writes data into second latch, generates institute
State the second open signal；
Second decoder is used for, and decodes the data in second latch, is controlled according to data decoded corresponding
The unlatching of pixel column.
4. Serial Peripheral Interface (SPI) circuit according to claim 1, which is characterized in that first sequence be from left to right,
Second sequence is from right to left；Alternatively, first sequence is that from right to left, second sequence is from left to right.
5. Serial Peripheral Interface (SPI) circuit according to claim 1, which is characterized in that
Pixel group in first grid line traffic control sub-circuit connection display area in the pixel column of part are as follows: the first grid line traffic control
Pixel group in system circuit connection display area in odd number pixel rows；
Pixel group in second gate line traffic control sub-circuit connection display area in rest of pixels row are as follows: the second gate line traffic control
Pixel group in system circuit connection display area in even pixel row.
6. Serial Peripheral Interface (SPI) circuit according to any one of claims 1 to 5, which is characterized in that the Serial Peripheral Interface (SPI)
Circuit further includes mode latch, and first shift register is also used to, and under the control of the first clock signal, is write by data
Before entering first grid line traffic control sub-circuit or second gate line traffic control sub-circuit, the mode latch is write data into.
7. Serial Peripheral Interface (SPI) circuit according to claim 1, which is characterized in that
The Serial Peripheral Interface (SPI) circuit further includes mode latch, and first shift register is also used to, in the first clock
Under signal control, before writing data into first grid line traffic control sub-circuit or second gate line traffic control sub-circuit, institute is write data into
State mode latch；
The first grid line traffic control sub-circuit includes connected the first latch and the first decoder, the first decoder connection
Pixel group in the display area in odd number pixel rows；
It includes: that first shift register will count that first shift register, which writes data into first grid line traffic control sub-circuit,
According to write-in first latch；
First latch is used for, and after first shift register writes data into first latch, generates institute
State the first open signal；
First decoder is used for, and decodes the data in first latch, is controlled according to data decoded corresponding
The unlatching of pixel column；
The second gate line traffic control sub-circuit includes the second latch and the second decoder being connected with each other, second decoder
Connect the pixel group in display area in even pixel row, wherein
It includes: that first shift register will count that first shift register, which writes data into second gate line traffic control sub-circuit,
According to write-in second latch；
Second latch is used for, and after first shift register writes data into second latch, generates institute
State the second open signal；
Second decoder is used for, and decodes the data in second latch, is controlled according to data decoded corresponding
The unlatching of pixel column.
8. a kind of display panel, which is characterized in that including the Serial Peripheral Interface (SPI) circuit as described in claim 1 to 7 is any.
9. a kind of driving method is applied to display panel as claimed in claim 8, comprising:
Based on the control of the first clock signal, first grid line traffic control sub-circuit and second is written into the data of the first shift register
Grid line controls sub-circuit；
The unlatching of corresponding pixel column is controlled according to the data that first grid line traffic control sub-circuit is written in the first shift register, and
After opening pixel column, the first open signal is generated to the shift register group；
By first clock signal and the first open signal control the multiple second shift register by the first sequence according to
Secondary generation second clock signal, is output to corresponding latch；By the control of the second clock signal successively by described
Multiple latch of the latch group are written in the data of one shift register, and, the data write-in in latch has been opened
Corresponding pixel group in the pixel column opened；
The unlatching of corresponding pixel column is controlled according to the data that second gate line traffic control sub-circuit is written in the first shift register, and
After opening pixel column, the second open signal is generated to the shift register group；
By first clock signal and the second open signal control the multiple second shift register by the second sequence according to
Secondary generation second clock signal, is output to corresponding latch, wherein second sequence is different from first sequence；
Successively the latch group is written in the data of first shift register by the control based on the second clock signal
Multiple latch, and, successively by corresponding pixel group in the pixel column that has turned on of data write-in in latch.
10. driving method according to claim 9, which is characterized in that first sequence is from left to right described second
Sequence is from right to left；Alternatively, first sequence is that from right to left, second sequence is from left to right.
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| CN201910324123.3A CN109872675B (en) | 2019-04-22 | 2019-04-22 | Serial peripheral interface circuit, display panel and driving method |
| PCT/CN2020/079147 WO2020215923A1 (en) | 2019-04-22 | 2020-03-13 | Serial peripheral interface circuit, display panel, and driving method |
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| WO2020215923A1 (en) | 2020-10-29 |
| CN109872675B (en) | 2021-03-02 |
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