KR101136237B1 - Liquid Crystal Display device - Google Patents

Abstract

Disclosed is a liquid crystal display device which improves image quality by removing flicker.

The liquid crystal display according to the present invention is a liquid crystal panel and pixels including pixels including thin film transistors formed in zigzag shapes on the basis of each of the gate lines and the data lines. And a liquid crystal panel driver for supplying the pixels in a line inversion manner in which polarity is inverted every 1/2 horizontal period (1 / 2H).

Line inversion method, dot inversion method

Description

Liquid crystal display device

1 is a view showing a conventional liquid crystal display device.

2A and 2B are diagrams illustrating a driving method of the line inversion method.

3 is a graph illustrating a driving method of the liquid crystal display of FIG. 1.

4 is a view showing a liquid crystal display device according to the present invention.

FIG. 5 is a graph illustrating a driving method of the liquid crystal display of FIG. 4.

6A and 6B illustrate a dot inversion driving method.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104a: first gate driver

104b: second gate driver 106: data driver

108: timing controller 110: common voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality by reducing a line flicker phenomenon.

Recently, with the rapid development of the information society, the necessity of a flat panel display device having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Liquid crystal display devices (Liquid Crystal Display device) is excellent in resolution, color display, image quality, etc. are actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, forms a liquid crystal material between the two substrates, and applies an electric field generated by applying a voltage to the two electrodes. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 2 displaying predetermined data, first and second gate drivers 4a and 4b for driving the liquid crystal panel 2, and data. And a timing controller 8 for generating control signals for controlling the first and second gate drivers 4a and 4b and the data driver 6.

The liquid crystal panel 2 includes a plurality of gate lines GL1 to GLn + 1 and data lines DL1 to DLm, and the plurality of gate lines GL1 to GLn + 1 and data lines DL1 to DLm. Thin film transistors (TFTs) are formed at the intersections of the &lt; RTI ID = 0.0 &gt; First and second gate drivers 4a and 4b are mounted on a lower substrate (not shown) of the liquid crystal panel 2.

The first and second gate drivers 4a and 4b sequentially supply scan signals to the plurality of gate lines GL1 to GLn + 1 according to gate control signals generated by the timing controller 8.

A plurality of shift registers S / R1 to S / Rn + 1 are mounted in the first and second gate drivers 4a and 4b. The odd-numbered shift registers S / R1 and S / R3 .. are mounted in the first gate driver 4a, and the even-numbered shift registers S / R2 and S / R4. .) Is implemented.

The data driver 6 supplies a data voltage to the plurality of data lines DL1 to DLm according to the data control signal generated by the timing controller 8.

The timing controller 8 generates a gate control signal and a data control signal using a vertical / horizontal synchronization signal V / H and a clock signal supplied from a system (not shown). The timing controller 8 also rearranges the R, G, and B signals supplied from the system (not shown) and supplies them to the data driver 6.

The liquid crystal display device having such a configuration uses an inversion driving method such as a frame inversion method, a line (column) inversion method or a dot inversion method in order to drive the pixels on the liquid crystal panel 2.

The frame inversion type liquid crystal panel driving method inverts the polarity of the data voltage supplied to the pixels on the liquid crystal panel 2 for each frame to prevent liquid crystal degradation.

In the liquid crystal panel driving method of the line inversion method, as shown in FIGS. 2A and 2B, the polarities of the data voltages supplied to the liquid crystal panel 2 are applied to the gate lines GL1 to GLn + 1 on the liquid crystal panel 2. ) And every frame. The line inversion driving method has a problem in that flicker such as a stripe pattern occurs between the gate lines GL1 to GLn + 1 as crosstalk between the pixels in the horizontal direction exists.

The column inversion type liquid crystal panel driving method inverts the polarities of the data voltages supplied to the liquid crystal panel 2 according to the data lines DL1 to DLm and the frame on the liquid crystal panel 2. This column inversion driving method has a problem in that flicker such as a stripe pattern occurs between the data lines DL1 to DLm as crosstalk exists between the vertical pixels.

The dot inversion type liquid crystal panel driving method allows each pixel on the liquid crystal panel 2 to be supplied with a data voltage having a polarity opposite to that of all adjacent pixels in the horizontal and vertical directions, and the polarity of the data voltage is changed for each frame. Let it be reversed.

The dot inversion driving method cancels the flicker generated between pixels adjacent to each other in the vertical and horizontal directions to provide an image of superior image quality compared to other inversion methods.

The liquid crystal panel 2 of the liquid crystal display device is driven in a line inversion method.

3 is a graph illustrating a driving method of the liquid crystal display of FIG. 1.

As shown in Figs. 1 and 3, the data voltage output from the data driver 6 has the same polarity for one horizontal period 1H. In addition, the common voltage generation unit (not shown) supplies a common voltage Vcom whose polarity is inverted at intervals of one horizontal period (1H) to the common electrode existing on the upper substrate of the liquid crystal panel 2.

Scan signals, that is, gate high voltages VGH are sequentially supplied to the plurality of gate lines GL1 to GLn + 1. At this time, the period of the scan signal supplied to the first and second gate lines GL1 and GL2 is one horizontal period 1H.

That is, while the gate high voltage VGH is sequentially supplied to the first and second gate lines GL1 and GL2, the data driver 6 may supply data voltages having the same polarity to the plurality of data lines DL1 ˜. DLm).

The period of the scan signal (gate high voltage VGH) supplied to the first gate line GL1 is 1/2 horizontal period (1 / 2H). When the scan signal is supplied to the first gate line GL1, the scan signal is sequentially supplied to the second gate line GL2. The period of the scan signal supplied to the first and second gate lines GL1 and GL2 is one horizontal period 1H.

When a scan signal having a period of 1/2 horizontal period (1 / 2H) is supplied to the first gate line GL1, the thin film transistor TFT connected to the first gate line GL1 is turned on. When a scan signal having a period of 1/2 horizontal period (1 / 2H) is supplied to the second gate line GL2, the thin film transistor TFT connected to the second gate line GL2 is turned on.

The thin film transistor TFT connected to the first and second gate lines GL1 and GL2 represents the same region on the liquid crystal panel 2.

As mentioned above during this operation, since the liquid crystal display device in which the two gate drivers 4a and 4b are formed on the lower substrate is driven in a line inversion manner, crosstalk between horizontal pixels is present. Flicker occurs in which a stripe pattern is formed between the horizontal lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of improving image quality by removing flicker by driving a line inversion method in a dot inversion method.

According to an exemplary embodiment of the present invention, a liquid crystal display (LCD) includes thin film transistors formed in regions formed by intersections of a plurality of gate lines and data lines, and connected in a zigzag form with respect to each of the gate lines. And a liquid crystal panel driver for supplying the pixels in a line inversion manner in which polarities are inverted every 1/2 horizontal period (1 / 2H) to drive the pixels in a dot inversion manner. do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

4 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 4, the liquid crystal display device includes a liquid crystal panel 102 displaying predetermined data, a first driving the liquid crystal panel 102 and positioned on a lower substrate of the liquid crystal panel 102. And not only the second gate drivers 104a and 104b, the data driver 106 driving the liquid crystal panel 102, the first and second gate drivers 104a and 104b, but also the data driver 106. The timing controller 108 generates a control signal to control and a common voltage generator 110 to supply a common voltage Vcom to a common electrode (not shown) existing on the liquid crystal panel 102.

The liquid crystal panel 102 includes a plurality of gate lines GL1 to GLn + 1 and data lines DL1 to DLm, and a thin film is formed at an intersection of the plurality of gate lines GL1 to GLn + 1 and the data line. The transistor TFT is formed.

The thin film transistor TFT is connected in a zigzag shape along the gate lines GL1 to GLn + 1. Accordingly, pixels driven by the gate lines GL1 to GLn + 1 are zigzag based on the gate lines GL1 to GLn + 1.

That is, pixels constituting the same horizontal line are alternately driven for each data line and driven by different gate lines GL. Accordingly, whenever the gate lines GL1 to GLn + 1 are driven, pixels arranged in a zigzag pattern are driven on two adjacent horizontal lines so that each horizontal line is driven by two gate lines.

For example, odd-numbered pixels of the pixels of the first horizontal line are driven by the first gate line GL1, and even-numbered pixels are driven by the second gate line GL2.

The first and second gate drivers 104a and 104b sequentially scan the scan signal, that is, the gate high voltage VGH, according to the gate control signal supplied from the timing controller 108. Supply to +1). The first and second gate drivers 104a and 104b are mounted on the lower substrate of the liquid crystal panel 102.

A plurality of shift registers S / R1 to S / Rn + 1 are mounted in the first and second gate drivers 104a and 104b. The odd-numbered shift registers (S / R1, S / R3 ..) are mounted in the first gate driver 104a, and the even-numbered shift registers (S / R2, S / R4.) Are mounted in the second gate driver 104b. .) Is implemented.

The first shift register S / R1 mounted in the first gate driver 104a is connected to the first gate line GL1 and the second shift register S mounted in the second gate driver 104a. / R2 is connected to the second gate line GL2.

The period of the scan signal supplied to the first gate line GL1 is 1/2 horizontal period (1 / 2H), and the period of the scan signal supplied to the second gate line GL2 is also 1/2 horizontal period ( 1 / 2H). Therefore, the period of the scan signal supplied to the plurality of gate lines GL1 to GLn + 1 is 1/2 horizontal period (1 / 2H).

The pixels of the first horizontal line are positioned in the same area on the liquid crystal panel 102.

When a scan signal is supplied to the first and second gate lines GL1 and GL2 at one horizontal period (1H) at intervals of 1/2 horizontal period (1 / 2H), the first and second gate lines (GL1.GL2) are provided. The thin film transistor (TFT) connected to is turned on in the same region on the liquid crystal panel 102.

The data driver 106 supplies a data voltage to the plurality of data lines DL1 to DLm according to a data control signal generated by the timing controller 108.

The data driver 106 may include a shift register array for sequentially supplying a sampling signal, a latch array for latching and outputting pixel data in response to the ramping signal, and a digital-analog for converting the pixel data into a data voltage. And a converter array, and a buffer array for buffering and outputting the data voltage.

The timing controller 108 generates a gate control signal and a data control signal using a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal Clock supplied from a system (not shown).

In addition, the timing controller 108 rearranges the R, G, and B data signals supplied from a system (not shown) and a graphics card (not shown) and supplies them to the data driver 106. The timing controller 108 generates a Vcom control signal to control the period and polarity of the common voltage Vcom generated by the common voltage generator 110.

The common voltage generator 110 generates the common voltage Vcom and supplies the common voltage Vcom to a common electrode (not shown) facing the pixel electrode on the liquid crystal panel 102. The common voltage Vcom generated by the common voltage generator 110 has a period of 1/2 horizontal period (1 / 2H) and its polarity is inverted at intervals of 1/2 horizontal period (1 / 2H).

As shown in FIG. 5, the common voltage Vcom generated by the common voltage generator 110 is inverted in polarity at intervals of 1/2 horizontal period (1 / 2H) and is supplied to the common electrode. When the gate high voltage VGH is supplied to the first gate line GL1 in the 1/2 horizontal period 1 / 2H, the thin film transistor TFT connected to the first gate line GL1 is turned on. At the same time, a common voltage having a negative polarity generated by the common voltage generator 110 is supplied to the common electrode.

When the thin film transistor TFT connected to the first gate line GL1 is turned on, a data voltage is supplied from the data lines DL1 to DLm to the pixel electrode. That is, a data voltage having positive polarity is charged in the odd-numbered pixels among the pixels in the first horizontal line.

The data voltage refers to a voltage whose polarity is inverted every 1/2 horizontal period (1 / 2H).

When the gate high voltage VGH is supplied to the second gate line GL2 in the 1/2 horizontal period 1 / 2H, the thin film transistor TFT connected to the second gate line GL1 is turned on. At the same time, the common voltage generator 110 inverts the polarity of the common voltage having the negative polarity according to the Vcom control signal supplied from the timing controller 108 so that the common voltage having the positive polarity is transferred to the common electrode. Supplied.

When the thin film transistor TFT connected to the second gate line GL2 is turned on, a data voltage is supplied from the data lines DL1 to DLm to the pixel electrode.

That is, the even-numbered pixels of the pixels of the first horizontal line are charged with a data voltage having a negative polarity.

The data voltage refers to a voltage having a different polarity from the data voltage supplied to the pixel electrode connected to the thin film transistor TFT connected to the first gate line GL1.

As a result, a scan signal having a period of 1/2 horizontal period (1 / 2H) is supplied to the first gate line GL1 so that a data voltage having a positive polarity is charged to the odd pixels of the first horizontal line. . Subsequently, when a scan signal having a period of 1/2 horizontal period (1 / 2H) is supplied to the second gate line GL2, a data voltage having a negative polarity is charged to the even pixels of the first horizontal line. do.

As mentioned above, since each of the plurality of gate lines GL1 to GLn + 1 is driven, pixels arranged in a zigzag form in two adjacent gate lines are driven to charge data voltages to the pixels in a line inversion manner. In this case, as illustrated in FIGS. 6A and 6B, the liquid crystal panel 102 is driven by a dot inversion method.

For example, as shown in FIG. 5 in one frame period, when the first gate line GL1 is driven in a 1/2 horizontal period (1 / 2H), positive polarity is applied to the odd-numbered pixels of the first horizontal line. When the data voltage of positive is charged and the second gate line GL2 is driven in a 1/2 horizontal period (1 / 2H), negative data is included in even-numbered pixels of the first horizontal line. The voltage is charged. The polarity of the data voltage is determined according to the common voltage Vcom which inverts the polarity every cycle of the 1/2 horizontal period (1 / 2H).

Accordingly, positive data voltages are applied to the odd pixels of the first horizontal line, negative data voltages are applied to the even pixels, and negative data voltages are applied to the odd pixels of the second horizontal line. Since the data voltage of polarity (-) is charged to the even-numbered pixels, the data voltage of positive polarity (+) is charged, so that the liquid crystal panel 102 is driven in a dot inversion manner.

When the first gate line GL1 is driven in the next frame period, the odd pixel of the first horizontal line is charged with a negative data voltage, and then the second gate line GL2 is charged. When driven, the even-numbered pixels of the first horizontal line are charged with a positive data voltage.

Accordingly, negative data voltages are applied to the odd pixels of the first horizontal line, positive data voltages are provided to the even pixels, and positive data voltages are applied to the odd pixels of the second horizontal line. Since the data voltage of polarity (+) is charged to the even-numbered pixels, the data voltage of negative (-) is charged. As a result, the liquid crystal panel 102 is driven in a dot inversion method.

The common voltage inverted by a half horizontal period (1 / 2H) generated by the common voltage generator 110 according to the Vcom control signal generated by the timing controller 108 is common to face the pixel electrode. Supplied to the electrode.

As described above, the liquid crystal display according to the present invention generates a common voltage which is inverted every 1/2 horizontal period (1 / 2H), and has a half horizontal period in the pixels arranged in a zigzag shape with respect to the corresponding gate line. Every (1 / 2H), the liquid crystal panel is dot-inverted by combining the odd-numbered (or even-numbered) data voltage of the corresponding horizontal period with the even-numbered (or odd-numbered) data voltage of the previous horizontal period. Will be driven.

Accordingly, the liquid crystal display according to the present invention uses the line inversion driving device to drive the liquid crystal panel in the dot inversion method, and thus flickers such as horizontal pattern patterns generated in the liquid crystal panel driven in the conventional line inversion method. It can be overcome by offsetting the phenomenon.

In addition, the liquid crystal display according to the present invention can improve image quality by overcoming the flicker phenomenon.

The liquid crystal display according to the present invention includes a common voltage generation unit for generating a common voltage inverted in a period of 1/2 horizontal period (1 / 2H), and 1/1 to pixels arranged in a zigzag form based on the corresponding gate line. 2 Every horizontal period (1 / 2H), line inversion is performed by combining the odd (or even) data voltage of the horizontal period and the even (or odd) data voltage of the previous 1/2 horizontal period (1 / 2H). By supplying in a manner, the liquid crystal panel is driven in a dot inversion manner. Accordingly, the liquid crystal display according to the present invention can improve the image quality by overcoming the flicker phenomenon generated by driving the conventional line inversion method.

Claims (6)

A liquid crystal panel having pixels formed in each region provided at the intersection of a plurality of gate lines and data lines and including thin film transistors connected in a zigzag form with respect to each of the gate lines; A common voltage generator configured to generate a common voltage which is a reference voltage of the pixels and is inverted every 1/2 horizontal period (1 / 2H); And And a liquid crystal panel driver for supplying the pixels in a line inversion manner in which polarity is inverted every 1/2 horizontal period (1 / 2H), thereby driving the pixels in a dot inversion manner. Device. The method of claim 1, The odd-numbered pixels of the pixels of the n-th horizontal line are connected to the n-th gate line, and the even-numbered pixels are connected to the n + 1th gate line. The method of claim 1, and even-numbered pixels of the pixels of the n-th horizontal line are connected to an n-th gate line, and odd-numbered pixels are connected to an n + 1 th gate line. The method of claim 1, The liquid crystal panel driver, Two gate drivers for driving the plurality of gate lines; A data driver supplying a data voltage to the plurality of data lines; And Control the common voltage generator, control the gate driver and the data driver, and transfer the data voltage of the current 1/2 horizontal period (1 / 2H) to the data driver every 1/2 horizontal period (1 / 2H). And a timing controller for supplying a combination of data voltages of 1/2 horizontal periods (1 / 2H). The method of claim 4, wherein And the two gate drivers are formed on the liquid crystal panel. The method of claim 4, wherein And the timing controller generates a common voltage control signal for controlling the inverted common voltage at intervals of 1/2 horizontal period (1 / 2H).

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