KR102115462B1 - Display device and method for driving the same - Google Patents

Abstract

The present invention provides a display device capable of reducing the bezel size and reducing the load of clock signal lines for inputting clock signals to the GIP-type gate shift register, and the rising time and falling time of the gate signal ( It relates to a method of driving a display device that can reduce the falling time).

Description

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

The present invention reduces the bezel size and reduces the loading of clock signal lines for inputting clock signals to a GIP-type gate shift register and a rising time and falling time of a gate signal and a display device. It relates to a method of driving a display device that can reduce.

The display device includes a display panel, a backlight unit, and a driving circuit unit for driving the display panel and the backlight (light source). The driving circuit portion includes a timing controller, a data driver, a gate shift register (gate driver), a backlight driver (LED driver), and a power supply.

In addition to forming a thin film transistor (TFT) for driving each pixel on the lower substrate (TFT array substrate) of the display panel using amorphous silicon (a-Si), the gate shift resistor is integrated into the lower substrate of the display panel. GIP (Gate In Panel) method is applied. At this time, the gate shift register may be formed by being distributed on the left and right sides of the non-display area (pad area) of the lower substrate.

1 is a view schematically showing a display device including a gate shift register of a GIP method according to the prior art.

Referring to FIG. 1, the GIP-type gate shift register 20 according to the prior art is formed on left and right sides of the active area 10 to sequentially gate signals on a plurality of gate lines formed on the display panel. To supply.

Here, when n gate lines are formed in the active region 10, a gate shift register 20 including n stages is formed on the left and right sides of the active region 10 in a GIP scheme.

In order to supply driving voltages VDD and VSS and driving signals Vst and CLK1 to 6 to the left gate shift register and the right gate shift register, a plurality of signal lines 30 are formed in the left and right non-display areas. have. At this time, the plurality of signal lines 30 is composed of a VDD line, a VSS line, a Vst signal line, and signal lines of CLK1 to CLK6.

The timing controller generates Vst and CLK1 to 6 for driving the gate shift register 20 and supplies them to a plurality of signal lines 30 formed on the left and right sides of the non-display area.

The left and right gate shift registers 20 generate gate signals using the input VDD, VSS and Vst, and CLK1 to 6 signals, and generate the generated gate signals to the active area 10 of the display panel. The formed gate lines are sequentially supplied.

Here, the left gate shift register and the right gate shift register output the gate signal to the same gate line at the same time in a double feeding method.

As described above, the gate signal can be supplied by the double feeding method, thereby reducing the delay of the gate signal, but the manufacturing cost increases and the bezel size increases because the same gate shift register and signal lines need to be formed in the left and right non-display areas. There is an increasing problem.

When 1080 gate lines are formed in the active area 10, a gate shift register including 1080 stages must be formed on the left and right sides of the active area, thereby providing space for forming logic of the left and right gate shift registers. need.

In addition, for the double feeding of the gate signal, CLK1 to 6 signals must be supplied to the left and right gate shift registers respectively, so that space for forming the CLK1 to 6 signal lines is required, thereby increasing the left and right bezel sizes. There is a problem.

2 is a diagram showing an output waveform of a gate signal of a gate shift register according to the prior art.

Referring to FIG. 2, the large screen and high-resolution display device increases the length of clock signal lines for supplying CLK1 to 6 signals to the left and right gate shift registers 20 and loads in proportion to the length increase of the signal lines ( There is a problem in that the gate signal output from the gate shift register 20 becomes unstable due to an increase in load).

In particular, the rising time and falling time of the gate signal are increased. In the case of UHD resolution, the charging time of the pixel is formed to 3.9us, but the charging time of the actual data voltage is shortened to 1 ~ 2us due to the delay of the rising and falling time of the gate signal, so that the data voltage is not charged. There is a problem that occurs.

The present invention is to solve the above-mentioned problems, and it is a technical problem to provide a display device capable of reducing the load of clock signal lines for inputting clock signals to a gate shift register.

An object of the present invention is to solve the above-mentioned problems, and to provide a display device capable of uniformly outputting a gate signal by improving clock signal lines that supply a signal to the gate shift register.

The present invention is to solve the above-mentioned problems, and it is a technical problem to provide a display device capable of reducing a delay of a gate signal output from a gate shift register.

The present invention is to solve the above-mentioned problems, and to reduce the bezel size (bezel size) of a display device including a gate shift register of the GIP (gate in panel) method as a technical problem.

The present invention is to solve the above-described problems, reducing the rising time and falling time (falling time) of the gate signal, a display device capable of sufficiently securing the charging time (charging time) of the data voltage and its It is a technical task to provide a driving method.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention are described below, or it will be clearly understood by those skilled in the art from the description and description.

A display device according to an exemplary embodiment of the present invention includes: a display panel formed to cross a plurality of gate lines and a plurality of data lines; A first gate shift register formed in one non-display area of the display panel and including a plurality of odd stages supplying an odd gate signal to a plurality of odd gate lines among the plurality of gate lines; A second gate shift register formed in the other non-display area of the display panel and including a plurality of even stages supplying an even gate signal to a plurality of even gate lines among the plurality of gate lines; A data driver generating odd clock signals for driving the first gate shift register and generating even clock signals for driving the second gate shift register; A plurality of odd clock signal lines for supplying the odd clock signals to the first gate shift register; And a plurality of even clock signal lines for supplying the even clock signals to the second gate shift register. Applying the odd clock signal to both input terminals of the odd clock signal lines, and the even clock signal line. Characterized in that the even clock signal is applied to both input terminals.

A driving method of a display device according to an exemplary embodiment of the present invention is a first gate shift register generating an odd gate signal and a second gate shift register generating an even gate signal separated on both sides of a display panel. The input terminal of both sides of the odd clock signal lines connected to the first gate shift register by generating odd clock signals for driving the first gate shift register and even clock signals for driving the second gate shift register. And inputting the odd clock signals to and inputting the even clock signals to both input terminals of even clock signal lines connected to the second gate shift register.

The display device according to an embodiment of the present invention for achieving the above-described problem may reduce the load of clock signal lines for inputting clock signals to the gate shift register.

The display device according to an embodiment of the present invention for achieving the above-described problems may improve the clock signal lines supplying a signal to the gate shift register to uniformly output the gate signal.

The display device according to an exemplary embodiment of the present invention for achieving the above-described problems may reduce the delay of the gate signal output from the gate shift register.

The display device according to an embodiment of the present invention for achieving the above-described problem may reduce the bezel size of a display device including a gate shift register of a GIP (gate in panel) method.

The display device according to an exemplary embodiment of the present invention for achieving the above-described problems may sufficiently reduce the rising time and falling time of the gate signal and sufficiently secure the charging time of the data voltage. have.

In addition, other features and advantages of the present invention may be newly identified through embodiments of the present invention.

1 is a view schematically showing a display device including a gate shift register of a GIP method according to the prior art.
2 is a diagram showing an output waveform of a gate signal of a gate shift register according to the prior art.
3 is a diagram schematically showing a display device including a gate shift register of a GIP method according to an embodiment of the present invention.
4 is a diagram illustrating the configuration of a gate shift register and signal lines according to an embodiment of the present invention.
5 is a view showing that the load of the clock signal is reduced as the clock signal is applied to both sides of the signal line.
6 is a view showing the rising time and falling time of the gate signal according to the resistance of the signal line.
7 is a diagram illustrating a comparison of a gate signal output waveform of a gate shift register and a gate signal output waveform of the prior art according to an embodiment of the present invention.
8 is a diagram illustrating a configuration of a gate shift register and a signal line according to another embodiment of the present invention.

Hereinafter, a display device and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

Prior to the description with reference to the drawings, the display device according to the exemplary embodiment of the present invention may apply a liquid crystal panel or an OLED panel as a display panel.

When a liquid crystal panel is applied as a display panel, it can be applied without limitation to TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, and FFS (Fringe Field Switching) mode. Hereinafter, in the embodiment, a liquid crystal panel is applied as a display panel as an example.

3 is a diagram schematically showing a display device including a gate shift register of a GIP method according to an embodiment of the present invention.

Referring to FIG. 3, a display device according to an exemplary embodiment of the present invention includes a display panel 100 that displays an image according to image data (data voltage) supplied with pixels arranged in a matrix form; A backlight unit (not shown) that supplies light to the display panel 100; It comprises a driving circuit for driving the light source of the display panel 100 and a backlight unit (not shown).

 The display panel 100 includes an opposingly bonded lower substrate (TFT array substrate) and an upper substrate (color filter array substrate), and a layer formed between the lower substrate and the upper substrate.

The upper substrate includes a color filter for displaying a color image by converting light incident through the pixels of the lower substrate into color light, and a light blocking layer for distinguishing each pixel and preventing color mixing.

N gate lines G1 to Gn and M data lines D1 to Dm are formed to cross the lower substrate. A pixel is defined by the intersection of the gate lines and the data lines, and each pixel includes a thin film transistor (TFT) and a storage capacitor (Cst). Further, each pixel includes a pixel electrode applying a data voltage and a common electrode applying a common voltage Vcom.

The TFT of each pixel is switched by the scan signal supplied through the gate line, and when the TFT is on, the data voltage supplied through the data line is supplied to the pixel.

The arrangement state of the liquid crystal in each pixel is changed by the electric field difference between the data voltage and the common voltage, and the image is displayed by adjusting the arrangement of the liquid crystal to adjust the transmittance of light incident from the backlight unit.

Subsequently, the driving circuit part includes a data driver 300, a gate shift register 200 (gate driver), a backlight driving part (not shown), and a power supply part (not shown).

Here, the data driver 300 is configured by integrating a timing controller (T-con) and a plurality of data drive ICs, and is connected to the pad 120 formed on the pad area of the display panel 100 to the active area 110. Supply data voltage.

The timing controller generates digital image data (R, G, B) by arranging the image signals from the outside in frame units, and supplies the generated digital image data to a plurality of data drive ICs.

In addition, the timing controller generates a gate control signal GCS for controlling the gate shift register 200 and a data control signal DCS for controlling the data drive IC using the input timing signal TS.

Here, the timing signal TS includes a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CLK.

The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

Data control signals (DCS) include source start pulse (SSP), source sampling clock (SSC), source output enable (SOE), polarity control signal (POL), etc. It may include.

The data driver 300 converts digital image data R, G, and B into analog image data (data voltage). Thereafter, an analog data voltage is supplied to each pixel through the data lines of the display panel 100.

In addition, the data driver 300 generates VDD voltage, VSS voltage, Vst signal and CLK1 to 6 signals for driving the gate shift register 200 formed in the left and right non-display areas of the display panel 100 by the GIP method. Then, the VDD voltage, the VSS voltage, the Vst signal, and the CLK1-6 signals are supplied to the gate shift register 200.

4 is a diagram illustrating the configuration of a gate shift register and signal lines according to an embodiment of the present invention.

Referring to FIG. 4, the gate shift register 200 generates a gate signal and supplies it to each of the plurality of gate lines formed in the active area 110 of the display panel 100, and It comprises a plurality of corresponding channels, that is, a plurality of stages.

The gate shift register 200 is formed to be distributed on the left and right sides of the non-display area (pad area) of the lower substrate. The left gate shift register 210 is formed on the left side of the non-display area of the lower substrate, and the right gate shift register 220 is formed on the right side of the non-display area of the lower substrate.

The left gate shift register 210 includes a plurality of odd stages ST having channels corresponding to 1/2 of the number of gate lines formed in the display panel 100.

The right gate shift register 220 includes a plurality of even stages ST having channels corresponding to 1/2 of the number of gate lines formed on the display panel 100.

The left gate shift register 210 and the right gate shift register 220 may include a level shifter for converting the Vout output (gate signal) to a swing width suitable for driving the thin film transistor TFT.

 A plurality of first signal lines 230 are formed in the left non-display area of the display panel 100. The plurality of first signal lines 230 supply VDD voltage, VSS voltage, Vst signal, and odd clock signals CLK1, CLK3, and CLK5 to drive the left gate shift register 210 of the display panel 100 It is to do.

Among the plurality of first signal lines 230, the odd clock signal lines 232 for supplying the odd clock signals CLK1, CLK3, and CLK5 to the odd stages of the left gate shift register 210 are the odd clock signal Is input by double feeding method. That is, the odd clock signals CLK1, CLK3, and CLK5 output from the data driver 300 are input to both input terminals of the odd clock signal lines 232.

The first clock signal CLK1 is input to both input terminals of the first ADD clock signal line, the third clock signal CLK3 is input to both input terminals of the second ADD clock signal line, and both sides of the third ADD clock signal line. The fifth clock signal CLK5 is input to the input terminal.

When the data driver 300 is formed on the upper side or the lower side of the display panel 100, the odd clock signal lines 232 are 'so that the odd clock signal can be input to the odd clock signal lines 232 in a double feeding method. It is formed in a U 'shape.

Both input terminals of the odd clock signal lines 232 are formed on the upper side of the display panel 100, and at the lower side of the display panel 100, the odd clock signal lines 232 are routed upward and the shape of the line is' It becomes U 'form.

Subsequently, a plurality of second signal lines 240 are formed in the right non-display area of the display panel 100. The plurality of second signal lines 240 supply VDD voltage, VSS voltage, Vst signal, and even clock signals CLK2, CLK4, and CLK6 to drive the right gate shift register 220 of the display panel 100 It is to do.

Among the plurality of second signal lines 240, the even clock signal lines 242 for supplying the even clock signals CLK2, CLK4, and CLK6 to the even stages of the right gate shift register 220 have an even clock signal. Is input by double feeding method. That is, the even clock signals CLK2, CLK4, and CLK6 output from the data driver 300 are input to both input terminals of the even clock signal lines 242.

The second clock signal CLK2 is input to both input terminals of the first even clock signal line, the fourth clock signal CLK3 is input to both input terminals of the second even clock signal line, and both sides of the third odd clock signal line. The sixth clock signal CLK6 is input to the input terminal.

When the data driver 300 is formed on the upper side or the lower side of the display panel 100, the even clock signal lines 242 are 'so that the even clock signal can be input to the even clock signal lines 242 in a double feeding method. It is formed in a U 'shape.

Both input terminals of the even clock signal lines 242 are formed on the upper side of the display panel 100, and the lower clock signal lines 242 are routed upward from the lower side of the display panel 100 so that the shape of the line is' It becomes U 'form.

The left gate shift register 210 generates an odd gate signal using the input VDD voltage, VSS voltage, Vst signal, and odd clock signals CLK1, CLK3, and CLK5, and a plurality of gate lines formed on the display panel 100 Among them, the odd gate signal is sequentially supplied to the odd gate lines.

In addition, the right gate shift register 220 generates an even gate signal using the input VDD voltage, VSS voltage, Vst signal, and even clock signals CLK2, CLK4, and CLK6, and a plurality of formed on the display panel 100 Among the gate lines, the even gate signal is sequentially supplied to the even gate lines.

Here, the left gate shift register 210 and the right gate shift register 220 alternately output gate signals for each channel. That is, the odd stages of the left gate shift register 210 sequentially supply gate signals to a plurality of odd gate lines. Further, the even stages of the right gate shift register 220 sequentially supply gate signals to a plurality of even gate lines.

In the display device according to an exemplary embodiment of the present invention, the gate shift register 200 is divided into a left gate shift register 210 and a right gate shift register 220 and is formed on the left and right sides of the display panel. In addition, in a single feeding method, the left gate shift register 210 and the right gate shift register 220 alternately output a gate signal for each channel, thereby reducing the number of stages to 1/2 and thus the gate shift register. The area for forming the logic of can be reduced.

5 is a view showing that the load of the clock signal is reduced as the clock signal is applied to both sides of the signal line.

Referring to FIG. 5, in the prior art, a clock signal is applied to only one side of a clock signal line, and RC of one clock signal line acts as a load for the clock signal, resulting in a delay of the clock signal, which causes the stage to be delayed. There is a problem that the output gate signal becomes unstable.

On the other hand, in the present invention, clock signals are applied to both input terminals of the clock signal lines, so that the load by RC of one clock signal line is reduced to 1/2. Since the load on the clock signal is reduced to 1/2, the delay of the clock signal is reduced, so that the gate signal can be stably output in the odd stages and even stages.

6 is a diagram showing a rising time and a falling time of a gate signal according to the resistance of a signal line, and FIG. 7 is a comparison of the gate signal output waveform of the gate shift register and the gate signal output waveform of the prior art according to an embodiment of the present invention It is a figure shown.

6 and 7, it can be seen that when the resistance of the clock signal line decreases, the rising time of the gate signal decreases, and when the resistance of the clock signal line increases, the rising time of the gate signal also increases. In FIG. 6, 'Link R' means a resistance of a clock signal line to which a clock signal is applied in a double feeding method.

In the prior art, the rising time of the gate signal was 8.0 μs. On the other hand, the display device according to an embodiment of the present invention and a driving method thereof can reduce the rising time of the gate signal to 6.67us by applying a clock signal (CLK) to the clock signal line by a double feeding method.

Similarly, it can be seen that when the resistance of the clock signal line decreases, the polling time of the gate signal decreases, and when the resistance of the clock signal line increases, the polling time of the gate signal also increases.

In the prior art, the polling time of the gate signal was 3.2 μs. On the other hand, the display device and the driving method according to an embodiment of the present invention can reduce the polling time of the gate signal to 2.48us by applying a clock signal (CLK) to the clock signal line in a double feeding method.

The display device according to an exemplary embodiment of the present invention and a driving method thereof are stably applied by applying a clock signal (CLK) to a clock signal line by a double feeding method to reduce the rising time of the gate signal by 1.33us and decrease the polling time by 0.72us. The gate signal may be supplied to the active region 110.

In addition, in the related art, a worst point is formed at a lower portion of the display panel based on the polling time of the gate signal. On the other hand, the present invention can be formed to move the lowest level point to the center of the display panel based on the polling time of the gate signal.

8 is a diagram illustrating a configuration of a gate shift register and a signal line according to another embodiment of the present invention.

Referring to FIG. 8, an odd clock signal may be input to the odd clock signal lines 232 in a double feeding method, and an even clock signal may be input to the even clock signal lines 242 in a double feeding method.

When the data driver 300 is formed on the upper and lower sides of the display panel 100, the odd clock signal lines 232 and even clock signal lines 242 are not routed in a 'U' form, and the display panel 100 ) Is formed in the shape of 'I' from the upper side to the lower side.

 The clock signals output from the first data driver formed on the upper side of the display panel 100 are applied to the upper input terminals of the odd clock signal lines 232 and even clock signal lines 242.

The clock signals output from the second data driver formed on the lower side of the display panel 100 are applied to the lower input terminals of the odd clock signal lines 232 and even clock signal lines 242.

The left gate shift register 210 generates an odd gate signal using the input VDD voltage, VSS voltage, Vst signal and odd clock signals CLK1, CLK3, and CLK5, and a plurality of gate lines formed on the display panel 100 Among them, the odd gate signal is sequentially supplied to the odd gate lines.

In addition, the right gate shift register 220 generates an even gate signal using the input VDD voltage, VSS voltage, Vst signal, and even clock signals CLK2, CLK4, and CLK6, and a plurality of formed on the display panel 100 Among the gate lines, the even gate signal is sequentially supplied to the even gate lines.

In FIG. 8, the left gate shift register 210 and the right gate shift register 220 alternately output a gate signal by one channel in a single feeding method, so that the number of stages is 1/2. By reducing, the area for forming the logic of the gate shift register can be reduced. Through this, the bezel size of the display device including the gate shift register of the GIP (gate in panel) method can be reduced.

Also, by applying clock signals to both input terminals of the clock signal lines, the delay of the clock signal can be reduced, and the gate signal can be stably output from the odd stages and even stages.

In addition, the rising time and falling time of the gate signal may be reduced to sufficiently secure a charging time of the data voltage.

Those skilled in the art to which the present invention pertains will understand that the above-described present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

The scope of the present invention is indicated by the following claims rather than the above detailed description, and it should be interpreted that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts are included in the scope of the present invention. do.

100: display panel 110: active area
120: pad 200: gate shift register
210: left gate shift register
220: right gate shift register
230: first signal line 232: odd clock signal line
240: second signal line 242: even clock signal line
300: data driver

Claims (19)

A display panel formed to cross a plurality of gate lines and a plurality of data lines;
A first gate shift register formed in one non-display area of the display panel and including a plurality of odd stages supplying an odd gate signal to a plurality of odd gate lines among the plurality of gate lines;
A second gate shift register formed in the other non-display area of the display panel and including a plurality of even stages that supply an even gate signal to a plurality of even gate lines among the plurality of gate lines;
A data driver generating odd clock signals for driving the first gate shift register and generating even clock signals for driving the second gate shift register;
A plurality of odd clock signal lines for supplying the odd clock signals to the first gate shift register; And
And a plurality of even clock signal lines for supplying the even clock signals to the second gate shift register.
Applying the odd clock signal to both input terminals of the odd clock signal lines,
The even clock signal is applied to both input terminals of the even clock signal lines, and the odd clock signal lines and the even clock signal lines are formed in an 'I' shape,
Clock signals output from the data driver formed on the upper side of the display panel are applied to the upper input terminal of the odd clock signal lines and the even clock signal lines,
The clock signal output from the data driver formed on the lower side of the display panel is applied to the lower input terminal of the odd clock signal lines and the even clock signal lines.
According to claim 1,
The odd clock signal lines are formed in one non-display area of the display panel,
The even clock signal lines are formed on the other non-display area of the display panel. delete delete delete delete delete A first gate shift register for generating an odd gate signal and a second gate shift register for generating an even gate signal, wherein the driving method of the display device is formed separately on both sides of the display panel,
Generate odd clock signals for driving the first gate shift register and even clock signals for driving the second gate shift register,
Input the odd clock signals to both input terminals of the odd clock signal lines connected to the first gate shift register,
Inputting the even clock signals to both input terminals of the even clock signal lines connected to the second gate shift register,
In the display device, the odd clock signal lines and the even clock signal lines are formed in an 'I' shape,
Clock signals output from the data driver formed on the upper side of the display panel are applied to the upper input terminal of the odd clock signal lines and the even clock signal lines,
The clock signal output from the data driver formed on the lower side of the display panel is applied to the lower input terminal of the odd clock signal lines and the even clock signal lines.
delete delete The method of claim 8,
The first gate shift register and the second gate shift register is a driving method of a display device, characterized in that alternately outputs a gate signal for each channel in a single feeding method.
According to claim 1,
And the first gate shift register and the second gate shift register alternately output a gate signal by one channel in a single feeding method.
delete delete delete delete delete delete delete

Images