KR101611910B1 - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a method of driving the same, which can reduce a manufacturing cost of a product by simplifying a driving circuit for reducing flicker of a liquid crystal panel having a built-in gate driver, A liquid crystal panel for displaying an image; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for generating a gate control signal together with a plurality of flicker prevention signals and controlling a driving timing of the gate driver; On-voltage is generated and output by half-number of the plurality of flicker-prevention signals by performing an AND operation so as to be varied at different points of the level of the gate-on voltage in accordance with each of the anti- A gate-on voltage varying unit; And a level shifter for changing the voltages of the plurality of clocks supplied from the timing controller to the at least one variable gate on voltage and the gate off voltage level and supplying the same to the gate driver.

Flicker, GPM (Gate Pulse Modulation) -IC,

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a driving device for a liquid crystal display device and a driving method thereof, which can reduce a manufacturing cost of a product by simplifying a driving circuit for reducing a flicker of a liquid crystal panel having a built- .

A liquid crystal display device displays an image using electrical and optical characteristics of a liquid crystal. Liquid crystals have different anisotropic properties depending on refractive index, permittivity and others in the molecular long axis direction and short axis direction, and can easily control molecular arrangement and optical properties. Accordingly, a liquid crystal display device displays an image by varying the arrangement direction of liquid crystal molecules according to an electric field to adjust the light transmittance.

A liquid crystal display includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the liquid crystal panel, and a data driver for driving data lines of the liquid crystal panel.

Each pixel of the liquid crystal panel implements a desired color by a combination of red, green, and blue sub-pixels that adjust the light transmittance by varying the liquid crystal array according to the data signal. Each sub-pixel includes a thin film transistor connected to the gate line and the data line, and a liquid crystal capacitor connected to the thin film transistor. The liquid crystal capacitor charges the pixel voltage, which is the difference between the data signal supplied to the pixel electrode through the thin film transistor and the common voltage supplied to the common electrode, and drives the liquid crystal according to the charged pixel voltage to adjust the light transmittance.

However, in the conventional liquid crystal display device, when the TFT is turned off, the pixel voltage charged in each sub pixel varies depending on the parasitic capacitance included in the TFT and the variable value of the gate voltage, and the positive and negative pixel voltage variable values Flicker occurs due to deviation. In addition, the conventional liquid crystal display device has a problem in that the amount of delay of the scan pulse due to the load (resistance and capacitor) of the gate line increases while the size of the liquid crystal display device increases, and the image charge time of the thin film transistor is insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a driving apparatus for a liquid crystal display device and a driving method thereof for reducing flicker of a liquid crystal panel incorporating a gate driver and simplifying a driving circuit therefor, The purpose of the method is to provide.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display, including: a liquid crystal panel having a plurality of pixel regions to display an image; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for generating a gate control signal together with a plurality of flicker prevention signals and controlling a driving timing of the gate driver; On-voltage is generated and output by half-number of the plurality of flicker-prevention signals by performing an AND operation so as to be varied at different points of the level of the gate-on voltage in accordance with each of the anti- A gate-on voltage varying unit; And a level shifter for changing the voltages of the plurality of clocks supplied from the timing controller to the at least one variable gate on voltage and the gate off voltage level and supplying the same to the gate driver.

Wherein the gate-on voltage varying unit includes at least one AND circuit for performing a logical multiplication of two signals having no mutual interference among the plurality of flicker-prevention signals to half-off the number of the plurality of flicker- On-voltage is varied so that the level of the gate-on voltage varies at different points according to each of the flicker-preventing signals of the GPM integrated circuit.

The at least one AND circuit may generate and output a first transform flicker preventing signal by performing a logical AND operation on the first flicker preventing signal and the third flickering preventing signal without mutual interference among the first through fourth flicker preventing signals And a second flicker preventing circuit for generating and outputting a second flicker preventing signal by ANDing the first flicker preventing signal and the second flickering preventing signal without mutual interference among the first AND circuit and the first to fourth flicker preventing signals, And a logical multiplication circuit.

Wherein the level shifter changes a voltage level of each of odd-numbered first and third clocks of the plurality of clocks from the timing controller to the first variable-gate-on voltage to output first and third variable clocks, And a second level shifter unit for outputting the second and fourth variable clocks by changing the voltage level of each of the even and odd second clocks of the plurality of clocks from the timing controller to the second variable gate on voltage .

The timing controller further generates a gate start pulse, and the first level shifter changes the high voltage of the gate start pulse to the first variable gate-on voltage and the gate-off voltage of the low voltage and outputs the same. do.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display including driving gate lines of a liquid crystal panel displaying an image using a gate driver, Controlling a driving timing of the liquid crystal panel by generating a gate control signal together with a plurality of flicker preventing signals through a timing controller; On-voltage is generated and output by half-number of the plurality of flicker-prevention signals by performing an AND operation so as to be varied at different points of the level of the gate-on voltage in accordance with each of the anti- ; And changing the voltage of the plurality of clocks supplied from the timing controller to the at least one variable gate on voltage and the gate off voltage level to supply the gate driver with the variable clock.

Wherein the step of generating and outputting the at least one variable gate on voltage includes performing a logical product operation of two signals having no mutual interference among the plurality of flicker prevention signals using at least one logical multiplication circuit, And generating at least one variable gate-on voltage so that the level of the gate-on voltage varies at different points according to each of the half-anti-flicker signals using at least one GPM integrated circuit The method comprising the steps of:

Wherein the step of halving the number of the flicker preventing signals includes a step of outputting a first flicker preventing signal having no mutual interference among the first flicker preventing signal and a third flickering preventing signal having no mutual interference among the first flicker preventing signal, Generating a first flicker preventing signal by ANDing a first flicker preventing signal and a second flicker preventing signal by performing a logical AND operation of the first flicker preventing signal and the second flicker preventing signal, And generating and outputting a second conversion flicker prevention signal by performing an AND operation on the anti-flip signal.

The step of generating the at least one variable gate-on voltage may comprise: using a first level shifter to set a voltage level of each of the odd-numbered first and third clocks of the plurality of clocks from the timing controller to the first variable- And outputting the first and third variable clocks; and using the second level shifter to shift the voltage level of each of the even-numbered second and fourth clocks of the plurality of clocks from the timing controller to the second variable- And outputting the second and fourth variable clocks.

Wherein the step of controlling the driving timing of the liquid crystal panel further includes the steps of generating a gate start pulse and using the first level shifter to set the high voltage of the gate start pulse to the first variable gate on voltage and the gate voltage of the low voltage gate off And outputting the converted voltage.

The driving apparatus and the driving method of the liquid crystal display according to the embodiment of the present invention having the above characteristics can reduce the flicker of the liquid crystal panel having the built-in gate driver and simplify the driving circuit for the same, have.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 2 having a plurality of pixel regions to display an image; A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2; A timing controller 8 for generating gate and data control signals GCS and DCS together with a plurality of flicker preventing signals FLK1 to FLK4 to control the gate and data drivers 6 and 4; The number of flicker preventing signals FLK1 to FLK4 is halved by performing an AND operation so that the flicker preventing signals FLK1 to FLK4 are varied at different points of the gate-on voltage according to each of the anti-flicker preventing signals, A gate on voltage varying unit 14 for generating and outputting signals VON1 and VON2; And a gate driver 6 for supplying the gate driver 6 with the voltages of the plurality of clocks CLK1 to CLK4 supplied from the timing controller 8 to at least one of the variable gate on voltages VON1 and VON2 and the gate off voltage level, (16).

The liquid crystal panel 2 includes a plurality of gate lines GL1 to GLn and data lines DL1 to DLm formed in a crossing structure with an insulating film therebetween and a plurality of gate lines GL1 to GLn, (DL1 to DLm), and arranged in a matrix form. Each of the sub-pixels includes a thin film transistor (TFT) connected to each gate line GL and a data line DL, a liquid crystal capacitor Clc connected in parallel with the thin film transistor TFT, and a storage capacitor Cst. The liquid crystal capacitor Clc includes a liquid crystal, a pixel electrode for applying an electric field to the liquid crystal, and a common electrode. The storage capacitor Cst has a structure in which the pixel electrode and the common electrode are overlapped with the insulating film sandwiched therebetween, or the pixel electrode overlaps the previous-stage gate line and the insulating film. The thin film transistor TFT supplies a data voltage from each data line DL to the pixel electrode in response to a gate-on voltage which is a scan pulse from each gate line GL and supplies the data voltage to the pixel electrode in response to the gate- Thereby maintaining the data voltage. The liquid crystal capacitor Clc charges the pixel voltage which is the difference between the data voltage supplied to the pixel electrode and the common voltage VCOM supplied to the common electrode and drives the liquid crystal according to the charged pixel voltage to adjust the light transmittance, The gradation of the sub-pixel is displayed. The storage capacitor Cst stably maintains the pixel voltage charged in the liquid crystal capacitor Clc during the period when the thin film transistor TFT is turned off. In the present invention, a GPM (Gate Pulse Modulation) method for converting a level of a gate-on voltage is performed to cause a scan pulse to fall from a gate-on voltage to a gate-off voltage in a stepwise manner through an intermediate voltage. Accordingly, since the variation value of the gate on voltage is reduced, the variation value of the pixel voltage charged in each sub pixel proportional to the variation value of the gate voltage is also reduced. Therefore, flicker due to the variation value of the pixel voltage is prevented.

The data driver 4 receives the image data Data and the data control signal DCS which are input from the timing controller 8 and drives the respective data lines DL1 to DLm. More specifically, the data driver 4 outputs the aligned input image data (data) by using a source start pulse (SSP) and a source shift clock (SSC) among the supplied data control signals DCS Data is converted into analog image data, that is, a data voltage, and a data voltage for one horizontal line is supplied to each data line (data line) for each horizontal period in which a gate-on signal (or a scan pulse) is supplied to each gate line GL1- (DL1 to DLm). At this time, the data driver 4 supplies the data voltages to the data lines DL1 to DLm in response to a source output enable (SOE) signal.

More specifically, the data driver 4 latches the image data (Data) input in accordance with the SSC in units of horizontal lines, and then outputs the latched image data to the analog data voltage (Vcc) using the positive and negative gamma voltages . At this time, the data driver 4 converts the polarity of the data voltages to be inverted in at least one horizontal line unit or frame unit according to the polarity control signal from the timing controller 8 and the positive and negative gamma voltages. And supplies the converted data voltages of positive or negative polarity to the data lines DL1 to DLm for one horizontal line per one horizontal period supplied with the gate-on signal to each of the gate lines GL1 to GLn.

The gate driver 6 is integrated with the data driver 4 and connected to the liquid crystal panel 2 or embedded on the liquid crystal panel 2. [ The gate driver 6 generates a scan signal responsive to the gate start pulse GSP and the plurality of variable clocks MCLK1 to MCLK4 from the timing controller 8 via the level shifter 16, (GL1 to GLn).

For this purpose, the gate driver 6 is composed of a shift register composed of a plurality of stages. The output lines of each of the plurality of stages are connected to each of the gate lines GL1 to GLn and the input stage of the next stage. A gate start pulse GSP is input to the input line of the first stage and a plurality of variable clocks MCLK1 to MCLK4 from the level shifter 16 are alternately supplied to the plurality of stages sequentially. Each stage outputs any one of a plurality of variable clocks (MCLK1 to MCLK4) supplied to the pull-up transistor of the output stage as a scan pulse. For example, when the first to fourth variable clocks MCLK1 to MCLK4 are input from the level shifter section 16 to the gate driver 6, the 4i-th stage (where i is a natural number) The fourth stage is a second variable clock MCLK2, the fourth i-1st stage is a third variable clock MCLK3, and the fourth i-th stage is a fourth variable clock MCLK4. ) As a scan pulse. Accordingly, each of the gate lines GL1 to GLn is supplied with a scan pulse in the 2H period in which the adjacent scan pulse and the 1H period are overlapped. When the gate-on voltage falls to the gate-off voltage at the end of the scan pulse, And then descends in a stepped form.

The gate on voltage varying unit 14 halves the number of the plurality of flicker preventing signals FLK1 to FLK4 input from the timing controller 8 by using at least one logical multiplication circuit. And at least one variable-gate-on-voltage, for example, a first and a second variable gate signal, to be varied at different levels of the gate-on voltage according to each of the anti-flicker signals using at least one GPM integrated circuit. On voltages VON1 and VON2. The first and second variable gate-on voltages VON1 and VON2 thus generated are supplied to the level shifter 16. [ As described above, the gate-on voltage varying unit 14 of the present invention includes at least one AND circuit (for example, AND Gate) to reduce the total number of flicker preventing signals FLK1 to FLK4 to 1/2 It is applied in half. Accordingly, the number of GPM integrated circuits that should have been provided so as to correspond to the total number of flicker prevention signals FLK1 to FLK4 can be reduced by half, so that the circuit configuration of the gate-on voltage varying unit 14 can be simplified do.

The level shifter section 16 is connected to the timing controller 8 using the first and second variable gate on voltages VON1 and VON2 from the gate on voltage varying section 14 and the gate off voltage from the power source section The level of the gate start pulse GSP is varied, and the waveform and level of the multiple clocks CLK are varied and output. Each of the plurality of clocks CLK input from the timing controller 8 has a high voltage period in a 2H period (two horizontal periods) and overlaps a high voltage in a temporally adjacent clock CLK with a 1H period (one horizontal period) And has a shifted form. The level shifter unit 16 outputs the high voltage of the gate start pulse GSP and the multiple clocks CLK1 to CLK4 to the first or second variable gate on voltages VON1 and VON2 from the gate on voltage variable unit 14, And changes the low level to the gate off voltage from the power supply unit (not shown) and outputs it. Accordingly, the plurality of variable clocks (MCLK1 to MCLK4) output from the level shifter 16 have a high voltage in the 2H period, and the high voltage end includes a portion cut to the intermediate voltage, And is supplied to the gate driver 6 while being overlapped with the 1H period. Hereinafter, the gate-on voltage varying unit and the level shifter according to the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a block diagram specifically illustrating the gate-on voltage varying unit and the level shifter unit shown in FIG. 1. FIG. 3 is an input / output waveform diagram of the gate-on voltage varying unit and the level shifter unit shown in FIG.

The gate-on voltage varying unit 14 of FIG. 2 performs an AND operation on the two flicker preventing signals FLK1 to FLK4 input from the timing controller 8, At least one logical multiplication circuit (40, 42) for halving the number of flicker detection signals (FLK1 to FLK4) and outputting half the number of flicker preventing signals (SFLK1, SFLK2) And at least one GPM integrated circuit (44, 46) for generating at least one variable gate on voltage (VON1, VON2) to be varied at a point.

3, the timing controller 8 has a high voltage of 2H period and a duty ratio of 0.5, and the 1H period is overlapped with the high voltage of the adjacent clock, 4 clocks (CLK1 to CLK4). However, the first clock CLK1 is supplied with a high voltage of 1H period only at the beginning of each frame.

As shown in FIG. 3, the timing controller 8 generates a low voltage in the period of 0.5H and a high voltage in the period of the remaining 3.5H in the period of 4H, and shifts while being superimposed on the high voltage of the adjacent clocks in the period of 2.5H And sequentially outputs the first to fourth flicker prevention signals FLK1 to FLK4.

The first logical product operation circuit 40 of the at least one logical multiplication circuit 40 or 42 outputs the first flicker preventing signal FLK1 to the fourth flicker preventing signal FLK4 generated as described above from the timing controller 8 Flicker preventing signal SFLK1 by ANDing the first flicker preventing signal FLK1 and the third flicker preventing signal FLK3 which do not have mutual interference.

The second AND operation circuit 42 of the at least one logical multiplication circuit 40 or 42 performs a second flicker prevention operation in which there is no mutual interference among the first to fourth flicker prevention signals FLK1 to FLK4, Flicker preventing signal SFLK2 by performing an AND operation between the signal FLK2 and the fourth flicker preventing signal FLK4.

The first GPM integrated circuit 44 outputs the gate-on voltage from the power supply unit (not shown) for every low voltage period of the first conversion flicker preventing signal SFLK1 in response to the polling edge of the first conversion flicker preventing signal SFLK1 To generate and output the first variable gate ON voltage VON1. In other words, as shown in FIG. 3, the first GPM integrated circuit 44 generates a first variable gate-on voltage (hereinafter, referred to as " gate-on voltage " MVON1.

The second GPM integrated circuit 46 reduces the gate-on voltage from the power supply unit (not shown) every low voltage period of the second conversion flicker preventing signal SFLK2 in response to the polling edge of the second conversion flicker preventing signal SFLK2 . As a result, the second GPM integrated circuit 46 maintains the gate-on voltage as shown in FIG. 3, and in response to the low voltage of the 2H period of the second converted flicker preventing signal SFLK2, And outputs a two-variable gate-on voltage VON2. At this time, the reduced portion of the second variable gate-on voltage VON2 has a shape that is staggered by the decreasing portion of the first variable gate-on voltage VON1 and the 1H period as shown in FIG.

The level shifter unit 16 changes the voltage level of each of the odd-numbered clocks CLK1 and CLK3 of the first to fourth clocks CLK1 to CLK4 from the timing controller 8 to the first variable gate-on voltage VON1 A first level shifter 50 for outputting first and third variable clocks MCLK1 and MCLK3 and a second level shifter 50 for outputting even-numbered clocks CLK2 and CLK4 among the first to fourth clocks CLK1 to CLK4 from the timing controller 8, And a second level shifter 52 for changing the voltage levels of the first and second variable clocks CLK1 and CLK4 to the second variable gate-on voltage VON2 to output the second and fourth variable clocks MCLK2 and MCLK4, respectively.

Specifically, the first level shifter unit 50 outputs the high voltages of the first and third clocks CLK1 and CLK3 from the timing controller 8 to the first variable gate on voltage (Vcc) from the first GPM integrated circuit 44 And the first and third variable clocks MCLK1 and MCLK3 by changing the low voltage to the gate off voltage from the power supply unit (not shown). As a result, the first and third variable clocks MCLK1 and MCLK3 have the same cycle as the first and third clocks CLK1 and CLK3 as shown in FIG. 3, the amplitude increases, and the end of the gate- Off voltage to the gate-off voltage. The first level shifter 50 converts the high voltage of the gate start pulse GSP to the first variable gate on voltage VON1 from the first GPM integrated circuit 44 and the low voltage to the power source unit To the gate-off voltage from the gate-off voltage.

The second level shifter section 52 outputs a high voltage of the second and fourth clocks CLK2 and CLK4 from the timing controller 8 to the second variable gate on voltage VON2 from the second GPM integrated circuit 46, , And changes the low voltage to the gate-off voltage and outputs it. As a result, the second and fourth variable clocks MCLK2 and MCLK4 have the same cycle as the second and fourth clocks CLK2 and CLK4 as shown in FIG. 3, and the amplitudes of the second and fourth variable clocks MCLK2 and MCLK4 increase, Off voltage to the gate-off voltage.

The first to fourth variable clocks CLK1 to CLK4 output from the first and second level shifter units 50 and 52 are alternately supplied to a plurality of stages of the gate driver 6. Thus, the 4i-3 (where i is a natural number) stage of the plurality of stages is the first variable clock MCLK1, the 4i-2st stage is the second variable clock MCLK2, the 4i-1 Th stage outputs the third variable clock MCLK3, and the 4 < th > stage outputs the fourth variable clock MCLK4 as a scan pulse. In other words, the first to fourth variable clocks MCLK1 to MCLK4 shown in FIG. 3 are alternately supplied to the gate lines GL1 to GLn as scan pulses.

As described above, in the present invention, the number of GPM integrated circuits 44 and 46, which should have been provided so as to correspond to the total number of flicker preventing signals, for example, the number of the first to fourth flicker preventing signals FLK1 to FLK4, And the circuit configuration of the gate-on voltage varying unit 14 can be simplified. Since the scan pulse in the 2H period in which the former scan pulse and the latter half are overlapped and the next scan pulse and the latter half (1H) are superimposed are supplied to the gate lines GL1 to GLn, the load (resistance and capacitance The data charging time of the thin film transistor can be sufficiently secured even if the scan pulse is delayed. In addition, since the gate-on voltage is lowered in a step-like manner to the gate-off voltage through the intermediate voltage only at the end of each scan pulse, the pixel voltage variation value decreases due to the decrease in the gate voltage variation value, thereby reducing the flicker.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a configuration diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention;

FIG. 2 is a block diagram specifically showing the gate-on voltage varying unit and the level shifter unit shown in FIG. 1. FIG.

FIG. 3 is an input / output waveform diagram of the gate-on voltage variable portion and the level shifter portion shown in FIG. 2. FIG.

Description of the Related Art [0002]

2; Liquid crystal panel 4: data driver

6: Gate driver 8: Timing controller

14: gate-on-voltage variable portion 16: level shifter

40: first logical product operation circuit 42: second logical product operation circuit

44: first GPM integrated circuit 46: second GPM integrated circuit

50: first level shifter section 52: second level shifter section

Claims (10)

A liquid crystal panel having a plurality of pixel regions to display an image; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for generating a gate control signal together with a plurality of flicker prevention signals and controlling a driving timing of the gate driver; On-voltage is generated and output by half-number of the plurality of flicker-prevention signals by performing an AND operation so as to be varied at different points of the level of the gate-on voltage in accordance with each of the anti- A gate-on voltage varying unit; And And a level shifter section for changing the voltage of the plurality of clocks supplied from the timing controller to the at least one variable gate on voltage and the gate off voltage level to supply the gate driver with the gate driver, The gate-on voltage varying unit At least one logical product arithmetic circuit for performing a logical multiplication of two signals without mutual interference among the plurality of flicker prevention signals so as to halve the number of the plurality of flicker prevention signals, On voltage to generate at least one variable gate-on voltage so that the level of the gate-on voltage varies at different points according to each of the half-anti-flicker signals, The at least one AND circuit A first AND circuit for generating and outputting a first conversion flicker preventing signal by ANDing the first flicker preventing signal and the third flickering preventing signal without mutual interference among the first flicker preventing signal and the fourth flickering preventing signal, And a second AND operation circuit for generating and outputting a second conversion flicker preventing signal by performing a logical multiplication of the first flicker preventing signal and the second flicker preventing signal without mutual interference among the first flicker preventing signal and the fourth flickering preventing signal And the driving device of the liquid crystal display device. delete delete The method according to claim 1, The level shifter unit A first level shifter section for changing the voltage level of each of odd-numbered first and third clocks among the plurality of clocks from the timing controller to the first variable gate-on voltage and outputting the first and third variable clocks, And a second level shifter portion for outputting the second and fourth variable clocks by changing the voltage levels of the even and odd second and fourth clocks of the plurality of clocks from the timing controller to the second variable gate on voltage And the driving device of the liquid crystal display device. 5. The method of claim 4, The timing controller And the first level shifter changes the high voltage of the gate start pulse to the first variable gate-on voltage and the gate-off voltage of the low voltage to output the gate-start pulse. Driving device. Driving gate lines of a liquid crystal panel displaying an image using a gate driver; Controlling a driving timing of the liquid crystal panel by generating a gate control signal together with a plurality of flicker preventing signals through a timing controller; On-voltage is generated and output by half-number of the plurality of flicker-prevention signals by performing an AND operation so as to be varied at different points of the level of the gate-on voltage in accordance with each of the anti- ; And Changing a voltage of a plurality of clocks supplied from the timing controller to the at least one variable gate on voltage and a gate off voltage level and supplying the gate driver with the variable clock voltage, The step of generating and outputting the at least one variable gate- A step of performing a logical multiplication of two signals having no mutual interference among the plurality of flicker preventing signals by using at least one logical multiplication circuit so that the number of the plurality of flicker preventing signals is halved and output; Generating at least one variable gate-on voltage using at least one GPM integrated circuit so that the level of the gate-on voltage varies at different points according to each of the half-anti-flicker signals, The step of outputting the number of the plurality of flicker preventing signals by half A first AND circuit is used to perform AND operation of the first flicker preventing signal and the third flicker preventing signal which are free of mutual interference among the first flicker preventing signal and the fourth flickering preventing signal to generate and output a first converting flicker preventing signal Step, and A second AND gate circuit for generating and outputting a second flicker preventing signal by ANDing the second flicker preventing signal having no mutual interference among the first flicker preventing signal and the fourth flickering preventing signal using the second AND gate, And a driving method of the liquid crystal display device. delete delete The method according to claim 6, The step of generating the at least one variable gate- The first and third variable clocks are switched by changing the voltage level of each of the odd-numbered first and third clocks among the plurality of clocks from the timing controller to the first variable-gate-on voltage using the first level shifter unit Step, and And outputting second and fourth variable clocks by changing a voltage level of each of second and fourth clocks, which are even-numbered among a plurality of clocks from the timing controller, to the second variable gate-on voltage by using a second level shifter unit And a driving method of the liquid crystal display device. 10. The method of claim 9, The step of controlling the driving timing of the liquid crystal panel Further generating a gate start pulse, and Further comprising changing the high voltage of the gate start pulse to the first variable gate-on voltage and the gate-off voltage of the low voltage by using the first level shifter section, and outputting .

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