KR100717193B1 - Liquid Crystal Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display for compensating a delay phenomenon of a gate signal due to a resistance and a capacitance component of a gate line. A liquid crystal display including a thin film transistor connected to a gate line and a data line, a pixel receiving a data signal through the thin film transistor, the liquid crystal display comprising: a data driver for outputting the data signal through the data line; And a gate driver for outputting a gate pulse signal through the gate driver, wherein the gate driver receives a pulse signal output from the shift register and a shift register for sequentially applying a pulse signal applied to the gate line. And an output buffer for outputting a gate pulse signal in which the voltage of the high level is further boosted for a period of time after the voltage rises to the level and before the data signal is applied to the thin film transistor.

Description

Liquid crystal display

1 is a waveform diagram for explaining a change in a data signal due to a gate signal of a conventional liquid crystal display device.

2 is a block diagram of a liquid crystal display device according to the present invention;

3 is an equivalent circuit diagram of one pixel of the liquid crystal display according to the present invention;

4 is a block diagram of a gate driver according to the present invention;

5 is a circuit diagram of an output buffer provided in the gate driver according to the present invention.

6A is an operational waveform diagram of an output buffer provided in the gate driver according to the present invention;

6B and 6C are circuit diagrams for describing an operation of a switching element of an output buffer provided in the gate driver according to the present invention.

7 is a waveform diagram illustrating a change of a data signal due to a gate signal of a liquid crystal display according to the present invention.

Explanation of symbols on the main parts of the drawings

120: gate driver 320: output buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display for compensating a delay phenomenon of a gate signal due to a resistance and a capacitance component of a gate line.

In general, a liquid crystal display (LCD) applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controls the amount of light transmitted through the substrate by controlling the intensity of the electric field. To obtain the desired image signal.

Such a conventional liquid crystal display device includes a liquid crystal panel for displaying an image, a data and gate driver for driving a liquid crystal panel, a signal controller for providing a data signal and a timing signal for controlling the display of the liquid crystal panel to the data and gate driver, and a liquid crystal panel. It includes a backlight for applying a predetermined light to.

The data driver is composed of a plurality of data drive circuits. Here, the data drive circuit includes a D / A converter and a buffer, and transmits an image signal applied from the outside to the liquid crystal panel through m (where m is a natural number of 2 or more) data lines. At this time, the image signal is applied as a digital signal from the outside, is converted into an analog signal through the D / A converter of the data drive circuit, and then amplified in the buffer and applied to the data line of the liquid crystal panel.

The gate driver is composed of a plurality of gate drive circuits. Here, the gate drive circuit includes a shift resist and a buffer, and transmits a gate pulse signal for controlling the thin film transistor included in the liquid crystal panel through the gate line to the liquid crystal panel. In this case, the gate drive circuit is connected to each of n (where n is a natural number of 2 or more) gate lines, and sequentially outputs a gate pulse signal from the first gate line to the nth gate line through a shift resist.

In the liquid crystal display having the above configuration, due to the resistance component of the gate line and the parasitic capacitance component of the thin film transistor, the amount of data charged in the pixel electrode connected to the m th data line is larger than the amount of data charged in the pixel electrode connected to the first data line. There is a decreasing problem. This will be described in detail with reference to FIG. 1.

1 is a waveform diagram illustrating a change of a data signal due to a gate signal of a conventional liquid crystal display. Here, the waveform represented by the solid line represents the gate pulse signal V _g and the data signal V _data applied to the pixel electrode connected to the first data line, and the waveform represented by the dotted line is applied to the pixel electrode connected to the m th data line. An applied gate pulse signal V _g and a data signal V _data are shown.

As shown, the liquid crystal display of the related art has a gate pulse signal having an on voltage (V _on ) and an off voltage (V _off ), and the gate pulse signal (V _g ) is generated by a gate output enable (GOE) signal. The on voltage V _on is applied, and the data signal V _data is charged to the pixel electrode.

However, the conventional liquid crystal display device has a thin film in which an on voltage V _on and an off voltage V _off of a gate pulse signal V _g applied to a thin film transistor connected to an m th data line are connected to a first data line. The gate voltage is delayed from the on voltage V _on and the off voltage V _off of the gate pulse signal V _g applied to the transistor and applied to the gate line. This is because a plurality of thin film transistors are connected in series to one gate line, and thus the length of the gate line becomes longer and the resistance component of the gate line becomes larger toward the m-th data line. In addition, in the conventional liquid crystal display, due to the parasitic capacitance component between the gate terminal and the source terminal, the gate terminal and the drain terminal, and the source terminal and the drain terminal of the plurality of thin film transistors, the gate pulse signal (V) increases toward the m-th data line. _g ) is gradually delayed and applied to the thin film transistor.

Accordingly, in the conventional liquid crystal display, due to the delay of the gate pulse signal V _g , the amount of data charged in the pixel electrode connected to the m-th data line decreases from the amount of data charged in the pixel electrode connected to the first data line.

Accordingly, the liquid crystal display according to the related art has a problem in that a flicker phenomenon such as flickering and a left and right luminance difference between the liquid crystal display are caused by the difference in the charge amount of the data signal V _data .

Therefore, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to flicker phenomenon such as flicker caused by the difference in the amount of charge of the data signal and the left and right luminance of the liquid crystal display device. An object of the present invention is to provide a liquid crystal display device having an improved difference.

In accordance with an aspect of the present invention, a liquid crystal display device is provided, which includes: a thin film transistor connected to a gate line and a data line, and a pixel receiving a data signal through the thin film transistor. A liquid crystal display comprising: a data driver for outputting the data signal through the data line and a gate driver for outputting a gate pulse signal through the gate line, wherein the gate driver is sequentially connected to the gate line. A shift register for outputting a pulse signal to be applied; and a high level for a time after receiving the pulse signal output from the shift register and rising from the pulse signal to a high level voltage until the data signal is applied to the thin film transistor. More voltage And an output buffer for outputting a boosted gate pulse signal.

In the above configuration, the output buffer includes: a first switching element connected between an input node and a first node; A second switching element connected between the input node and the second node; A first capacitor coupled between the first node and the second node; A third switching element and a second capacitor connected in series between the second node and a ground voltage; And an amplifier including a positive input terminal connected to the first node and a negative input terminal connected to an output node, wherein the first switching element and the third switching element perform the same operation.

In the above configuration, the first switching element and the third switching element are turned on and the second switching element is turned off for a time until the gate pulse signal rises from the low level voltage to the high level voltage. It features.

In the above configuration, the first switching element and the third switching element are turned off for a time after the gate pulse signal rises to a high level voltage and before the data signal is applied to the switching element, and the second switching element is It is turned on to further boost the high level voltage.

(Example)

2 is a block diagram of a liquid crystal display according to the present invention, and FIG. 3 is an equivalent circuit diagram of one pixel of the liquid crystal display according to the present invention.

As illustrated, the liquid crystal display according to the present invention includes a liquid crystal panel assembly 110, a gate driver 120, a data driver 130, and a signal controller 140 including an upper panel 210 and a lower panel 220. ).

The liquid crystal panel assembly 110 includes a plurality of gate lines G ₁ to G _n , a plurality of data lines D ₁ to D _m , and a plurality of gate and data lines G ₁ to G _{n ,} D ₁ to D _m. And a plurality of pixels arranged in a matrix form.

Here, each pixel includes a thin film transistor Q connected to a plurality of gates and data lines G ₁ to G _{n ,} D ₁ to D _m , and a liquid crystal capacitor C _LC connected to the thin film transistor Q. ) And a storage capacitor (C _ST ).

The thin film transistor Q is provided in the lower panel 220, the gate terminal and the drain terminal are connected to the gate line G ₁ to G _n and the data line D ₁ to D _m, respectively, and the source terminal is a liquid crystal capacitor. (C _LC ) and holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 221 of the lower panel 220 and the common electrode 211 of the upper panel 210, and the liquid crystal layer between the two electrodes 211 and 221 serves as a dielectric. do. Here, the pixel electrode 221 is connected to the thin film transistor Q, and the common electrode 211 is formed on the entire surface of the upper panel 210 to receive the common voltage V _com .

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 221 provided in the lower panel 220, and defining a common voltage V _{com on the} separate signal line. Voltage is applied.

On the other hand, in order to implement color display, each pixel must display a color, which is possible by providing a red, green, or blue color filter 212 in a region corresponding to the pixel electrode 221.

The gate driver 120 is connected to the gate lines G ₁ to G _n of the liquid crystal panel assembly 110 and includes a gate pulse signal V formed of a combination of a gate on voltage V _on and a gate off voltage V _off . _g ) is applied to the gate lines G ₁ to G _n .

The data driver 130 is connected to the data lines D ₁ to D _m of the liquid crystal panel assembly 110 to apply the gray voltage applied by the gray voltage generator (not shown) as the data signal V _data . .

The signal controller 140 generates a control signal for controlling operations of the gate driver 120 and the data driver 130, and provides control signals corresponding to each part to the gate driver 120 and the data driver 130. do.

Hereinafter, the display operation of the liquid crystal display according to the present invention will be described in detail.

The signal controller 140 is an input control signal for controlling the display of the RGB image signals R, G and B and the RGB image signals R, G and B from an external graphic controller (not shown), for example. The vertical synchronization signal V _sync and the horizontal synchronization signal H _sync , a main clock MCLK, and a data enable signal DE are provided. Thereafter, the signal controller 140 generates a gate control signal CONT1 and a data control signal CONT2 through an input control signal, and generates image signals R, G, and B in an operating condition of the liquid crystal panel assembly 110. Handle accordingly. Then, the signal controller 140 sends the gate control signal CONT1 to the gate driver 120, and sends the data control signal CONT2 and the processed image signal to the data driver 130.

Here, the gate control signal (CONT1) is the gate pulse signal (V _g) to the output start not show the start signal (STV) a vertical synchronization of the gate the gate clock signal (CPV) for controlling the output timing of the pulse signal (V _g) And an output enable signal OE which limits the width of the gate pulse signal V _g .

In addition, the data control signal CONT2 corresponds to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data signal V corresponding to the data lines D ₁ to D _m . It includes a load signal (lOAD), a common voltage (inversion signal (RVS), and the data clock signal (HCLK) for inverting the polarity of the data signal (V _data) to the V _com) and so on for instructing the application of the _data).

The data driver 130 sequentially receives and shifts the image data R ′, G ′, and B ′ corresponding to the pixels in one row according to the data control signal CONT2 applied from the signal controller 140. The data driver 130 selects a gray voltage corresponding to each of the image data R ', G', and B 'among the gray voltages applied by the gray voltage generator, and then, the image data R', G ', and B. ') Is converted into the corresponding data signal V _data and applied to the corresponding data lines D ₁ to D _m .

Gate driver 120 signals the gate-on voltage (V _on) of the gate line according to the control unit 140. The gate control signal (CONT1) is in the (G ₁ ~ G _n) applied to the gate line in (G ₁ ~ G _When the thin film transistor Q connected to _n ) is turned on, the data signal V _data applied to the data lines D ₁ to D _m is applied to the corresponding pixel through the turned on thin film transistor Q.

Thereafter, the difference between the data signal V _g and the common voltage V _com applied to the pixel is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. Here, the arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, and accordingly, the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the panels 210 and 220.

Then, after one horizontal period (or " 1H ") (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV) passes, the data driver 130 and the gate driver 120 ) Repeats the same operation for the pixels in the next row. In this manner, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ to G _n during one frame to apply the data signal V _data to all the pixels.

Then, the liquid crystal display according to the present invention starts the next frame after one frame, the inversion signal applied to the data driver 130 so that the polarity of the data signal applied to each pixel is opposite to the polarity of the previous frame The state of (RVS) is controlled ("frame inversion"). In this case, the liquid crystal display according to the present invention changes the polarity of the data signal V _data flowing through one data line ("column inversion") within one frame according to the characteristics of the inversion signal RVS, or in one pixel row. Polarities of the applied data signal V _data may also be different (“dot inversion”).

Hereinafter, the operation of the gate driver and the output buffer provided therein will be described in detail with reference to FIGS. 4 to 7. Here, the gate driver shown in FIGS. 4 to 7 is the same as the gate driver 120 of FIG. 1.

4 is a block diagram of a gate driver according to the present invention.

As shown, the gate driver according to the present invention includes a shift register 310 and an output buffer 320.

The shift register 310 converts the level of the voltage input from a power generator (not shown) and outputs it as the gate pulse signal V _g .

The output buffer 320 boosts a predetermined period of the gate pulse signal V _g and transfers it to the gate lines G ₁ to G _n .

5 is a circuit diagram of an output buffer provided in the gate driver according to the present invention.

As shown, the output buffer provided in the gate driver according to the present invention includes three switching elements (Ctrl1, Ctrl2, Ctrl3), two capacitors (C1, C2), and an amplifier (410).

The switching element Ctrl1 is connected between the 'A' node and the 'C' node, the switching element Ctrl2 is connected between the 'A' node and the 'B' node, and the switching element Ctrl3 is the 'B' node. And capacitor C2. Here, the 'A' node is an input node to which the gate pulse signal V _g is applied.

The capacitor C1 is connected between the 'B' node and the 'C' node, and the capacitor C2 is connected between the switch Ctrl3 and the ground voltage.

The positive input terminal (+) of the amplifier 410 is connected to the node 'C', and the negative input terminal (-) of the amplifier 410 is connected to the output node.

Hereinafter, the operation of the output buffer provided in the gate driver according to the present invention will be described in detail with reference to FIGS. 6A to 6C.

6A is an operation waveform diagram of an output buffer provided in the gate driver according to the present invention, and FIGS. 6B and 6C are circuit diagrams for describing an operation of a switching element of the output buffer provided in the gate driver according to the present invention.

As shown, first, in step 'i' shown in FIG. 6A, the switching elements Ctrl1 and Ctrl3 are turned on so that two capacitors C1 and C2 are connected in series between the node C and the ground voltage as shown in FIG. 6B. Leads to. At this time, the gate pulse signal V _g maintains the gate off voltage V _off , and the level increases to the gate on voltage V _on . Accordingly, the two capacitors C1 and C2 connected in series receive and charge the gate-on voltage V _on .

Next, in step 'ii' shown in FIG. 6A, the switching elements Ctrl1 and Ctrl3 are turned off, and the switching elements Ctrl2 are turned on, and as shown in FIG. 6C, between the input node and the positive input terminal (+) of the amplifier 410. One capacitor C1 is connected to it. In this case, the gate pulse signal V _g is transmitted to the input node of the output buffer according to the present invention while maintaining the gate on voltage V _on . Accordingly, the gate pulse signal V _g is charged with the capacitor C1 at the gate-on voltage V _on through the capacitor C1 and the amplifier 410, so that the positive input terminal of the amplifier 410 ( Is passed to +). In other words, the output buffer according to the present invention outputs a voltage V _emp1 boosted by the voltage level charged in the capacitor C1 at the gate-on voltage V _on when the switching element Ctrl2 is turned _on .

Next, in step 'iii' shown in FIG. 6A, the switching element Ctrl2 is turned off, the switching elements Ctrl1 and Ctrl3 are turned on, and as shown in FIG. 6B, two capacitors (C) between the node 'C' and the ground voltage are again turned on. C1, C2) are connected in series. Therefore, the gate pulse signal has a low voltage level from the boosted voltage V _emp1 to the gate on voltage V _on .

Next, in step 'iv' shown in FIG. 6A, the switching elements Ctrl1 and Ctrl3 are turned off and the switching elements Ctrl2 are turned on, and as shown in FIG. 6C, between the input node and the positive input terminal (+) of the amplifier 410. One capacitor C1 is connected to it. At this time, the gate pulse signal transitions from the gate- _on voltage (V _on ) to the gate-off voltage (V _off ) and is then transmitted to the input node of the output buffer according to the present invention. Accordingly, the gate pulse signal is added to the positive input terminal (+) of the amplifier 410 by adding the voltage charged to the capacitor C1 at the gate-off voltage V _off through the capacitor C1 and the amplifier 410. Delivered. In other words, the output buffer according to the present invention outputs the voltage V _emp2 lowered by the voltage level charged in the capacitor C1 at the gate-off voltage V _off when the switching element _Ctrl2 is turned on.

7 is a waveform diagram illustrating a change of a data signal due to a gate signal of a liquid crystal display according to the present invention. Here, the waveform represented by the solid line represents the gate pulse signal V _g and the data signal V _data applied to the pixel electrode connected to the first data line D ₁ , and the waveform represented by the dotted line is the m-th data line. The gate pulse signal V _g and the data signal V _data applied to the pixel electrode connected to D _m are shown.

As illustrated, the liquid crystal display according to the present invention has a time until the data signal V _data is applied to the thin film transistor Q after the gate pulse signal V _g rises to the gate on voltage V _on . Is applied to the gate lines G ₁ to G _n with the voltage V _{emp1 stepped} up than the gate-on voltage V _on . Similarly, in the liquid crystal display according to the present invention, after the gate pulse signal V _g decreases from the gate on voltage V _on to the gate off voltage V _off , the data signal V _data becomes the thin film transistor Q. The voltage is applied to the gate lines G ₁ to G _n with the voltage V _emp2 lowered than the gate off voltage V _off for the time until it is applied.

Accordingly, in the liquid crystal display according to the present invention, the on voltage V _on and the off voltage V _off of the gate signal V _g applied to the thin film transistor Q connected to the m th data line D _m are _reduced . The level difference between the on voltage V _on and the off voltage V _off of the gate signal V _g applied to the thin film transistor Q connected to the first data line D ₁ is not large.

In other words, the liquid crystal display according to the present invention has a resistance of the gate lines G ₁ to G _{n that} increase toward the m th data line D _m through the boosted voltage V _emp1 and the lowered voltage V _emp2 . Components and parasitic capacitance components of the thin film transistor Q are compensated for.

Therefore, the liquid crystal display according to the present invention stores the amount of data stored in the thin film transistor Q connected to the first data line D ₁ and the amount of data stored in the thin film transistor Q connected to the m th data line D _m . By reducing the difference, the flicker phenomenon such as flickering and the left and right luminance difference of the liquid crystal display are reduced.

According to the above-described configuration of the present invention, in the liquid crystal display device, an effect of reducing the flicker phenomenon such as flickering and the left and right luminance difference of the liquid crystal display device by compensating for the delay phenomenon of the gate pulse signal due to the resistance and capacitance components of the gate line. There is.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (4)

A liquid crystal display comprising a thin film transistor connected to a gate line and a data line, and a pixel receiving a data signal through the thin film transistor. A data driver for outputting the data signal through the data line; A gate driver configured to output a gate pulse signal through the gate line, The gate driver is configured to output a pulse signal sequentially applied to the gate line, and after receiving the pulse signal output from the shift register and the pulse signal rises to a high level voltage, the data signal becomes the thin film transistor. And an output buffer for outputting a gate pulse signal in which the voltage of the high level is further boosted for a time until it is applied to the liquid crystal display. The method of claim 1, The output buffer, A first switching element connected between the input node and the first node; A second switching element connected between the input node and the second node; A first capacitor coupled between the first node and the second node; A third switching element and a second capacitor connected in series between the second node and a ground voltage; And And an amplifier including a positive input terminal connected to the first node and a negative input terminal connected to an output node. And the first switching element and the third switching element perform the same operation. The method of claim 2, Wherein the first switching element and the third switching element are turned on and the second switching element is turned off for a period before the gate pulse signal rises from the low level voltage to the high level voltage. Display device. The method of claim 2, The first switching element and the third switching element are turned off, and the second switching element is turned on to turn the high voltage off after the gate pulse signal rises to a high level voltage and before the data signal is applied to the switching element. And further boosts the voltage at the level.

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