KR20080022932A - Power module for liquid crystal display, liquid crystal display having this and driving method thereof - Google Patents

Abstract

An LCD device, a power module for the LCD device, a driving method for the LCD device are provided to suppress an afterimage by minimizing a remaining DC component by discharging the remaining DC component using a common voltage signal and an image voltage signal. A power module for an LCD(Liquid Crystal Display) device includes a common voltage generator(830) and a high frequency application unit(840). The common voltage generator receives a source voltage, generates a common voltage, and outputs the common voltage. The common voltage includes positive and negative pulses. The high frequency application unit matches a high frequency signal to the common voltage, generates a high frequency common voltage, and outputs the high frequency common voltage. The high frequency common voltage defines the positive and negative pulses as main pulses and the high frequency signal as a sub pulse.

Description

Power supply module of liquid crystal display device, liquid crystal display device having same and driving method of liquid crystal display device {POWER MODULE FOR LIQUID CRYSTAL DISPLAY, LIQUID CRYSTAL DISPLAY HAVING THIS AND DRIVING METHOD THEREOF}

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram illustrating a unit pixel according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a driving voltage generator according to an exemplary embodiment of the present invention.

4 is a waveform diagram illustrating a process of generating a common power supply in the liquid crystal display according to the present embodiment.

5 is a waveform diagram illustrating a process of generating a high frequency common power source in the liquid crystal display according to the present embodiment.

FIG. 6 is a view showing a liquid crystal display panel according to the present embodiment which is driven by a line inversion method. FIG.

7 is a view showing a liquid crystal display panel according to the present embodiment driven in a frame inversion scheme.

8 is a waveform diagram illustrating a pixel voltage and a common voltage applied to a unit pixel of a liquid crystal display panel according to the present embodiment.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 200: upper substrate

300: liquid crystal display panel 400: gate driver

500: data driver 600: signal controller

700: DC / DC converter 800: drive voltage generator

900: gray voltage generator

The present invention relates to a power supply module of a liquid crystal display device, a liquid crystal display device having the same, and a method of driving the liquid crystal display device, and more particularly, a liquid crystal display device which can prevent an afterimage by reducing a DC component remaining in a unit pixel. Its purpose is to provide a power supply module, a liquid crystal display device having the same, and a method of driving the liquid crystal display device.

Liquid crystal display is a display device that realizes an image by controlling the amount of light incident from a light source using the optical anisotropy of liquid crystal molecules and the polarization characteristics of a polarizing film. In recent years, its power consumption is small, and its application range is rapidly expanding.

Since the liquid crystal display is easily deteriorated by the DC component due to the dielectric anisotropy of the liquid crystal molecules, when the same image is displayed for a long time, the trace of the initial screen, that is, image sticking, remains even when the display screen is changed.

That is, the dielectric constant of the liquid crystal molecules is changed when the driving voltage is applied to the pixel electrode or the common electrode or when the blocking voltage is applied to control the liquid crystal molecules. Due to the difference, the DC applied to the pixel electrode or the common electrode is changed. The surplus charges induced in the components remain in the ionic impurity introduced during the manufacturing process. Ionic impurities including such residual DCs are adsorbed on an organic layer, for example, an alignment layer, in the unit pixel to form an electric double layer. In this case, when the same image is displayed for a long time, the residual image remains after the liquid crystal is rearranged by the residual DC to change the transmittance characteristics even if the display screen is changed.

This afterimage is mainly a problem in the DC driving method, but as the screen resolution and the operating frequency of the liquid crystal display are increased, and the response speed is increased, the AC driving method is also a big problem. This is because the AC voltage also has a DC component in view of a very short time, which causes residual DC to occur in the unit pixel.

The present invention has been made to solve the above problems, and by providing a common power signal having a high frequency characteristic to a common electrode of a unit pixel, a liquid crystal display device which can prevent afterimages by minimizing DC components remaining in the unit pixel. It is an object of the present invention to provide a power supply for a device, a liquid crystal display device having the same, and a method of driving the liquid crystal display device.

In order to achieve the above object, a power supply module of a liquid crystal display according to the present invention includes a common voltage generator which receives a power supply voltage and generates and outputs a common voltage consisting of a positive pulse and a negative pulse; A high frequency application unit for generating a high frequency common voltage for matching the high frequency signal to a signal, generating the high frequency signal as a sub pulse, and generating the high frequency signal as a main pulse; do.

The high frequency signal is characterized by having an operating clock in the range of 100KHz ~ 6MHz.

A liquid crystal display device according to the present invention for achieving the above object includes a liquid crystal display panel having a plurality of unit pixels, a gate driver and a data driver for driving the liquid crystal display panel, the gate driver and the data driver And a driving voltage generator configured to provide driving power to the driving voltage generator, wherein the driving voltage generator receives a power supply voltage and generates and outputs a common voltage consisting of a positive pulse and a negative pulse, and a signal of the common voltage. And a high frequency application unit for generating and outputting a high frequency common voltage in which the positive and negative pulses are the main pulses and the high frequency signals are the sub pulses.

In the RGB mode, the main clock input from the outside is used, and in the CPU mode, the main clock generated by itself is preferably used.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: receiving a power supply voltage and generating and outputting a common voltage consisting of a positive pulse and a negative pulse; Generating and outputting a high frequency common voltage that matches the signal and sets the positive and negative pulses as the main pulse and the high frequency signal as the sub pulse; And applying to a common electrode of the liquid crystal display panel.

It is preferable to apply a pixel voltage signal to the pixel electrode of the liquid crystal display panel such that polarities are inverted for each data line.

Preferably, the pixel voltage signal is applied to the pixel electrode of the liquid crystal display panel so that polarity is inverted for each frame.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like reference numerals in the drawings refer to like elements.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram illustrating a unit pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display includes a liquid crystal display panel 300, a gate driver 400, a data driver 500, a DC / DC converter 700, a driving voltage generator 800, and a gray voltage. The unit 900 and a signal control unit 600 for controlling them.

The liquid crystal display panel 300 includes a plurality of unit pixels arranged in a matrix form. The unit pixel is defined by a cross region of a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm formed in a horizontal and vertical direction, and includes a switching element Q and a liquid crystal capacitor connected thereto. Clc) and a storage capacitor (Cst).

Referring to FIG. 2, the liquid crystal display panel 300 includes a lower substrate 100 on which a switching element Q, a gate line G, a data line D, and a pixel electrode 190 are arranged, and a black matrix ( The upper substrate 200 having the color filter 230 and the common electrode 270 arranged thereon and a liquid crystal layer (not shown) filled between the two substrates 100 and 200.

The switching element Q includes amorphous silicon, polysilicon, or the like as a channel layer, and includes a thin film transistor (TFT) including a gate electrode, a source electrode, and a drain electrode. It is effective to use Here, the gate electrode is connected to the gate lines G1 to Gn, the source electrode is connected to the data lines D1 to Dm, and the drain electrode is the pixel electrode 190, the liquid crystal capacitor Clc, and the storage capacitor Cst. Connected with

The liquid crystal capacitor Clc is configured to have a constant capacitance by using a pixel electrode 190 connected to the switching element Q and a common electrode 270 opposite to each other, and a liquid crystal layer between the two terminals as a dielectric. do.

The sustain capacitor Cst is configured such that a gate line G or a separate sustain line (not shown) and the pixel electrode 190 overlap with an insulator interposed therebetween. The sustain capacitor Cst includes a voltage corresponding to a difference between a gate voltage applied through the gate line G and a gray voltage applied to the pixel electrode 190, or a common voltage and a pixel electrode applied through a separate sustain line. The voltage corresponding to the difference of the gray scale voltage applied to the battery 190 is charged to maintain the image signal transmitted to the specific pixel for a predetermined frame (usually one frame). Of course, the sustain capacitor Cst, which plays an auxiliary role of the liquid crystal capacitor Clc, may be omitted.

The DC / DC converter 700 receives a predetermined voltage and generates and outputs a liquid crystal driving voltage AVDD.

The driving voltage generator 800 may include a gate-on voltage Von for turning on the switching element Q, a gate-off voltage Voff for turning off the switching element Q, and driving. A liquid crystal driving voltage AVDD and a common electrode for generating a reference voltage VDD (not shown) for operating a chip and outputting the same to the gate driver 400 and generating a gray voltage applied to the pixel electrode 190. The common voltage Vcom applied to the data source 270 is generated and output to the data driver 500.

The gray voltage generator 900 generates a gray voltage (or gamma voltage) using the liquid crystal driving voltage AVDD applied from the driving voltage generator 800, and outputs the gray voltage (or gamma voltage) to the data driver 500.

The gate driver 400 is connected to each gate line G1 to Gn of the liquid crystal display panel 300 and includes a gate on voltage Von and a gate off voltage Voff from the driving voltage generator 800. Analog signals are sequentially applied to the gate lines G1 to Gn as gate signals. The gate driver 400 includes a plurality of stages in which shift resistors are arranged in a line.

The data driver 500 is connected to each of the data lines D1 to Dm of the liquid crystal display panel 300, and the grayscale voltage applied from the gray voltage generator 900 is converted into the image signals R ', G', and B '. It modulates to suit and apply it sequentially to each data line D ₁ to D _m as a data signal.

The signal controller 600 may include image signals R, G, and B and control signals thereof input from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock. The image signal and the control signal are processed in accordance with the operating conditions of the liquid crystal display panel 300 in response to the signal MCLK, the data enable signal DE, and the like, and then the gate control signal CONT1 and the data control signal CONT2. ) And the voltage part control signal CONT3.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal GS), and a gate clock signal CPV for controlling the output timing of the gate-on pulse. And an output enable signal OE which defines the width of the gate on pulse.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B ', and the data lines D1 to Dm. Signal LOAD or TP, an inverted signal (RVS) that inverts the polarity of the data voltage with respect to the common voltage (Vcom) (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage"); Data clock signal HCLK and the like.

Next, the driving voltage generator provided in the liquid crystal display according to the present embodiment will be described in detail as follows.

3 is a block diagram schematically illustrating a driving voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the driving voltage generator 800 includes a gate on voltage generator 810, a gate off voltage generator 820, a common voltage generator 830, and a high frequency applying unit 840. .

The gate on voltage generator 810 generates and outputs a gate on voltage Von using a power supply voltage input from the DC / DC converter 700, that is, a liquid crystal driving voltage AVDD, and generates the gate off voltage. The unit 820 generates and outputs a gate off voltage Voff.

The common voltage generator 830 modulates a power supply voltage received from the DC / DC converter 700, that is, a liquid crystal driving voltage AVDD, to form a common voltage (+) and a negative voltage (−). Vcom) is generated and output, and the high frequency applying unit 840 applies an internally generated high frequency signal or a high frequency signal input from the outside to the common voltage signal Vcom of the common voltage generator 830 to generate the two signals. The waveform outputs a matching high frequency common power supply (V _H -com).

A process of generating the common power Vcom and the high frequency common power V _H -com will be described with reference to FIGS. 4 and 5 as follows. 4 is a waveform diagram illustrating a process of generating a common power supply in the liquid crystal display according to the present embodiment, and FIG. 5 is a waveform diagram illustrating a process of generating a high frequency common power in the liquid crystal display according to the present embodiment.

First, the liquid crystal driving voltage AVDD output from the DC / DC converter 700 is input to the common voltage generator 830. The liquid crystal driving voltage AVDD has a constant voltage, that is, a voltage level of + V ₁ as shown in FIG.

The common voltage generator 830 modulates the input liquid crystal driving voltage AVDD to generate a common voltage Vcom in which positive and negative pulses swing up and down. do. The common voltage Vcom may be generated by various conventional methods, but it is effective to use a pulse width modulation (PWM) method.

For example, it generates a reference pulse signal that is used in pulse width modulation. The reference pulse signal has a period of T ₁ , as shown in FIG. 4B, and has a change width of Δt to adjust the pulse width. In this case, the duty ratio is preferably about 50%, and the duty ratio is adjusted by changing Δt.

The liquid crystal driving voltage AVDD is pulse-width modulated using the reference pulse signal to generate a first modulated signal Vcom ₁ having a square wave shape as shown in FIG. 4C. Subsequently, the first modulated signal Vcom ₁ is inverted and then shifted by one clock to generate a second modulated signal Vcom ₂ having a square wave shape as shown in FIG. 4C. When the waveforms of the modulated signal Vcom ₁ and the second modulated signal Vcom ₂ are matched, a common voltage Vcom is generated.

Therefore, the common power supply Vcom is output in the form of a square wave swinging at a period of T ₁ while having a positive pulse of + V ₁ and a negative pulse of −V ₁ , as shown in FIG. 4C.

The high frequency applying unit 840 applies a high frequency signal V _HF to the input common voltage signal Vcom, and generates and outputs a high frequency common power source V _H -com in which the waveforms of the two signals match.

In this case, the high frequency applying unit 840 may use a high frequency signal applied from the outside of the system, and may use a high frequency signal generated internally in the system.

That is, in the RGB mode in which an image signal is received and displayed on the screen in real time, the main clock MLCK applied together with the image signal may be used as a high frequency signal, and the changed portion may be determined by determining whether or not to change the content of the image signal. In this case, a new screen is displayed, and in the case of the CPU mode displaying a conventional screen when there is no change, the main clock MLCK generated by itself can be used as a high frequency signal. Of course, the high frequency signal is not limited to a specific signal, and any signal having high frequency characteristics, for example, any one of various control signals generated by the signal controller 600 may be used as the high frequency signal.

The high frequency signal V _HF is output in the form of a square wave swinging at a period of T _{2 with} a positive pulse of + V ₂ and a negative pulse of −V ₂ , as shown in FIG. 5A. V _HF may generate an operation clock high enough to generate a plurality of sub pulses within a main pulse period of the common voltage signal Vcom, that is, within a period between a positive pulse and a negative pulse. It is desirable to have. For example, the operating clock of the high frequency signal V _HF is preferably in the range of about 100 KHz to 6 MHz.

Therefore, the high frequency common voltage V _H -com output from the high frequency applying unit 840 is the main pulse swinging at a period of T ₁ by the pulse component of the common voltage signal as shown in FIG. 5 (b). and a sub pulse swinging at a period of T ₂ by a pulse component of a high frequency signal in a section of a pulse.

The generated high frequency common voltage V _H -com is applied to the common electrode 270 of the liquid crystal display panel 300 and inverts the polarity of the common electrode 270 with time. Particularly, since the high frequency common voltage V _H -com has a high frequency pulse which is a sub pulse in the same polarity, that is, a positive pulse and a negative pulse period, the potential changes frequently, so that a DC component having the same potential is applied. The time is so short that the residual DC amount of the unit pixel is minimized.

Meanwhile, it is preferable that a pixel voltage signal is applied to the pixel electrode 190 of the liquid crystal display panel 300 according to the present embodiment in a line inversion method or a frame inversion method. The high frequency common power source V _H -com having the high frequency characteristics is preferably applied to the common electrode 270 of the panel 300.

6 illustrates a liquid crystal display panel according to the present exemplary embodiment driven by a line inversion method, and FIG. 7 illustrates a liquid crystal display panel according to the present exemplary embodiment driven by a frame inversion method.

Referring to FIG. 6, when the liquid crystal display panel 300 is driven in a line inversion scheme, as illustrated in (a), a positive pixel voltage signal is applied to pixel electrodes of an odd data line during an odd frame. At the same time, a negative pixel voltage signal is applied to the pixel electrodes of the even data line, and as shown in (b), a negative polarity (-) is applied to the pixel electrodes of the odd data line during the even frame following the odd frame. A positive pixel voltage signal is applied to the pixel electrodes of the even data line.

Referring to FIG. 7, when the liquid crystal display panel 300 is driven in a frame inversion scheme, as illustrated in (a), a positive pixel voltage signal is applied to all pixel electrodes during an odd frame. As in b), a negative pixel voltage signal is applied to all pixel electrodes during the even frame following the odd frame.

8 is a waveform diagram illustrating a pixel voltage and a common voltage applied to a unit pixel of the liquid crystal display panel according to the exemplary embodiment.

Referring to FIG. 8, a pixel voltage signal whose polarity is inverted for each horizontal line or frame is applied to the pixel electrode 190 of the unit pixel, and a common voltage signal is applied to the common electrode 270 of the unit pixel. do. In particular, the common voltage signal includes a positive pulse and a negative pulse swinging at a period of T ₁ as described above, and the positive and negative pulses include a high frequency pulse swinging at a period of T ₂ . .

As such, a pixel voltage signal having polarity inverted for each line or frame is applied to the unit pixels of the liquid crystal display panel 300, and a common voltage signal having high frequency characteristics and inverted polarity is applied to change the potential constantly. Therefore, since the time when the DC component of the same potential is applied is very short and the amount of residual DC in the unit pixel is minimized, no afterimage occurs.

As mentioned above, although this invention was demonstrated with reference to the above-mentioned Example and an accompanying drawing, this invention is not limited to this, It is limited by the following claims. Therefore, it will be apparent to those skilled in the art that the present invention may be variously modified and modified without departing from the technical spirit of the following claims.

As described above, in the present invention, the common electrode of the unit pixel is provided with a common voltage signal having high frequency characteristics and inverted polarity, and the pixel electrode of the unit pixel is inverted in a line inversion or frame inversion manner. An image voltage signal is provided. Therefore, since the application time of the DC component is shortened by the high frequency component of the common voltage signal, the residual DC amount is reduced, and the residual DC is also discharged and erased by the common voltage signal and the image voltage signal whose polarity is inverted, thereby minimizing the overall residual DC. Afterimages do not appear.

Claims (10)

A common voltage generator which receives a power supply voltage and generates and outputs a common voltage consisting of a positive pulse and a negative pulse; Matching a high frequency signal to the signal of the common voltage to generate and output a high frequency common voltage in which the positive and negative pulses are the main pulses, and the high frequency signal is the sub pulses. And a high frequency applying unit. The method according to claim 1, The high frequency signal has a power clock of 100KHz ~ 6MHz range power module of the liquid crystal display device. A liquid crystal display panel having a plurality of unit pixels; A gate driver and a data driver for driving the liquid crystal display panel; A driving voltage generator configured to provide driving power to the gate driver and the data driver; The driving voltage generator includes a common voltage generator that receives a power supply voltage and generates and outputs a common voltage consisting of a positive pulse and a negative pulse; A high frequency signal matching a high frequency signal to the signal of the common voltage, generating and outputting a high frequency common voltage in which the positive and negative polarity pulses are the main pulses and the high frequency signal as the sub pulses. And an applying unit. The method according to claim 3, The high frequency signal has an operating clock in the range of 100KHz ~ 6MHz. The method according to claim 3, In the RGB mode, a high frequency signal uses a main clock input from the outside, and in the CPU mode, a main clock generated by itself is used. Receiving a power supply voltage and generating and outputting a common voltage consisting of a positive pulse and a negative pulse; Matching a high frequency signal to a signal of the common voltage, generating and outputting a high frequency common voltage in which the positive and negative pulses are the main pulses, and the high frequency signal is the sub pulses; Wow, And applying the high frequency common voltage to a common electrode formed on the liquid crystal display panel. The method according to claim 6, The high frequency signal has a driving clock in the range of 100KHz ~ 6MHz. The method according to claim 6, In the RGB mode, a main clock input from the outside is used as the high frequency signal, and a main clock generated by itself is used in the CPU mode. The method according to claim 6, And a pixel voltage signal is applied to the pixel electrode of the liquid crystal display panel such that polarities are inverted for each data line. The method according to claim 6, And a pixel voltage signal is applied to the pixel electrode of the liquid crystal display panel such that the polarity is inverted for each frame.

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