KR20070001476A - Tft gate driving circuit for liquid crystal display and liquid crystal display comprising the same - Google Patents

Abstract

A liquid crystal display and a TFT gate driving circuit thereof are provided to reduce manufacturing cost of the liquid crystal display device by compensating a kick-back voltage by coupling control and output terminals of an output buffer with a capacitor. A TFT(Thin Film Transistor) gate driving circuit of a liquid crystal display includes a level shifter(220) and an output buffer(230). The level shifter changes the voltage level of an input signal and outputs the result. The output buffer includes at least one output buffers, which receive the resultant signal and output the received signal for a predetermined time interval. The output buffer decreases the voltage level of the level-changed signal, before the voltage level of the level-changed signal is shifted down. The output buffer includes a capacitor, which is connected between the output terminal and the control terminal.

Description

TFT Gate Driving Circuit for Liquid Crystal Display and Liquid Crystal Display Comprising the Same}

1 is an equivalent circuit diagram of a unit pixel in a general liquid crystal display device.

FIG. 2 is a waveform diagram of a voltage compensated for a kickback voltage applied to the gate of FIG. 1.

3 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a schematic block diagram of a liquid crystal display gate driving circuit unit according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an output buffer of a gate driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a graph illustrating waveforms in an output buffer of a gate driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: liquid crystal panel 200: gate driving circuit portion

210: shift register portion 220: level shifter portion

230: output buffer unit 231: output buffer

232: input stage 233: control stage

234: output stage 300: source driving circuit portion

400: gate driving voltage generator 500: timing controller

600: gradation voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor gate driving circuit and a liquid crystal display of a liquid crystal display, and more particularly, to a thin film transistor gate driving circuit and a liquid crystal of a liquid crystal display for implementing kickback voltage compensation simply by changing the configuration of an output buffer of the driving circuit. It relates to a display device.

A liquid crystal display (LCD) applies an electric field to a liquid crystal material having an anisotropy dielectric constant injected between two substrates, and adjusts the intensity of the electric field to control the amount of light transmitted through the substrate, thereby providing a desired image. It is a device to display.

A plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed on the substrate of the liquid crystal display device, and one pixel is defined in an area surrounded by the gate lines and the data lines. Here, a thin film transistor (hereinafter, referred to as TFT) is formed at a portion where each gate line and data line cross each other.

1 is an equivalent circuit for a unit pixel in a general liquid crystal display. As shown in FIG. 1, the gate electrode g, the source electrode s, and the drain electrode d of the TFT are connected to the gate line Gn, the data line Dm, and the pixel electrode P, respectively. A liquid crystal material is formed between the pixel electrode P and the common electrode Com, which is equivalently represented as a liquid crystal capacitor Clc. A storage capacitor Cst is formed between the pixel electrode P and the front gate line Gn-1, and a parasitic capacitor due to misalignment between the gate electrode g and the drain electrode d. Cgd).

Such a liquid crystal display device is a gate signal for driving a gate electrode g connected to a gate line Gn to display an image. After the TFT is turned on by applying a gate-on voltage Von, the image signal is converted into a gate signal. A data voltage for display is applied to the pixel electrode P. Then, the data voltage is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the pixel electrode P, respectively, and an electric field is formed by the potential difference between the pixel electrode P and the common electrode Com.

On the other hand, when the TFT is turned on, the voltage applied to the liquid crystal capacitor Clc and the storage capacitor Cst must continue to be maintained even after the TFT is turned off, but between the gate electrode g and the drain electrode d. Due to the parasitic capacitor Cgd at, when the gate off voltage Voff is applied to the gate electrode g of the TFT, the absolute value of the voltage applied to the pixel electrode is lowered as the gate voltage is lowered.

As such, a voltage for lowering the voltage of the pixel electrode is called a kick-back voltage, and the kickback voltage Vk is obtained by the following equation.

When the kickback voltage Vk becomes large, the voltage applied to the liquid crystal capacitor Clc of the pixel changes, thereby changing the displayed image, thereby causing problems such as flickering and image sticking of the image. .

The kickback voltage Vk is reduced by lowering the gate-on voltage Von, and at the same time, the image display capability of the pixel is also reduced. Accordingly, the kickback voltage is realized by implementing the waveform as shown in FIG. 2 by lowering the gate-on voltage Von before the falling transition time when the voltage of the gate electrode g changes from the gate-on voltage Von to the gate-off voltage Voff. There are many ways to compensate.

However, the implementation of the gate-on voltage (Von) waveform, such as the waveform shown in FIG. 2 is generally implemented by making a separate kickback voltage compensation circuit, which requires a separate transistor, a resistor and a capacitor. Therefore, the manufacturing of the liquid crystal display device is complicated, and there is a problem that leads to an increase in the manufacturing cost of the liquid crystal display device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide a thin film transistor gate driving circuit and a liquid crystal display device of a liquid crystal display device, which implements a kickback voltage compensation simply by changing a configuration of an output buffer of a driving circuit. do.

According to an aspect of the present invention for achieving the object of the present invention, an output having a level shifter for changing the level of the input signal and outputting, and at least one output buffer for receiving the level-changed signal for a predetermined time And a buffer unit, wherein the output buffer lowers and outputs the voltage before the level-changed signal falls down and provides the thin film transistor gate driving circuit of the liquid crystal display.

According to another aspect of the present invention for achieving the object of the present invention, a plurality of gate lines formed in the column direction and a plurality of data lines formed in the row direction, the gate line and the data line is formed at the intersection portion of the gate electrode and A liquid crystal panel including a plurality of thin film transistors each having a source electrode connected to the gate line and the data line, a level shifter for varying and outputting an input signal level, and receiving the level changed signal to the gate line for a predetermined time; And a gate driving circuit unit including an output buffer unit having one or more output buffers, wherein the output buffer outputs a voltage lowered before the level-changed signal falls.

The output buffer is characterized by having a capacitor between the output terminal and the control terminal.

The output buffer delays a signal input to the input terminal for a predetermined time and outputs a signal corresponding to the input signal when the signal input to the control terminal rises and transitions.

The output buffer is characterized in that the three-phase buffer for lowering the voltage of the signal before the falling transition.

EMBODIMENT OF THE INVENTION Hereinafter, with reference to an accompanying drawing, embodiment of this invention is described in detail.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. In the liquid crystal display according to the exemplary embodiment of the present invention illustrated in FIG. 3, the liquid crystal panel 100, the gate driving circuit unit 200, the source driving circuit unit 300, the gate driving voltage generator 400, and the timing controller 500 may be used. And a gray voltage generator 600.

The timing controller 500 is provided with an R (red), G (green), B (blue) data signal, a vertical synchronization signal (Vsync) that is a frame discrimination signal, and a horizontal synchronization signal from a graphic controller (not shown) outside the LCD module. Hsync) and the main clock signal CLK are received to generate and output a digital signal for driving the gate driving circuit unit 200 and the source driving circuit unit 300.

The timing signal output from the timing controller 500 to the gate driving circuit unit 200 includes a vertical start signal (hereinafter referred to as a "Vstart signal") for instructing the gate line to start applying the gate signal, and the gate signal to the gate signal. A gate clock signal (hereinafter referred to as a 'CPV signal') for sequentially applying to the gate line and a gate on enable signal (hereinafter referred to as an 'OE signal') to enable the output of the gate driving circuit unit 200. And control signals.

The timing signal output from the timing controller 500 to the source driver circuit unit 300 includes a horizontal start signal Hstart and a source driver circuit unit 300 which command a driving start of the R, G, and B data signals received from the graphic controller. There is a control signal such as a signal LOAD for commanding the application of a data signal converted into an analog signal) and a horizontal clock signal HCLK for data shift in the source driving circuit unit 300.

The gate driving voltage generator 400 may include a gate on voltage Von and a gate off voltage Voff used as a gate signal, and a common voltage Vcom serving as a reference for the data voltage in the TFT. Will output

In this case, the gate driving circuit unit 200 receives the CPV signal and the Vstart signal from the timing controller 500, and receives the voltages Von, Voff, and Vcom from the gate driving voltage generator 400, and thus the liquid crystal panel 100. The TFT is controlled such that a voltage to be applied to each pixel on the i) is transferred to the corresponding pixel.

The gate driving circuit unit 200 receives a CPV signal and an 0E signal output from the timing controller 500 and uses a gate-on voltage Von that is synchronized with the two signals CPV and OE as a gate signal. ... are sequentially applied to Gn) to turn on and off the thin film transistor of the liquid crystal panel 100. The gate signal toggles to a high level in synchronization with the falling transition of the OE signal and then toggles to a low level in synchronization with the rising transition of the next OE signal.

The gray voltage generator 600 generates an equal gray voltage according to the number of bits of the RGB data received from the graphic controller, and transmits the gray voltage to the source driving circuit 300.

The source driving circuit unit 300 applies a data voltage to all data lines D1, D2,..., Dn in accordance with a signal output from the timing controller 500 in synchronization with driving of the gate driving circuit unit 200. do. Assuming that the data line is not significantly affected by the delay of the data line, the data voltage is charged in the pixel during the period in synchronization with the high period of the gate-on voltage Von.

The liquid crystal panel 100 includes a plurality of gate lines G1, G2, ..., Gn formed in a column direction, a plurality of data lines D1, D2, ..., Dn formed in a row direction, and the gate line. The thin film transistor may include a plurality of thin film transistors formed at portions where the data lines intersect to connect the gate electrode and the source electrode to the gate line and the data line, respectively.

The liquid crystal panel 100 receives a data voltage and a gate signal output from the source driving circuit unit 300 and the gate driving circuit unit 200 to display an image for each frame.

In the liquid crystal display having the above structure, the gate driving circuit unit 200 according to the embodiment of the present invention changes the configuration of the output buffer so that the gate signal is changed from the gate on voltage Von to the gate off voltage Voff. The kickback voltage is simply compensated by lowering the voltage before the falling transition time and applying it to the gate line.

Hereinafter, operations of the liquid crystal display gate driving circuit unit according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

The liquid crystal display gate driving circuit unit 200 according to the exemplary embodiment of the present invention shown in FIG. 4 includes a shift register unit 210, a level shifter unit 220, and an output buffer unit 230.

The shift register unit 210 receives input control signals DI / O, U / D and CPV signals from the timing controller 500, and corresponds to the input control signals DI / O, U / D and CPV signals. The received signals are sequentially applied to the shift lines S1, S2, ..., Sn.

When the control pulse (DI / O) is generated according to the Vstart signal received from the timing controller 500, the shift register unit 210 generates the control pulse (DI / O) in synchronization with the rising transition time of the CPV signal. The shift lines S1, S2, ..., Sn are shifted by one line.

Here, the shift lines S1, S2, ..., Sn are lines that correspond one-to-one to the gate lines D1, D2, ..., Dn, respectively, and the shift register unit 210 is one at a time. Only the shift line is turned on, and the remaining shift line is turned off so that only one gate line can be selected to output the gate-on voltage Von.

The level shifter unit 220 changes the level of the on / off signal output from the shift register unit 210 to the shift lines S1, S2, ..., Sn, and thereby changes the level lines L1, L2, ... , Ln). The level change is implemented based on the gate-on voltage Von and the gate-off voltage Voff received from the gate driving voltage generator 400. Since the implementation of such a level change is a general content, description thereof is omitted.

The output buffer 230 receives the on / off signal output from the level shifter 220 to the level lines L1, L2, ..., Ln, and gates the on / off signal for a predetermined time. Applies to (G1, G2, ..., Gn).

The output buffer unit 230 includes an output buffer for each line corresponding to the level lines L1, L2, ..., Ln and the gate lines G1, G2, ..., Gn.

The output buffer 231 according to the embodiment of the present invention shown in FIG. 5 has a level line L1, L2, ..., Ln and a gate line G1, G2 at the input terminal 232 and the output terminal 234, respectively. , ..., Gn) are connected, and a control signal (hereinafter referred to as a Ctrl signal) for delaying the CPV signal for a predetermined time is input to the control terminal 233. Also, the kickback voltage compensation capacitors Ck1, Ck2, ..., Ckn are connected between the control terminal 233 and the output terminal 234.

Here, the output buffer 231 delays the input signal for a predetermined time and outputs a signal corresponding to the input signal when the Ctrl signal rises and transitions.

Hereinafter, referring to the waveform output from the output buffer 231 having the above configuration with reference to FIG. 6, the input gate-on voltage Von is output as it is when the Ctrl signal rises, but the Ctrl signal falls. When the output terminal 234 is floated to the control terminal 233 due to the kickback voltage compensation capacitors Ck1, Ck2, ..., Ckn connected between the output terminal 234 and the control terminal 233 The gate-on voltage Von is lowered and output.

That is, referring to the operation of the gate driving circuit unit 200 according to the embodiment of the present invention, the shift register unit 210 controls the control pulses (DI / O) to the shift lines S1, S2, ..., Sn. Is output by shifting line by line, and accordingly, the level shifter 220 sequentially applies a level-changed signal to the level lines L1, L2, ..., Ln, and the output buffer unit 230 The voltage is lowered before the level shifted signal is outputted to the gate lines G1, G2, ..., Gn.

This output waveform is similar to the waveform compensated for the kickback voltage shown in FIG. 2, so that the voltage is lowered before the gate signal falls, thus reducing the kickback voltage.

In the exemplary embodiment of the present invention, the kickback voltage is compensated by connecting a kickback voltage compensation capacitor between the output terminal and the control terminal of the output buffer. However, a three-phase buffer whose voltage gradually decreases before the falling transition time is used as the output buffer. It can also compensate for kickback voltage. Since the content of such a three-phase buffer is conventional content, description thereof is omitted.

The scope of the present invention is not limited to each embodiment described above, but all changes and improvements made by those skilled in the art using the basic concept of the present invention defined in the claims also belong to the scope of the present invention.

As described above, the thin film transistor gate driving circuit of the liquid crystal display according to the embodiment of the present invention is configured by using a three-phase buffer in which the output buffer of the driving circuit is gradually dropped before the falling transition time, or controlling the output buffer. Kickback voltage compensation can be implemented simply by connecting capacitors to the stage and output stages. Therefore, the kickback voltage compensation circuit does not need to be manufactured separately, which simplifies the manufacturing process of the liquid crystal display and reduces the manufacturing cost.

Claims (7)

A level shifter for changing and outputting the level of the input signal; An output buffer unit having one or more output buffers for receiving the level-changed signal and outputting the signal for a predetermined time; And the output buffer lowers and outputs the voltage before the level-changed signal falls. The thin film transistor gate driving circuit of claim 1, wherein the output buffer includes a capacitor between an output terminal and a control terminal. The liquid crystal display device according to claim 2, wherein the output buffer delays a signal input to the input terminal for a predetermined time and outputs a signal corresponding to the input signal when the signal input to the control terminal rises and transitions. Thin film transistor gate driving circuit. The thin film transistor gate driving circuit of claim 1, wherein the output buffer is a three-phase buffer for lowering a voltage of a signal before falling. A plurality of gate lines formed in a column direction and a plurality of data lines formed in a row direction, and a plurality of thin film transistors formed at a portion where the gate line and the data line cross each other, the gate electrode and the source electrode are connected to the gate line and the data line, respectively. With a liquid crystal panel A gate shifter circuit unit including a level shifter unit for changing a level of an input signal and outputting the output signal, and an output buffer unit having one or more output buffers for receiving the level-changed signal and applying it to the gate line for a predetermined time; And the output buffer lowers and outputs the voltage before the level-changed signal falls. 6. The liquid crystal display of claim 5, wherein the output buffer includes a capacitor between an output terminal and a control terminal. 6. The liquid crystal display device according to claim 5, wherein the output buffer is a three-phase buffer which lowers the voltage of the signal before falling.

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