KR101313650B1 - Circuit for compensating clock signal of liquid crystal display - Google Patents

Abstract

The present invention relates to a technique for reducing a flicker phenomenon caused by a clock signal supplied to a GIP panel of a liquid crystal display device. This invention comprises a timing controller for outputting clock signals CK1 to CK4 and clock signal FLK; A GPM integrated device configured to supply a gate high signal of a form modulated using the clock signal FLK and a compensation signal for compensating a distorted portion of the clock signals CLK1 to CLK4; A switching unit configured to separately output the modulated gate high signal and the compensation signal in synchronization with an even and odd clock signal; In synthesizing the odd clock signals CK1 and CK3 and the odd gate high signal, the distorted intermediate portion is compensated using the compensation signal, and in synthesizing the even clock signal CK2 and CK4 and the even gate high signal. After compensating for the distorted intermediate portion using the compensation signal, the level is increased by an odd and even level shift unit for generating clock signals CLK1 and CLK3 and CLK2 and CLK4 to be supplied to the GIP panel.

Description

CIRCUIT FOR COMPENSATING CLOCK SIGNAL OF LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display device according to the prior art.

2 is a block diagram of generation of a GPM clock signal according to the prior art;

3A to 3D are waveform diagrams of clock signals CK1-CK4 in FIG.

4 (a)-(c) are waveform diagrams of input / output signals of the GM integrated device of FIG. 2;

5A to 5D are waveform diagrams of clock signals CLK1-CLK4 in FIG.

6 is a block diagram of a clock signal correction circuit of the liquid crystal display device according to the present invention;

FIG. 7A is a waveform diagram of the clock signal FLK in FIG. 6; FIG.

7 (b) and 7 (c) are output waveform diagrams of the T flip-flop in FIG. 6;

8 (a)-(d) are waveform diagrams of the compensated clock signals CLK1-CLK4 according to the present invention.

DESCRIPTION OF THE REFERENCE SYMBOLS

61 timing controller 62 GPM integrated device

63: switching unit 64: level shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing flicker caused by a clock signal supplied to a GIP (GIP: Gate In panel) panel of a liquid crystal display, and particularly, to reduce flicker by correcting a GPM clock signal supplied to a GIP panel. A clock signal correction circuit of a liquid crystal display device.

In general, the liquid crystal display (LCD) has been gradually expanded to office automation equipment, audio / video equipment, and the like due to features such as light weight, thinness, and low power consumption driving.

1 is a block diagram of a liquid crystal display device according to the prior art, as shown therein, a system 11 for supplying video data, a vertical / horizontal synchronization signal and a clock signal; A liquid crystal panel 15 driven by a data signal and a gate-on signal to display an image; A gate driver 13 supplying a gate-on signal to each gate line of the liquid crystal panel 15; A data driver 14 for supplying the data signal to each data line of the liquid crystal panel 15; A timing controller 12 outputting a control signal for controlling the driving of the gate driver 13 and the data driver 14; It includes a DC / DC converter 16 for generating various driving voltages required by the liquid crystal panel 15. The operation thereof will be described as follows.

The liquid crystal panel 15 includes a plurality of liquid crystal cells Clc arranged in a matrix at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn.

The graphics processing circuit of the system 11 converts analog data into digital video data RGB and adjusts the resolution and color temperature of the digital video data RGB. The digital video data RGB and the vertical / horizontal synchronization signal and the clock signal output from the system 11 are supplied to the timing controller 12.

The timing controller 12 controls the gate control signal GDC and the data driver 14 for controlling the gate driver 13 using the vertical / horizontal synchronization signal and the clock signal supplied from the system 11. To generate a data control signal DDC. In addition, the timing controller 12 samples the digital video data RGB input from the system 11 and rearranges the same, and supplies the data to the data driver 14.

The data driver 14 converts the digital video data RGB into a data voltage (analog gamma compensation voltage) corresponding to the gray scale value in response to the data control signal DDC from the timing controller 12. The data voltage is supplied to the data lines D1 to Dm on the liquid crystal panel 15.

The gate driver 13 sequentially supplies scan pulses (gate pulses) to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 12, thereby supplying data. Horizontal lines of the liquid crystal panel 15 are selected.

The DC / DC converter 16 generates a high potential common voltage VDD voltage, VCOM voltage, gate on (or high) voltage VGH, and gate off (or low) voltage VGL using the VCC voltage from the system 11. do.

For reference, in the above description, the data driver 14 and the gate driver 13 are separately installed from the liquid crystal panel 15. However, in recent years, each of them is COG (Chip On Glass) or COF (Chip On). There is a tendency to be directly mounted on the liquid crystal panel 15 by using a packaging technology such as a film or a chip on flexible printed circuit.

2 is a generation block diagram of a GPM clock signal according to the prior art, as shown therein, a timing controller 21 for outputting clock signals CK1 to CK4 and a clock signal FLK of a predetermined level; A gate pulse modulation IC (GPM) 22 which outputs a gate high signal Vgh_m of a modulated form using a clock signal FLK supplied from the timing controller 21; And a level shifter 23 for synthesizing the clock signal FLK and the gate high signal Vgh_m, increasing the level of the synthesized signal to generate the clock signals CLK1 to CLK4, and supplying them to the GIP panel. When described with reference to Figures 3 to 5 attached to the action thereof.

The timing controller 21 outputs clock signals CK1 to CK4 having a 3.3V level to the level shifter 22, as shown in FIGS. 3A to 3D, and the clock signal shown in FIG. FLK) is output to the GM integrated device 22.

The GPM integrated device 22 uses the clock signal FLK supplied from the timing controller 21 and the GPM signal GPM as shown in FIG. 4A, as shown in FIG. 4C. A gate high signal Vgh_m having a modulated form of 1V level is generated and output to the level shifter 23.

The level shifter 23 synthesizes the clock signals CK1 to CK4 and the gate high signal Vgh_m, increases the level of the synthesized signal, and increases the 20V level as shown in FIGS. 5A to 5D. The modulated clock signals CLK1 to CLK4 are generated, and the generated clock signals CLK1 to CLK4 are supplied to the GIP panel.

By the way, as shown in (a)-(d) of FIG. 5, it can be seen that the middle portion of each clock signal CLK1 to CLK4, that is, the distortion at the 1H point (the GPM effect appears). The signals CLK1 to CLK4 are generated by the influence of falling edges of adjacent clock signals.

For example, as shown in (b) of FIG. 5, the middle portion of the clock signal clk2 is distorted, which is influenced by the falling edge of the clock signal clk1 as shown in FIG. It occurred.

As described above, in the conventional liquid crystal display, when the GPM clock signal is supplied to the GIP panel, the middle portion of each clock signal is distorted, which causes a problem of flickering.

Accordingly, an object of the present invention is to provide a clock signal correction circuit for correcting a distortion portion by using a compensation signal and a switching element when supplying a GPM clock signal to a GIP panel.

The present invention for achieving the above object is a timing controller for outputting the clock signal (CK1 ~ CK4) and the clock signal (FLK) of a predetermined level; A GPM integrated device configured to supply a gate high signal of a form modulated using the clock signal FLK and a compensation signal for compensating a distorted portion of the clock signals CLK1 to CLK4; A switching unit for separating and outputting the modulated gate high signal and the compensation signal in synchronization with even and odd clock signals; In synthesizing the odd clock signals CK1 and CK3 and the odd gate high signal, the distorted intermediate portion is compensated using the compensation signal, and in synthesizing the even clock signal CK2 and CK4 and the even gate high signal. After compensating for the distorted middle portion using the compensation signal, the level of the synthesized signal is increased to a radix or even level shift unit for generating clock signals CLK1 and CLK3 and CLK2 and CLK4 to be supplied to the GIP panel. It is characterized by the configuration.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a block diagram showing an embodiment of a clock signal correction circuit of a liquid crystal display according to the present invention. As shown therein, a clock signal CK1 to CK4 and a clock signal FLK of a predetermined level are output. A timing controller 61; The gate high signal Vgh_m of the modulated form is output using the clock signal FLK supplied from the timing controller 61, and

A gate pulse modulation IC (GPM) 62 for supplying a compensation signal DCS for compensating for the distorted portions of the clock signals CLK1 to CLK4; A switching unit (63) for separating and outputting the modulated gate high signal (Vgh_m) and the compensation signal (DCS) in synchronization with an even and odd clock signal; In synthesizing the odd clock signals CK1 and CK3 and the odd gate high signal Vgh_m_odd, the distorted intermediate portion is compensated using the compensation signal, and the even clock signals CK2 and CK4 and the even gate high signal ( In synthesizing Vgh_m_even), the distorted middle portion is compensated using the compensation signal, and then the clock signals CLK1, CLK3 and CLK4 are generated and supplied to the GIP panel by increasing the level of the synthesized signals. It consists of the level shift parts 64A and 64B which are mentioned.

),(

)에서 출력되는 신호에 의해 턴온되어 상기 클럭신호(CLK1,CLK3),(CLK2,CLK4)의 왜곡 부분을 보상하기 위한 보상신호(DCS)를 선택적으로 통과시키기 위한 트랜지스터(T1),(T2)와; 상기 지피엠 집적소자(62)로부터 공급되는 게이트하이신호(Vgh_m)를 기수,우수 게이트하이신호(Vgh_m_odd),(Vgh_m_even)로 분리하여 출력하고, 상기 보상신호(DCS)를 공급하기 위한 다이오드(D1∼D3)로 구성하였다.The switching unit (63) includes: a T-type flip-flop (TF / F) for dividing the clock signal (FLK) input from the timing controller (61) by 1/2; Output terminal of the T flip-flop (TF / F)

), (

Transistors T1 and T2 for being selectively turned on by a signal outputted from the first pass through the compensation signal DCS for compensating for the distortion parts of the clock signals CLK1 and CLK3 and CLK4. ; The diode D1 for separating the gate high signal Vgh_m supplied from the GMP element 62 into an odd number, an excellent gate high signal Vgh_m_odd, and Vgh_m_even, and outputting the same, and supplying the compensation signal DCS. D3).

The operation of the present invention configured as described above will be described in detail with reference to FIGS. 7 and 8 as follows.

On the other hand, the timing controller 61, on the one hand, clock signals CK1, CK3, and CK2, CK4 having a predetermined level (e.g., 3.3V level) as shown in FIGS. And output to the odd and excellent level shift units 64A and 64B on the level shifter 64, and on the other hand, the clock signal FLK as shown in FIG. ) And a T flip-flop (TF / F) of the switching unit 63.

The GPM integrated device 62 uses the clock signal FLK supplied from the timing controller 61 and the GPM signal GPM as shown in FIG. 4A, as shown in FIG. 4C. The gate high signal Vgh_m having a predetermined level (for example, 1V) of the modulated form is generated and output to the switching unit 63. In addition, the GPM integrated device 62 includes distortion parts of the clock signals CLK1, CLK3, and CLK2 and CLK4 supplied to the GIP panel through the odd and excellent level shift units 64A and 64B. The compensation signal DCS for compensating for the signal is output to the switching unit 63.

),(

)에 도 7의 (b),(c)와 같이 1/2분주된 신호를 출력하는데, 이들에 의해 트랜지스터(T1),(T2)가 온오프된다. The T-type flip-flop TF / F of the switching unit 63 receives a clock signal FLK as shown in FIG. 7A from the timing controller 61 and outputs its own output terminal (

), (

) Outputs a half-divided signal as shown in FIGS.

Accordingly, the gate high signal Vgh_m of the corresponding period among the gate high signals Vgh_m shown in FIG. 4C output from the GM integrated device 62 is an excellent gate high signal through the diode D2. It is output as (Vgh_m_even).

)에서 출력되는 '하이' 신호에 의해 트랜지스터(T2)가 턴온된다. 이에 따라, 상기 지엠피 집적소자(62)에서 출력되는 보상신호(DCS)가 다이오드(D1), 상기 트랜지스터(T2) 및 다이오드(D2)를 통해 출력된다. At this time, the output terminal of the T-type flip-flop (TF / F)

Transistor T2 is turned on by the 'high' signal. Accordingly, the compensation signal DCS output from the GM integrated device 62 is output through the diode D1, the transistor T2, and the diode D2.

Similarly, the gate high signal Vgh_m of the corresponding period among the gate high signals Vgh_m shown in FIG. 4C output from the GM integrated device 62 is an odd gate high signal through the diode D3. Output as (Vgh_m_odd).

)에서 출력되는 '하이' 신호에 의해 트랜지스터(T1)가 턴온된다. 이에 따라, 상기 지엠피 집적소자(62)에서 출력되는 보상신호(DCS)가 다이오드(D1), 상기 트랜지스터(T1) 및 다이오드(D3)를 통해 출력된다. At this time, the output terminal of the T-type flip-flop (TF / F)

Transistor T1 is turned on by the 'high' signal. Accordingly, the compensation signal DCS output from the GM integrated device 62 is output through the diode D1, the transistor T1, and the diode D3.

Accordingly, the odd level shift unit 64A connects the diode D1, the transistor T1, and the diode D3 to a distorted middle portion of the gate high signal Vgh_m_odd input through the diode D3. Since the compensating signal DCS is input, the distorted portion is normally compensated.

Similarly, the even level shift unit 64B includes the diode D1, the transistor T1, and the diode D2 at a distorted middle portion of the gate high signal Vgh_m_even input through the diode D2. Since the compensating signal DCS inputted through is synthesized, the distorted portion is normally compensated.

As a result, since the clock signals CLK1 to CLK4 supplied to the GIP panel from the level shifter 64 are compensated by the above-described processing, the distorted portions as shown in FIGS. It is output in the normal state without.

As described in detail above, the present invention compensates for the distorted portion by using the compensation signal and the switching element when supplying the GPM clock signal to the GIP panel, thereby preventing the flicker phenomenon from occurring due to the distorted clock signal. It works.

Claims (5)

A timing controller for outputting clock signals CK1 to CK4 and clock signal FLK; A GPM integrated device configured to supply a gate high signal of a form modulated using the clock signal FLK and a compensation signal for compensating a distorted portion of the clock signals CLK1 to CLK4; A switching unit configured to separately output the modulated gate high signal and the compensation signal in synchronization with an even and odd clock signal; In synthesizing the odd clock signals CK1 and CK3 and the odd gate high signal, the distorted intermediate portion is compensated using the compensation signal, and in synthesizing the even clock signal CK2 and CK4 and the even gate high signal. Compensating the distorted middle portion by using the compensation signal, the level is increased by the odd number and even level shift unit for generating clock signals (CLK1, CLK3), (CLK2, CLK4) to be supplied to the GIP panel Clock signal correction circuit of liquid crystal display device. The method of claim 1, wherein the switching unit A T flip-flop for dividing the clock signal FLK by 1/2; Transistor T1 for turning on by the signals output from the two output terminals of the T flip-flop to pass the compensation signal DCS for compensating for the distortion parts of the clock signals CLK1, CLK3 and CLK4. ), (T2); A diode D1 to D3 for separating and outputting the gate high signal Vgh_m supplied from the GM integrated device into an odd number, an excellent gate high signal Vgh_m_odd, and Vgh_m_even, and supplying the compensation signal DCS. Clock signal correction circuit of the liquid crystal display device characterized in that consisting of. 3. The clock signal correction circuit according to claim 2, wherein the output terminal and the inverting output terminal of the T flip-flop are connected to the gates of the transistors (T1) and (T2), respectively. The gate high signal Vgh_m is output to the terminal of the odd gate high signal Vgh_m_odd through the diode D1 and the transistor T1, and is provided through the diode D1 and the transistor T2. A clock signal correction circuit of a liquid crystal display device, characterized in that it is configured to be output to a terminal of an even gate high signal (Vgh_m_even). The clock signal correction circuit of claim 1, wherein the even-numbered even-number shift unit is formed of one chip.

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