KR102306988B1 - A crystal dispplay device - Google Patents

Abstract

In the present invention, there is no need to input a separate signal to generate the odd power supply voltage and the even power supply voltage to the level shifter, and the odd power supply voltage and the even power supply voltage are generated based on the start signal and the driving clock signal input to the level shifter. can be Accordingly, the present invention eliminates the need for a signal line for inputting a separate signal, thereby minimizing the interference between the signal lines by reducing the number of signal lines and reducing costs. In addition, the present invention can secure an area occupied as much as a separate signal line, thereby enhancing the usability of the PCB.

Description

Display device {A CRYSTAL DISPPLAY DEVICE}

The present invention relates to a display device.

A display device is a device that displays an image or information. Among display devices, a liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field.

The liquid crystal display includes a liquid crystal display panel in which pixels defined by a plurality of gate lines and a plurality of data lines are arranged in a matrix, and driving circuits for driving the liquid crystal display panel.

A gate driving circuit and a level shifter for driving the gate driving circuit are provided to select a pixel of the liquid crystal display panel as one of the driving circuits. The gate driving circuit generates a gate signal according to signals provided from the level shifter and is supplied to each pixel of the liquid crystal display channel, and each pixel of the liquid crystal display panel is selected by the gate signal.

A plurality of signals GST, On_CLK, Off_CLK, and EO are input to the level shifter to generate signals provided from the level shifter. Accordingly, four signal lines corresponding to the four signals are connected to the input terminal of the level shifter.

However, since many signal lines are connected to the level shifter, interference occurs between the signal lines, so that layout is difficult or cost is increased.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems.

Another object of the present invention is to provide a display device capable of reducing the number of signal lines.

According to one aspect of the present invention to achieve the above or other objects, a display device includes a display panel, a level shifter, and a plurality of shift registers. The display panel includes a plurality of pixels defined by intersections of a plurality of gate lines and a plurality of data lines. The level shifter generates a start voltage, first to fourth gate clock signals, a first power voltage, and a second power voltage based on the start signal, the first driving clock signal, and the second driving clock signal. The plurality of shift registers supplies one of the first to fourth clock signals to a corresponding gate line in response to the start voltage. In this case, the first and second power supply voltages may be generated using the start signal and the second driving clock signal.

The effects of the terminal according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, there is no need to input a separate signal to the level shifter in order to generate the odd power supply voltage and the even power supply voltage. A power supply voltage and an even-numbered power supply voltage may be generated. Accordingly, the present invention eliminates the need for a signal line for inputting a separate signal, thereby minimizing the interference between the signal lines by reducing the number of signal lines and reducing costs. In addition, the present invention can secure an area occupied as much as a separate signal line, thereby enhancing the usability of the PCB.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments such as preferred embodiments of the present invention are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention may be clearly understood by those skilled in the art.

1 is a view showing a display device according to the present invention.
FIG. 2 is a block diagram illustrating the level shifter of FIG. 1 .
3 is a block diagram illustrating the level shifter of FIG. 1 in detail.
FIG. 4 is a waveform diagram for driving the level shifter of FIG. 1 .
5 is a block diagram illustrating the gate driving circuit of FIG. 1 in detail.
6 is a diagram illustrating gate signals generated during one frame.
FIG. 7 is a diagram illustrating one of the shift registers of FIG. 5 in detail.
8 is a diagram illustrating a power supply voltage for controlling the pull-down transistors of FIG. 7 .

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and overlapping descriptions thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1 , a liquid crystal display according to the present invention includes a display panel 100 , a printed circuit board (hereinafter referred to as a PCB, 200), a gate driving circuit 300 and a plurality of chip-on films (COF). Film, hereinafter referred to as COF, 400) may be included.

The display panel 100 may be a liquid crystal display panel that displays an image by displacement of liquid crystal molecules included in the liquid crystal layer, but is not limited thereto.

In addition to the COF 400 , a Chip On Board (COB) or a Tape Carrier Package (TCP) may be used, but is not limited thereto.

Hereinafter, for convenience of explanation, the present invention is limited to the COF 400, but the present invention can be equally applied to TCP or COB.

Each of the COFs 400 may include a data driving circuit 410 . In other words, the data driving circuit 410 may be mounted on the COF 400 . Specifically, pins of the data driving circuit 410 may be electrically connected to the COF 400 by bonding.

The display panel 100 may display an image and may be electrically connected to the PCB 200 through a plurality of COFs 400 .

The display panel 100 may include a lower substrate 110 , an upper substrate 120 , and a liquid crystal layer (not shown) formed between the substrates 110 and 120 .

A plurality of pixels P may be defined by crossing the plurality of gate lines GL and the plurality of data lines DL on the lower substrate 110 . Each pixel P may include a thin film transistor (not shown) connected to the gate line GL and the data line DL, and a pixel electrode connected to the thin film transistor. The pixel electrodes formed on each pixel P may be spaced apart from each other.

A color filter formed to correspond to each pixel P and a black matrix for separating the color filters are formed on the upper substrate 120 .

Meanwhile, a common electrode for supplying a common voltage may be formed on any one of the lower substrate 110 and the upper substrate 120 . For example, the common electrode is formed on the upper substrate 120 when the display panel 100 is driven in a vertical electric field method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and an IPS (In Plane Switching) mode. When driven by a horizontal electric field method such as a fringe field switching (FFS) mode, it may be formed on the lower substrate 110 together with the pixel electrode.

The display panel 100 may display an image by adjusting the light transmittance of the liquid crystal layer according to the data voltage applied to each pixel P.

A timing controller 210 , a level shifter 220 , a gamma voltage generator (not shown), and a power voltage generator (not shown) are formed on the PCB 200 .

The power voltage generator may generate various power voltages for use in various devices, for example, the timing controller 210 , the level shifter 220 , the gate driving circuit 300 , the data driving circuit 410 , and the gamma voltage generator. have. For example, the power supply voltage includes VDDH, HVDD, VSSH, VCC, and the like. VCC may be used as a driving voltage for driving the timing controller 210 , the gate driving circuit 300 , the data driving circuit 410 , and the like.

The timing controller 210 generates the first gate control signals GST, On_CLK, and OFF_CLK based on the timing control signals Vsync, Hsync, DE, DCLK, etc. input from the outside while generating the data control signals SSP, SSC, SOE, POL, etc.) may be generated and supplied to the data driving circuit 410 .

The level shifter 220 may generate the second gate control signals (VST, GCLK1 to GCLK4, EVEN, ODD, etc.) based on the first gate control signals (GST, On_CLK, and OFF_CLK) generated by the timing controller 210 . have. The second gate control signals VST, GCLK1 to GCLK4, EVEN, ODD, etc. may have a larger voltage swing range than the first gate control signals GST, On_CLK, and OFF_CLK.

The gamma voltage generator divides the voltage between HVDD and VDDH to generate a plurality of gamma voltages (GMA1, GMA2, GMA3, etc.) in the high gray range, and divides the voltage between VSSH and HVDD to generate a plurality of gamma voltages in the low gray range. It can generate voltages (GMA4, GMA5, GMA6, etc.). Although three gamma voltages are described for each of the high grayscale range and the low grayscale range, this is for convenience of description and the number of gamma voltages can be changed according to the usage purpose of the display panel 100 or the size of the panel.

For example, when an 8-bit digital data signal is used for image display, the low gradation range may be 0 to 127 gradations and the high gradation range may be 128 to 256 gradations. For example, when a 10-bit digital data signal is used for image display, the low gradation range may be 0 to 511 gradations, and the high gradation range may be 512 to 1024 gradations. Accordingly, the low gradation range and the high gradation range can be freely modified according to the number of bits of the data signal used for image display.

The gate driving circuit 300 may be formed on one side of the lower substrate 110 . The gate driving circuit 300 may be formed together with each pixel P using a semiconductor process. That is, the gate driving circuit 300 may be embedded on the lower substrate 110 .

The gate driving circuit 300 may generate a gate signal based on the gate control signal generated by the timing controller 210 and passed through the COF 400 and sequentially supply it to the gate line GL of the display panel 100 . .

Specifically, as shown in FIG. 5 , the gate driving circuit 300 may include a plurality of shift registers SR1 to SRn. Each of the shift registers SR1 to SRn may be dependently connected to each other. For example, the output terminal of the previous shift register may be connected to the input terminal of the next shift register. Accordingly, the gate signal output to the output terminal of the previous shift register may be input to the input terminal of the next shift register. A gate signal may be output from an output terminal of the next shift register in response to a gate signal inputted to an input terminal of the next shift register.

Since the previous shift register of the first shift register SR1 does not exist, the start voltage VST output from the level shifter 220 is inputted from the level shifter 220 to the input terminal of the first shift register SR1 to initiate this start. The first gate signal Vg1 may be output from the first shift register SR1 to the corresponding gate line GL in response to the voltage VST.

The first gate signal Vg1 may be input to the input terminal of the second shift register SR2 , and the second gate signal Vg2 may be output from the second shift register SR2 . In this way, each of the shift registers SR1 to SRn is driven, and as shown in FIG. 6, the gate signals Vg1, Vg2, Vg3, ..., Vgn are gated from each of the shift registers SR1 to SRn during one frame. They may be sequentially output to the lines GL.

A start voltage VST or an output signal output from an output terminal of a previous shift register may be input to an input terminal of each of the shift registers SR1 to SRn. Also, the first to fourth gate clock signals GCLK1 to GCLK4 output from the level shifter 220 may be input to input terminals of the respective shift registers SR1 to SRn. In addition, one of the odd power voltage ODD and the even power voltage EVEN output from the level shifter 220 may be input to the input terminal of each of the shift registers SR1 to SRn. Here, the odd-numbered power supply voltage ODD may be referred to as a first power supply voltage and the even-numbered power supply voltage EVEN may be referred to as a second power supply voltage.

As shown in FIG. 7 , each of the shift registers SR1 to SRn may include a controller 320 , a pull-up transistor Tpu, a first pull-down transistor Tpd1 and a second pull-down transistor Tpd2 . Here, the pull-up transistor Tpu may be referred to as a first transistor, the first pull-down transistor Tpd1 may be referred to as a second transistor, and the second pull-down transistor Tpd2 may be referred to as a third transistor.

The pull-up transistor Tpu, the first pull-down transistor Tpd1, and the second pull-down transistor Tpd2 may be PMOS transistors or NMOS transistors.

The control unit 320 selectively increases the potentials of the first node Q and the second or third nodes QB1 and QB2 in response to the control signal X, the odd power supply voltage ODD, and the even power supply voltage EVEN. Each can be controlled. The controller 320 for controlling the potentials of the first node Q and the second or third nodes QB1 and QB2 may be implemented in any known configuration.

The pull-up transistor Tpu, the first pull-down transistor Tpd1, or the second pull-down transistor Tpd2 may be turned on/off according to potential states of the first to third nodes Q, QB1, and QB2. In addition, as the first pull-down transistor Tpd1 or the second pull-down transistor Tpd2 is turned on/off, the gate high voltage VGH or the gate low voltage VGL is output to the corresponding gate line GL as an output signal. can The gate high voltage VGH may be any one of the first to fourth gate clock signals GCLK1 to CGLK4.

The gate high voltage VGH may be a voltage for turning on the thin film transistor of each pixel P, and the gate low voltage VGL may be a voltage for turning off the thin film transistor of each pixel P.

The control signal X may be a start voltage VST or an output signal of a previous shift register. When the high level control signal X is input, the high level control signal X may be applied to the first node Q. In response to the high-level control signal X applied to the first node Q, the pull-up transistor Tpu is turned on so that the gate high voltage VGH may be output as a gate signal through the output node n. The odd-numbered power supply voltage ODD and the even-numbered power supply voltage EVEN may be supplied to the second node QB1 or the third node QB2 at regular intervals.

For example, as shown in FIG. 8 , during the first frame F1 , the high level of the odd power supply voltage ODD is supplied to the second node QB1 and the low level of the even power supply voltage EVEN reaches the third node ( QB2) can be supplied. In this case, in response to the high level odd power voltage ODD supplied to the second node QB1 , the first pull-down transistor Tpd1 is turned on so that the gate low voltage VGL is the gate signal of the first pull-down transistor Tpd1 . ) and the output node n may be output to the corresponding gate line GL. In contrast, the second pull-down transistor Tpd2 is turned off in response to the low-level even power voltage EVEN supplied to the third node QB2 . In this case, a low-level potential is maintained at the first node Q, and the pull-up transistor Tpu may be turned off by the low-level potential.

Subsequently, during the second frame F2 , the low level of the odd power supply voltage ODD may be supplied to the second node QB1 and the high level of the even power supply voltage EVEN may be supplied to the third node QB2 . In this case, the first pull-down transistor Tpd1 is turned off in response to the low-level odd power voltage ODD supplied to the second node QB1 . In contrast, in response to the high-level even power voltage EVEN supplied to the third node QB2 , the second pull-down transistor Tpd2 is turned on, and the gate low voltage VGL is an output signal of the second pull-down transistor ( Tpd2) and the output node n may be output to the corresponding gate line GL. In this case, a low-level potential is maintained at the first node Q, and the pull-up transistor Tpu may be turned off by the low-level potential.

In this way, by alternately turning on the second pull-down transistor Tpd2 or the third pull-down transistor for each frame, for example, in a predetermined period, an increase in stress due to the continuous application of a high-level power voltage to one pull-down transistor can be prevented. have.

FIG. 2 is a block diagram illustrating the level shifter of FIG. 1 , and FIG. 3 is a block diagram illustrating the level shifter of FIG. 1 in detail.

2, the timing control unit 210 generates the first gate control signals (GST, On_CLK, and OFF_CLK) based on the timing control signals (Vsync, Hsync, DE, DCLK, etc.) input from the outside to generate a level shifter ( 220) can be supplied.

The level shifter 220 may generate the second gate control signals (VST, GCLK1 to GCLK4, EVEN, ODD, etc.) based on the first gate control signals (GST, On_CLK, and OFF_CLK) generated by the timing controller 210 . have.

The second gate control signals VST, GCLK1 to GCLK4, EVEN, ODD, etc. may have a larger voltage swing range than the first gate control signals GST, On_CLK, and OFF_CLK. For example, the first gate control signals (GST, On_CLK, and OFF_CLK) have a voltage swing range of, for example, 0V to 5V, while the second gate control signals (VST, GCLK1 to GCLK4, EVEN, ODD, etc.) have a voltage swing range of -10V to 30V. It may have a voltage swing range, but is not limited thereto.

Among the first gate control signals, the start signal GST may have a level of 5V, and the driving clock signals On_CLK and Off_CLK may have a plurality of pulses swinging between 0V and 5V.

Among the second gate control signals, the start voltage VST has a level of, for example, 25V, the gate clock signals GCLK1 to GCLK4 have pulses swinging between -5V to 25V, and an odd power supply voltage ODD and an even power supply voltage (EVEN) may have a low level of -5V or a high level of 25V.

In the present invention, there is no need to input a separate signal to the level shifter 220 to generate the odd power supply voltage ODD and the even power supply voltage EVEN, and the start signal GST input to the level shifter 220 and An odd power supply voltage ODD and an even power supply voltage EVEN may be generated based on the driving clock signal Off_CLK. Accordingly, the present invention eliminates the need for a signal line for inputting a separate signal, thereby minimizing the interference between the signal lines by reducing the number of signal lines and reducing costs. In addition, according to the present invention, it is possible to secure an area occupied by a separate signal line, so that the usefulness of the PCB 200 can be strengthened.

The generation of the second gate control signal output from the level shifter will be described in detail with reference to FIGS. 3 and 4 .

Referring to FIG. 3 , the first gate control signal output from the timing controller 210 , for example, the start signal GST, and the first and second driving clock signals On_CLK and Off_CLK may be input to the level shifter 220 . have.

As shown in FIG. 4A , the start signal GST may have a first pulse P1_GST and a second pulse P2_GST having a high level. The first pulse P1_GST is used to generate a start voltage VST for driving each of the shift registers SR1 to SRn, and the second pulse P2_GST generates an odd power supply voltage ODD and an even power supply voltage EVEN. can be used to create

The first pulse P1_GST may be generated once every frame. The second pulse P2_GST may be generated in a vertical blank period Vblank defined in a partial period of the frame. The vertical blank section Vblank may be defined in a section from a boundary time point between a previous frame and a next frame to a partial time point before it.

As shown in FIG. 4B , the first driving clock signal On_CLK may have a pulse P_On overlapping the pulse P_On of the start signal GST and a plurality of pulses P1_CLK. The width of the pulse P_On may be equal to or at least smaller than the width of the pulse P_On of the start signal GST. The pulse P_On may be used to generate the start voltage VST together with the pulse P_On of the start signal GST.

As shown in FIG. 4C , the second driving clock signal Off_CLK may have a pulse P_Off overlapping the second pulse P_GST of the start signal GST and a plurality of pulses P2_CLK. A pulse P_Off of the second driving clock signal Off_CLK is also generated in the vertical blank section, and the width of the pulse P_Off of the second driving clock signal Off_CLK is equal to that of the second pulse P2_GST of the start signal GST. It may be equal to or at least less than the width. The pulse P_Off of the second driving clock signal Off_CLK may be used together with the second pulse P2_GST of the start signal GST to generate the odd power supply voltage ODD and the even power supply voltage EVEN.

The level shifter 220 may include first to fourth logic circuits 221 , 223 , 225 , 227 , a clock modulator 230 , and a selection circuit 240 .

The first logic circuit 221 receives the start signal GST and the first driving clock signal On_CLK to generate the start voltage VST based on the start signal GST and the first driving clock signal On_CLK. can The first logic circuit 221 may be an AND gate, but is not limited thereto.

As shown in FIG. 4D , the first logic circuit 221 performs an AND-gate operation on the start signal GST and the first driving clock signal On_CLK to generate the start signal GST and the first driving clock signal On_CLK. The start voltage VST having a high level during a period in which the first pulse P1_GST of the start signal GST and the pulse P_On of the first driving clock signal On_CLK simultaneously have a high level during a period having a high level at the same time. ) can be created.

The clock modulator 230 may generate first to fourth gate clock signals GCLK1 to GCLK4 based on the first driving clock signal On_CLK and the second driving clock signal Off_CLK.

The second logic circuit 223 receives the start signal GST and the second driving clock signal Off_CLK and outputs a low-level output signal EO based on the start signal GST and the second driving clock signal Off_CLK. can create The low level output signal EO may be an enable signal to be input to the third logic circuit 225 . The second logic circuit 223 may be a NAND gate, but is not limited thereto.

As shown in FIG. 4E , the second logic circuit 223 performs a NAND gate operation on the start signal GST and the second driving clock signal Off_CLK to generate the start signal GST and the second driving clock signal Off_CLK. The output signal EO having a low level during a section having a high level at the same time, that is, a section in which the second pulse P2_GST of the start signal GST and the pulse P_Off of the second driving clock signal Off_CLK simultaneously have a high level. ) can be created.

The selection circuit 240 may be connected to the second logic circuit 223 to receive the enable signal EO output from the second logic circuit 223 . The selection circuit 240 may change the levels of the first and second selection signals Sel-a and Sel-b output to the first and second output terminals according to the enable signal EO.

For example, as shown in FIGS. 4F and 4G , when the first enable signal EO1 is input to the selection circuit 240 during the current frame Fn, a low-level signal is transmitted to the first output terminal of the selection circuit 240 . A first selection signal Sel-a may be output, and a high level second selection signal Sel-b may be output to a second output terminal of the selection circuit 240 . When the second enable signal EO2 is input to the selection circuit 240 during the next frame Fn+1, the high-level first selection signal Sel-a is output to the first output terminal of the selection circuit 240 . and a low-level second selection signal Sel-b may be output to the second output terminal of the selection circuit 240 . As such, whenever the enable signals EO1, EO2, etc. are input, the first and second selection signals Sel-a and Sel-b are changed from a low level to a high level or from a high level to a low level. can In this case, the first and second selection signals Sel-a and Sel-b may have levels opposite to each other. That is, when the first selection signal Sel-a has a low level, the second selection signal Sel-b may have a high level.

The third logic circuit 225 may receive the output signal EO output from the second logic circuit 223 and the first selection signal Sel-a outputted to the first output terminal of the selection circuit 240 . . The third logic circuit 225 may generate an odd power supply voltage ODD based on the output signal EO and the first selection signal Sel-a.

As shown in FIG. 4H , the third logic circuit 225 may perform an AND gate operation on the output signal EO and the first selection signal Sel-a.

For example, when the first selection signal Sel-a is at the low level, the third logic circuit 225 may generate the odd power supply voltage ODD of the low level regardless of the level of the output signal EO.

For example, when the first selection signal Sel-a is at the high level, the third logic circuit 225 may generate the odd power supply voltage ODD of the high level in a section in which the output signal EO becomes the high level. have. As shown in FIG. 4E , as described above, the high level may be maintained during the remaining sections except for the first and second output signals EO1 and EO2 of the low level. Accordingly, when the first selection signal Sel-a is at a high level, during the high-level period between the first and second output signals EO1 EO2 , the third logic circuit 225 generates a high-level odd power supply voltage ODD. ) can be created.

The fourth logic circuit 227 may receive the output signal EO output from the second logic circuit 223 and the second selection signal Sel-b outputted to the second output terminal of the selection circuit 240 . . The fourth logic circuit 227 may generate an even-numbered power supply voltage EVEN as shown in FIG. 4I based on the output signal EO and the second selection signal Sel-b.

As shown in FIG. 4I , the fourth logic circuit 227 may perform an AND gate operation on the output signal EO and the second selection signal Sel-b.

For example, when the second selection signal Sel-b is at the low level, the fourth logic circuit 227 may generate the even power voltage EVEN of the low level regardless of the level of the output signal EO.

For example, when the second selection signal Sel-b is at the high level, the third logic circuit 225 may generate the odd power supply voltage ODD of the high level in a section in which the output signal EO becomes the high level. have. That is, when the second selection signal Sel-b is at the high level, during the high-level period between the first and second output signals EO1 EO2 shown in FIG. 4E , the fourth logic circuit 227 operates at the high level. An odd power supply voltage (ODD) may be generated.

In summary, the third logic circuit 225 generates the odd power supply voltage ODD of high level during the high-level section between the first and second output signals EO1 EO2 shown in FIG. 4E , and the fourth logic circuit 227 may also generate a high-level even power voltage EVEN during a high-level period between the first and second output signals EO1 and EO2 illustrated in FIG. 4E .

Each of the third and fourth logic circuits 225 and 227 may be an AND gate, but is not limited thereto.

The start voltage VST output from the first logic circuit 221 , the first to fourth gate clock signals GCLK1 to GCLK4 output from the clock modulator 230 , and odd numbers output from the third logic circuit 225 . The voltage swing range of the power supply voltage ODD and the even-numbered power voltage EVEN output from the fourth logic circuit 227 is greater than the voltage swing range of the first gate control signals GST, On_CLK, and OFF_CLK. (not shown) may be adjusted.

As described above, in the present invention, since the enable signal EO required to generate the odd power supply voltage ODD and the even power supply voltage EVEN does not need to be input to the level shifter 220, the enable signal ( There is no need for a signal line to supply EO). Accordingly, the cost is reduced by reducing the number of input signal lines connected to the level shifter 220, and as the number of input signal lines is reduced, the interval between the signal lines becomes wider, thereby minimizing the occurrence of electrical interference between the signal lines. Distortion of the first gate control signals GST, On_CLK, and Off_CLK input to the level shifter 220 may be prevented.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

100: display panel
200: printed circuit board
210: timing control
220: level shifter
221, 223, 225, 227: logic circuit
230: clock modulator
240: selection circuit
300: gate driving circuit
400: chip on film
410: data driving circuit

Claims (6)

a display panel including a plurality of pixels defined by intersections of a plurality of gate lines and a plurality of data lines;
a level shifter configured to generate a start voltage, first to fourth gate clock signals, a first power voltage, and a second power voltage based on the start signal, the first driving clock signal, and the second driving clock signal;
a plurality of shift registers for supplying any one of the first to fourth clock signals to a corresponding gate line in response to the start voltage;
The initiation signal has first and second pulses,
The second driving clock signal has a pulse overlapping the second pulse,
The second pulse of the start signal and the pulse of the second driving clock signal are generated in a vertical blank section included in a frame,
The first and second power voltages are generated using the start signal and the second driving clock signal. delete According to claim 1,
The level shifter is
a first logic circuit for generating a low-level output signal based on a second pulse of the start signal and a pulse of the driving clock signal;
a selection circuit for outputting first and second selection signals whose phases are inverted from each other by using the output signal output from the first logic circuit as an enable signal;
a second logic circuit configured to generate the first power voltage based on an output signal output from the first logic circuit and a selection signal of any one of the first and second selection signals output from the selection circuit; and
and a third logic circuit configured to generate the second power voltage based on an output signal output from the first logic circuit and the other one of the first and second selection signals output from the selection circuit; . 4. The method of claim 3,
and the first logic circuit is a NAND gate. 4. The method of claim 3,
and each of the second and third logic circuits is an AND gate. 4. The method of claim 3,
The output signal output from the first logic circuit is generated for each vertical blank period of every frame,
The first and second power supply voltages are phase-inverted according to the output signal generated for each vertical blank period of each frame.

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