KR102294765B1 - Level shifter and display device - Google Patents

Abstract

The level shifter generates a plurality of gate clock signals based on a single clock signal input from the outside, so that only one pin through which the level shifter can input a single clock signal is required, so the number of pins of the level shifter can be reduced.

Description

Level shifter and display device {LEVEL SHIFTER AND DISPLAY DEVICE}

The present invention relates to a level shifter and a display device.

A display device is a device that displays an image or information. Among display devices, a liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field.

The liquid crystal display includes a liquid crystal display panel in which pixels defined by a plurality of gate lines and a plurality of data lines are arranged in a matrix, and driving circuits for driving the liquid crystal display panel.

As one of the driving circuits, there is a level shifter for generating at least two-phase or more gate clock signals used for generating a gate signal for supplying to the liquid crystal display panel.

The level shifter is integrated into a circuit and has input/output pins for input/output of a plurality of signals.

However, since the input/output pins given to the level shifter are limited while the number of input/output pins to be used is increasing, it is necessary to optimize the use of the input/output pins.

In particular, two clock signals are provided from the timing controller to generate at least two-phase or more gate clock signals from the level shifter. In this case, two output pins should be allocated to the timing controller for output of two clock signals, and two input pins should be allocated to the level shifter for input of two clock signals. In addition, two signal lines are required to transmit two clock signals between the timing controller and the level shifter. Accordingly, as two pins are required for each of the timing controller and the level shifter, the use of other signals is restricted, and there is a problem in that an area occupied by the two signal lines is increased.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems.

Another object of the present invention is to provide a level shifter and a display device capable of efficiently managing the number of pins and lines.

According to one aspect of the present invention to achieve the above or other objects, the level shifter generates a plurality of gate clock signals based on a single clock signal input from the outside, so that the level shifter can input a single clock signal. Since only pins of , the number of pins of the level shifter can be reduced.

According to another aspect of the present invention, a display device includes a timing controller for generating a clock signal, and a level shifter for generating a plurality of gate clock signals based on first and second clock signals generated from the clock signal, Since only one pin capable of inputting and outputting a single clock signal is required for each of the timing controller and the level shifter, the number of pins of the timing controller and the level shifter can be reduced. In addition, the number of signal lines connected between the timing controller and the level shifter may be reduced.

The effects of the terminal according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, since only one pin capable of inputting and outputting a single clock signal is required for each of the timing controller and the level shifter, the number of pins of each of the timing controller and the level shifter can be reduced, and the timing controller and the level shifter There is an advantage in that the number of signal lines connected therebetween can be reduced.

According to at least one of the embodiments of the present invention, the first clock signal among the first and second clock signals generated from the single clock signal is used for driving the timing controller, the gate driving circuit, and the data driving circuit using a driving voltage used to drive the data driving circuit. By generating and generating the second clock signal using the ground voltage, there is no need to generate a separate additional voltage to generate the first clock signal, so an additional circuit is not required to generate the additional voltage, thereby reducing costs It has the advantage of maximizing space utilization by securing space for other electronic circuits.

According to at least one of the embodiments of the present invention, a single clock signal used to generate a plurality of gate clock signals ( CLK) has the advantage of being able to expand its availability.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments such as preferred embodiments of the present invention are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention may be clearly understood by those skilled in the art.

1 is a view showing a display device according to the present invention.
FIG. 2 shows input/output signals of the level shifter of FIG. 1 .
FIG. 3 is a block diagram illustrating the level shifter of FIG. 1 .
FIG. 4 is a block diagram illustrating the clock control unit of FIG. 3 .
5 is an input/output waveform diagram of the level shifter.
6 is an input/output waveform diagram of a level shifter for overlap between adjacent gate clock signals.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and overlapping descriptions thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

First, data transmission of the present invention is based on the EPI protocol transmission method (see FIG. 1).

EPI (Embedded clock Point-to-point Interface) protocol satisfies the interface regulations of (1) to (3) below.

(1) The transmitting end of the timing controller 210 and the receiving end of the data driving circuits 410 are connected in a point-to-point manner via a pair of data lines.

(2) A separate pair of clock wires is not connected between the timing controller 210 and the data driving circuits 410 . The timing controller 210 transmits a timing control signal and a video data signal along with a clock signal to the data driving circuits 410 through a pair of data lines.

(3) DLL (Delay Locked Loop, hereinafter referred to as DLL) for CDR (Clok and Data Recovery) is built in each of the data driving circuits 410 . The timing controller 210 transmits a preamble signal (also called a clock training signal) to the data driving circuits so that the output phase and frequency of the DLL can be locked. The DLL embedded in the data driving circuits 410 generates an internal clock when the preamble signal and the clock signal are input through the data wire pair after the phase of the output thereof is fixed.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1 , a liquid crystal display according to the present invention includes a display panel 100 , a printed circuit board (hereinafter referred to as a PCB, 200), a gate driving circuit 300 and a plurality of chip-on films (COF). Film, hereinafter referred to as COF, 400) may be included.

The display panel 100 may be a liquid crystal display panel that displays an image by displacement of liquid crystal molecules included in the liquid crystal layer, but is not limited thereto.

In addition to the COF 400 , a Chip On Board (COB) or a Tape Carrier Package (TCP) may be used, but is not limited thereto.

Hereinafter, for convenience of explanation, the present invention is limited to the COF 400, but the present invention can be equally applied to TCP or COB.

Each of the COFs 400 may include a data driving circuit 410 . In other words, the data driving circuit 410 may be mounted on the COF 400 . Specifically, pins of the data driving circuit 410 may be electrically connected to the COF 400 by bonding.

The display panel 100 may display an image and may be electrically connected to the PCB 200 through a plurality of COFs 400 .

The display panel 100 may include a lower substrate 110 , an upper substrate 120 , and a liquid crystal layer (not shown) formed between the substrates 110 and 120 .

A plurality of pixels P may be defined by crossing the plurality of gate lines GL and the plurality of data lines DL on the lower substrate 110 . Each pixel P may include a thin film transistor (not shown) connected to the gate line GL and the data line DL, and a pixel electrode connected to the thin film transistor. The pixel electrodes formed on each pixel P may be spaced apart from each other.

A color filter formed to correspond to each pixel P and a black matrix for separating the color filters are formed on the upper substrate 120 .

Meanwhile, a common electrode for supplying a common voltage may be formed on any one of the lower substrate 110 and the upper substrate 120 . For example, the common electrode is formed on the upper substrate 120 when the display panel 100 is driven in a vertical electric field method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and an IPS (In Plane Switching) mode. When driven by a horizontal electric field method such as a fringe field switching (FFS) mode, it may be formed on the lower substrate 110 together with the pixel electrode.

The display panel 100 may display an image by adjusting the light transmittance of the liquid crystal layer according to the data voltage applied to each pixel P.

A timing controller 210 , a level shifter 220 , a gamma voltage generator (not shown) and a power voltage generator (not shown) may be provided on the PCB 200 .

The power voltage generator may generate various power voltages for use in various devices, for example, the timing controller 210 , the level shifter 220 , the gate driving circuit 300 , the data driving circuit 410 , and the gamma voltage generator. have. For example, the power supply voltage includes a gate high voltage VGH, a gate low voltage VGL, a driving voltage VCC, and a ground voltage GND. The driving voltage VCC and the ground voltage GND may be used as voltages for driving the timing controller 210 , the gate driving circuit 300 , the data driving circuit 410 , and the like. The driving voltage VCC may be a voltage used to drive the timing controller 210 , the gate driving circuit 300 , and the data driving circuit 410 , but is not limited thereto.

Each of the gate high voltage VGH and the gate low voltage VGL may be used as a high level and a low level of the gate clock signals GCLK1 to GCLK4 generated by the level shifter 220 . For example, the driving voltage VCC may be 3.3V or more, the ground voltage GND may be 0V, the gate high voltage VGH may be 20V or more, and the gate low voltage VGL may be -0V or less. I never do that.

The timing controller 210 generates the first gate control signals GST and CLK based on the timing control signals Vsync, Hsync, DE, DCLK, etc. inputted from the outside while generating the data control signals SSP, SSC, SOE, POL, etc.) may be generated and supplied to the data driving circuit 410 .

As described above, related data may be transmitted between the timing controller 210 and the data driving circuit 410 based on the EPI transmission protocol method. That is, the EPI data signal may be transmitted from the timing controller 210 to the data driving circuit 410 based on the EPI transmission protocol transmission method. The EPI data signal is transmitted in the format of the first to third steps. The preamble signal is loaded in the format of the first step, and the format of the second step is the data control signal (SSP, SSC, SOE, POL, etc.) as a control packet. ), and in the format of the third step, a video data signal may be loaded as a data packet.

The gamma voltage generator may generate a plurality of gamma voltages by dividing a voltage between the upper power supply voltage and the lower power supply voltage.

As shown in FIG. 2 , the level shifter 220 generates second gate control signals (VST, GCLK1 to GCLK4, etc.) based on the first gate control signals GST and CLK generated by the timing controller 210 . can do. Although not shown, the power voltages VGH and VGL generated by the power voltage unit of the timing controller 210 may also be input to the level shifter 220 .

The level shifter 220 includes the main inventive idea of the present invention, which will be described in detail later.

The gate driving circuit 300 may be formed on one side of the lower substrate 110 . The gate driving circuit 300 may be formed together with each pixel P using a semiconductor process. That is, the gate driving circuit 300 may be embedded on the lower substrate 110 .

The gate driving circuit 300 generates a gate signal based on the second gate control signals (VST, GCLK1 to GCLK4, etc.) generated from the level shifter 220 and passed through the COF 400 to generate a gate signal of the display panel 100 . It may be sequentially supplied to the line GL.

Specifically, the gate driving circuit 300 may include a plurality of shift registers SR1 to SRn (not shown). Each of the shift registers SR1 to SRn may be dependently connected to each other. For example, the output terminal of the previous shift register may be connected to the input terminal of the next shift register. Accordingly, the gate signal output to the output terminal of the previous shift register may be input to the input terminal of the next shift register. A gate signal may be output from an output terminal of the next shift register in response to a gate signal inputted to an input terminal of the next shift register.

FIG. 3 is a block diagram illustrating the level shifter of FIG. 1 , and FIG. 4 is a block diagram illustrating the clock controller of FIG. 3 .

Referring to FIG. 3 , the timing controller 210 generates the first gate control signals GST and CLK based on the timing control signals Vsync, Hsync, DE, DCLK, etc. inputted from the outside to generate the level shifter 220 . can be supplied with

The level shifter 220 may generate second gate control signals VST, GCLK1 to GCLK4, etc. based on the first gate control signals GST and CLK generated by the timing controller 210 .

The start signal GST may be 5V, whereas VST may be 25V. Accordingly, the level shifter 220 may level-adjust the start signal GST of 5V to 25V and output it as the start signal VST.

As shown in FIG. 5 , the clock signal CLK may have a plurality of pulses swinging between the ground voltage GND and the driving voltage VCC. In contrast, the first to fourth gate clock signals may have a plurality of pulses swinging between the gate low voltage VGL and the gate high voltage VGH.

The level shifter 220 may include an AND gate 221 , a NOR gate 223 , and a clock controller 225 .

In the present invention, the driving voltage VCC and the ground voltage GND may be input to the level shifter 220 . Specifically, the driving voltage VCC may be input to the AND gate 221 , and the ground voltage GND may be input to the NOR gate 223 . In this case, the AND gate 221 may be set to recognize the driving voltage VCC as a high level, and the NOR gate 223 may be set to recognize the ground voltage GND as a low level.

In addition, the AND gate 221 may be configured to recognize a voltage above the threshold voltage as a high level and a voltage below the threshold voltage as a low level. In this case, the threshold voltage may be changed in consideration of the value of the driving voltage VCC. For example, when the driving voltage VCC is 3.3V, the threshold voltage may be 2.6V.

The NOR gate 223 may be configured to recognize a voltage below the threshold voltage as a low level and a voltage above the threshold voltage as a high level. In this case, the threshold voltage may be changed in consideration of the value of the ground voltage GND. For example, when the ground voltage GND is 0V, the threshold voltage may be 0.7V.

The AND gate 221 may receive the driving voltage VCC and the clock signal CLK, operate the AND gate 221 on the driving voltage VCC and the clock signal CLK, and output the first clock signal CLK1. have.

5 , the clock signal CLK may have a plurality of pulses swinging between the ground voltage GND and the driving voltage VCC. In addition, the clock signal CLK may have an intermediate voltage V_mid positioned between the ground voltage GND and the driving voltage VCC. The intermediate voltage V_mid may vary according to the value of the driving voltage VCC. For example, the intermediate voltage V_mid may be 1.2V when the driving voltage VCC is 3.3V.

When the intermediate voltage V_mid is 1.2V and the clock signal CLK is input to the AND gate 221 , the threshold voltage of the AND gate 221 is 2.6V or less, so the intermediate voltage V_mid is applied to the AND gate 221 . can be recognized as a low level by

When the intermediate voltage V_mid is 1.2V and the clock signal CLK is input to the NOR gate 223 , the intermediate voltage V_mid is applied to the NOR gate 223 because the threshold voltage of the NOR gate 223 is 0.7V or more. can be recognized as a high level by

The AND gate 221 may output a high-level pulse when a pulse having the same level as the driving voltage VCC is input from the clock signal CLK. The driving voltage VCC input to the AND gate 221 may serve as a mask for outputting a pulse having the same level as the driving voltage VCC among the clock signals CLK.

Accordingly, the AND gate 221 operates the AND gate 221 on the driving voltage VCC and the clock signal CLK to have the first clock signal having pulses having the level of the driving voltage VCC of the clock signal CLK. (CLK1) can be created. The generated first clock signal CLK1 may be provided to the clock controller 225 .

The NOR gate 223 may receive the clock signal CLK and the ground voltage GND, operate the NOR gate 223 on the clock signal CLK and the ground voltage GND, and output the second clock signal CLK2. have.

The NOR gate 223 may output a low-level pulse when a pulse having the same level as the ground voltage GND is input from the clock signal CLK. The ground voltage GND input to the NOR gate 223 may serve as a mask for outputting a pulse having the same level as the ground voltage GND among the clock signals CLK.

Accordingly, the AND gate 221 may be referred to as a first mask, and the NOR gate 223 may be referred to as a second mask.

The NOR gate 223 operates the NOR gate 223 on the clock signal CLK and the ground voltage GND, and the second clock signal ( CLK2) can be created. The generated second clock signal CLK2 may be provided to the clock controller 225 .

In the present invention, the first clock signal CLK1 is generated using the driving voltage VCC used to drive the timing controller 210 , the gate driving circuit 300 and the data driving circuit 410 , and the second clock signal ( By generating CLK2 using the ground voltage GND, there is no need to generate a separate additional voltage to generate the first clock signal CLK1 , so an additional circuit is not required to generate the additional voltage, thereby reducing the cost. This saves space and frees up space for other electronic circuits, maximizing space utilization.

The clock controller 225 may generate the first to fourth gate clock signals GCLK1 to GCLK4 based on the first and second clock signals CLK1 and CLK2, the RDLY signal RDLY, and the RE signal RE. have.

A first resistor R1 may exist on a first input line for inputting the RDLY signal RDLY connected to the clock controller 225 . A second resistor R2 may exist on a second input line for inputting the RE signal RE connected to the clock controller 225 . The first and second resistors R1 and R2 may be intrinsic resistors present on the first and second input lines or resistors that are separately connected to the first and second input lines, but are not limited thereto. does not

Although the present invention is limited to four clock signals GCLK1 to GCLK4 for convenience, the first and second gate clock signals GCLK1 and GCLK2 are two-phase, and the first to sixth gate clock signals GCLK1 to GCLK6 are six-phase. ) or more gate clock signals may be generated.

More specifically, as shown in FIG. 4 , the clock controller 225 may include a clock generator 231 , a level adjuster 233 , and an edge modulator 235 .

The clock generator 231 receives the first and second clock signals CLK1 and CLK2 and receives first to fourth gate clock signals GCLK1 to GCLK4 based on the first and second clock signals CLK1 and CLK2 can create The first to fourth gate clock signals GCLK1 to GCLK4 may be sequentially generated. The first to fourth gate clock signals GCLK1 to GCLK4 may or may not overlap each other.

In this case, although not shown, each of the first to fourth gate clock signals GCLK1 to GCLK4 may have a plurality of pulses swinging between the ground voltage GND and the driving voltage VCC.

Meanwhile, since the AND gate 221 and the NOR gate 223 shown in FIG. 3 generate first and second clock signals CLK1 and CLK2 using the clock signal CLK, respectively, the AND gate 221 and The first clock generator including the NOR gate 223 may be generated as a component. In this case, as shown in FIG. 4 , the clock generator 231 that generates the first to fourth gate clock signals GCLK1 to GCLK4 based on the first and second clock signals CLK1 and CLK2 includes the second It may be called a clock generator.

The first to fourth gate clock signals GCLK1 to GCLK4 may be provided to the level adjuster 233 .

The level adjuster 233 converts the first to fourth gate clock signals GCLK1 to GCLK4 from a plurality of pulses swinging between the ground voltage GND and the driving voltage VCC to the gate high voltage VGH and the gate low voltage VGH. VGL) can be tuned with multiple pulses swinging between them. That is, the ground voltage GND may be adjusted to the gate low voltage VGL, and the driving voltage VCC may be adjusted to the gate high voltage VGH. The level-adjusted first to fourth gate clock signals GCLK1 to GCLK4 are illustrated in FIG. 5 . However, in the level-adjusted first to fourth gate clock signals GCLK1 to GCLK4, edge modulation is not generated at a rising time and a falling time as shown in FIG. 5 .

The first to fourth gate clock signals GCLK1 to GCLK4 output from the level adjuster 233 may be provided to the edge modulator 235 .

The edge modulator 235 may modulate an edge region of each of the first to fourth gate clock signals GCLK1 to GCLK4 based on the RDLY signal RDLY and the RE signal RE. For example, the RDLY signal RDLY may be a signal determining a start time of modulation, and the RE signal RE may be a signal determining a modulation slope. A modulation width of each of the first to fourth gate clock signals GCLK1 to GCLK4 may be determined by the RE signal RE.

Each of the first to fourth gate clock signals GCLK1 to GCLK4 whose level is adjusted by the level adjuster 233 may have a constant high level between a rising time and a falling time. In other words, each of the level-adjusted first to fourth gate clock signals GCLK1 to GCLK4 may transition from a low level to a high level at a rising time, and may transition from a high level to a low level at a falling time. .

As shown in FIG. 5 , the edge modulator 235 performs the level-adjusted first to fourth gate clock signals GCLK1 to GCLK4 at each rising time based on the RDLY signal RDLY and the RE signal RE. Edge modulation can be performed. In addition, as shown in FIG. 5 , the edge modulator 235 is configured to poll each of the first to fourth gate clock signals GCLK1 to GCLK4 whose level is adjusted based on the RDLY signal RDLY and the RE signal RE. Edge modulation can be performed in time.

The edge modulator 235 performs edge modulation at both a rising time and a falling time of each of the level-adjusted first to fourth gate clock signals GCLK1 to GCLK4, or performs edge modulation at any one of the rising time and the falling time. can be done

The level-adjusted and clock-modulated first to fourth clock signals as shown in FIG. 5 may be output through the edge modulator 235 . The first to fourth clock signals may be provided to the gate driving circuit 300 , and the gate signals may be sequentially provided to the display panel 100 by the gate driving circuit 300 .

A corresponding gate line is activated by a gate signal provided to the display panel, and a data voltage provided to a plurality of data lines crossing the corresponding gate line is a pixel on one line defined by the corresponding gate line and the plurality of data lines. The images can be displayed by being supplied to them.

The level shifter 220 of the present invention may generate the first to fourth gate clock signals GCLK1 to GCLK4 using only one signal, that is, the clock signal CLK. Accordingly, since only one pin capable of inputting and outputting one clock signal CLK is required for each of the timing controller 210 and the level shifter 220 , the number of pins of the timing controller 210 and the level shifter 220 is adjusted can be reduced In addition, the number of signal lines connected between the timing controller 210 and the level shifter 220 may be reduced.

Meanwhile, the above description is a case in which the first to fourth gate clock signals GCLK1 to GCLK4 are generated without overlapping with each other.

Alternatively, as shown in FIG. 6 , the first to fourth gate clock signals GCLK1 to GCLK4 may be generated to overlap each other.

6 illustrates an overlap between the first gate clock signal GCLK1 and the second gate clock signal GCLK2. Although not shown, the second to fourth gate clock signals GCLK2 to GCLK4 may or may not be generated to overlap each other, and the present invention is not limited thereto.

The clock signal CLK shown in FIG. 6 is different from the clock signal CLK shown in FIG. 5 , and an intermediate voltage (middle level, V_mid) between the ground voltage (low level, GND) and the driving voltage (high level, VCC). .

The level shifter 220 may generate the first and second clock signals CLK1 and CLK2 based on the clock signal CLK. That is, the AND gate 221 of the level shifter 220 generates the first clock signal CLK1 by performing an AND gate 221 operation on the driving voltage VCC and the clock signal CLK, and The NOR gate 223 may generate the second clock signal CLK2 by performing a NOR gate 223 operation on the clock signal CLK and the ground voltage GND.

Each of the first and second clock signals CLK1 and CLK2 may have a plurality of pulses. For example, the pulses of the first clock signal CLK1 may be temporally positioned between pulses of the second clock signal CLK2 .

However, at a specific point in time when the driving voltage (high level, VCC) of the clock signal CLK transitions from the driving voltage (high level, VCC) to the ground voltage (low level, GND), the pulse of the first clock signal CLK1 becomes the falling time while the second clock signal The pulse of the signal CLK2 may be a rising time.

The pulse of the first clock signal CLK1 generated before the singular time with respect to the singular point may be referred to as a first pulse, and the pulse of the second clock signal CLK2 generated after the singular point may be referred to as a second pulse. have.

In this case, the first and second gate clock signals GCLK1 and GCLK2 passing through the clock generator 231 , the level adjuster 233 , and the edge modulator 235 of the shift register 220 are shown in FIG. 6 . there is a bar

The first gate clock signal GCLK1 and the second gate clock signal GCLK2 may be generated to partially overlap each other.

For example, edge modulation may be performed at the rising time of the second gate clock signal GCLK2 in synchronization with the rising time of the first pulse of the first clock signal CLK1 .

For example, edge modulation at the falling time of the first gate clock signal GCLK1 is synchronized with the falling time of the first pulse of the first clock signal CLK1 and the rising time of the second pulse of the second clock signal CLK2 can be performed.

In other words, since the rising time of the second gate clock signal GCLK2 is located temporally earlier than the falling time of the first gate clock signal GCLK1, a partial period of the first gate clock signal GCLK1 and the second gate clock signal Some sections of (GCLK2) may be generated to overlap each other.

According to the present invention, at least first and second gate clock signals GCLK1 and GCLK2 that may be superimposed on each other may be generated using one signal, that is, the clock signal CLK. The availability of a single clock signal CLK used to generate a plurality of gate clock signals GCLK1 to GCLK4 may be expanded.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

100: display panel
200: printed circuit board
210: timing control
220: level shifter
221: and gate
223: nor gate
225: clock control unit
231: clock generator
233: level adjustment unit
235: edge modulator
300: gate driving circuit
400: chip on film
410: data driving circuit

Claims (11)

one pin for inputting one clock signal;
a first clock generator for generating first and second clock signals based on the one clock signal input through the single pin;
a second clock generator generating a plurality of gate clock signals based on the first and second clock signals; and
and a level adjuster for adjusting the levels of the gate clock signals. According to claim 1,
The first clock generator,
a first mask for generating a first clock signal based on the clock signal and the driving voltage; and
and a second mask for generating a second clock signal based on the clock signal and a ground voltage. 3. The method of claim 2,
The first mask is an AND gate, and the second mask is a NOR gate. 4. The method of claim 3,
The AND gate is
A level shifter generating a plurality of pulses having the same level as the driving voltage among the clock signals as the first clock signal. 4. The method of claim 3,
The NOR gate is
A level shifter generating the second clock signal by inverting a plurality of pulses having the same level as the ground voltage among the clock signals. 3. The method of claim 2,
The driving voltage is a voltage used to drive a timing controller, a gate driving circuit, and a data driving circuit of a display device. According to claim 1,
The gate clock signals are generated to be spaced apart from each other. According to claim 1,
A level shifter in which at least first and second gate clock signals among the gate clock signals are generated by overlapping each other. 9. The method of claim 8,
the clock signal has a plurality of low level pulses, a plurality of high level pulses and an intermediate level positioned between the low level pulses and the low level pulses;
The level shifter having a singular timing in which the clock signal transitions from a high level to a low level to generate the first and second gate clock signals overlapping each other. a timing controller for generating a clock signal; and
a plurality of gate clock signals based on first and second clock signals generated from one of the clock signals input from the timing controller through the one pin; A display device including a level shifter to generate. 11. The method of claim 10,
The level shifter is
a first clock generator generating the first and second clock signals based on the clock signal;
a second clock generator generating the gate clock signals based on the first and second clock signals;
a level adjusting unit for adjusting the levels of the gate clock signals; and
and an edge modulator for modulating an edge region of each of the level-adjusted gate clock signals.

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