KR100709702B1 - Liquid crystal display for compensation of data charging time - Google Patents

Abstract

The present invention relates to a liquid crystal display device that compensates for a data charging time, and includes an LCD panel, a timing controller, a gate driver, and a data driver. In this case, the timing controller generates an output enable signal considering the delay of the data voltage so that the gate-on voltage output from the gate driver is delayed and output from the final gate line rather than the initial gate line.

As a result, the present invention has an effect of preventing the charging time of the data voltage from the pixel shortened due to the delay of the data voltage.

LCD, Output Enable, Delay

Description

Liquid crystal display compensating for data charging time {LIQUID CRYSTAL DISPLAY FOR COMPENSATION OF DATA CHARGING TIME}

1 is a diagram illustrating waveforms of a gate voltage and a data voltage generally applied to a corresponding pixel.

2 is a block diagram of a liquid crystal display device for compensating for data charging time according to an exemplary embodiment of the present invention.

3 is a waveform diagram of a signal output from a timing controller of a liquid crystal display for compensating for data charging time according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a thin film transistor (TFT) liquid crystal display (LCD), and more particularly, to compensate for shortening of a charging time of a data voltage by a signal delay of a data line. Output Enabel) The present invention relates to a liquid crystal display device for adjusting the generation time of a signal.

An LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by controlling the intensity of the electric field. Such LCDs are typical of portable flat panel display devices, and among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

The TFT LCD includes a plurality of gate lines for transmitting a scan signal and data lines for crossing the gate lines and for transmitting image data, and are formed in an area surrounded by these gate lines and data lines, respectively. It includes a plurality of pixels in the form of a matrix connected through.

The method of applying image data to each pixel in such an LCD is as follows.

First, when a gate-on signal, which is a scanning signal, is sequentially applied to the gate lines, the switching elements connected to the gate lines are sequentially turned on, and at the same time, an image signal to be applied to the pixel row corresponding to the gate line, more specifically, a gray level. Supply voltage to each data line. Then, the image signal supplied to the data line is applied to each pixel through the turned-on switching element. In this case, the gate-on signal is sequentially applied to all the gate lines during one frame period to apply the pixel signal to all the pixel rows, thereby displaying an image of one frame.

By the way, there is a line resistance component in the data line and the gate line, and a delay of the gate driving signal and the data signal is generated by this resistance component, and as a result, as shown in FIG. The charge will vary.

1 is a diagram illustrating waveforms of a gate voltage and a data voltage generally applied to a corresponding pixel. In FIG. 1, a is a gate clock (hereinafter, referred to as 'CPV'), and b is an n-1 th output enable that prevents current data from colliding with data applied to a previous data line. : An OE signal, c is a data voltage Dn-1 charged in a pixel connected to an n-1th gate line, and d is a gate-on voltage Gn-1 applied to an n-1th gate line. And e is the n-th generated OE signal, f is the data voltage Dn charged in the pixel connected to the n-th gate line, and g is the gate-on voltage Gn applied to the n-th gate line.

As shown in Fig. 1, the gate-on signal is applied to the corresponding gate line at the falling edge of the OE signal occurring in synchronization with the rising edge of the CPV and applied to the corresponding gate line at the rising edge of the next OE. It doesn't work. That is, during the period where the OE signal is high, the gate on signal is not applied to the gate line. Therefore, the gray level voltage is not applied to the pixel during the period in which the OE signal is high, and the gate driving voltage and the data voltage are generated in the period in which the OE signal is low.

However, looking at the n-1 th data voltage and the n th data voltage through f and g, the n th data voltage is delayed by A time from the time point of the n-1 th data voltage due to the delay of the data line and applied to the corresponding pixel. Therefore, the charging time Tn is shorter than the n-1th charging time Tn-1.

As described above, when the charging time of the data voltage is changed by the gate selection, there is a problem in that the characteristics of the panel, that is, the contrast ratio, are changed.

 Accordingly, an object of the present invention is to compensate for data charging time due to data signal delay. In addition, an object of the present invention is to compensate for the data charging time by using the OE signal and not changing the width of the OE signal.

According to an aspect of the present invention for achieving the above object, a liquid crystal display device for compensating for a data charging time is provided.

A liquid crystal panel in which a plurality of data lines, a plurality of gate lines insulated and vertically intersected with the plurality of data lines, and pixels including pixel electrodes, common electrodes, and thin film transistors are arranged in a matrix form;

A timing controller configured to receive horizontal and vertical synchronization signals, data signals, and a main clock signal from an external source, and output a gate clock pulse and an OE signal generated according to a first rule corresponding to the gate clock pulses from the vertical and horizontal synchronization signals;

A source driver which drives according to a timing signal output from the timing controller and applies a data signal to the data line;

A gate driver configured to sequentially drive the gate driving signal to the gate line by driving the timing signal output from the timing controller;

The first rule is to generate an OE signal having a large delay width gradually from the rising edge of the gate clock pulse in consideration of the delay of the data line.

Accordingly, the timing controller of the present invention causes the OE for the last generated gate driving signal to be delayed as compared to the OE signal for the gate driving signal first generated in one frame. That is, the gate driver of the present invention causes the later gate driving signal to be gradually delayed and applied to the gate line compared to the gate driving signal first generated in one frame.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention by the above configuration as follows.

2 is a block diagram of a liquid crystal display device for compensating for data charging time according to an exemplary embodiment of the present invention. As shown in FIG. 2, the LCD for compensating for the data charging time according to an exemplary embodiment of the present invention includes a timing controller 10, a gray voltage generator 20, a gate driving voltage generator 30, and a gate. The driver 40, the data (source) driver 50, and the liquid crystal panel 60 are comprised.

The timing controller 10 receives R, G, and B data and a vertical sync signal Vsync, a frame discrimination signal, a horizontal sync signal Hsync, and a line discrimination signal from a graphic controller (not shown) outside the LCD module. In order to indicate a zone, the digital signal for driving the data driver 50 and the gate driver 40 is output while receiving the signal DE and the main clock signal MCLK having a high level only during the data output period.

More specifically, the timing controller 10 commands the digital driver to start inputting the digital data signals R (0: N), G (0: N), and B (0: N) from the graphics controller. Signal (Hstart), a signal (LOAD) for instructing data to be converted into analog in the source driver 50 and applying the converted analog value to the LCD panel, and for data shift in the source driver 50. The clock signal HCLK is output to the data driver 50.

Also, in order to sequentially apply the gate-on signal to the gate line, the timing controller 10 may include a Vstart indicating the start of the application of the gate-on signal, a CPV for sequentially performing the gate-on signal to each gate line, and a gate driver. An output of the 40 is enabled, and an OE signal that cuts a portion overlapping with the gate-on voltage of the next line caused by the delayed gate-on voltage applied to the panel is output to the gate driver 40.

At this time, the OE signal output from the timing controller 10 is delayed and output compared to the first signal based on one frame. The delay of this OE signal is designed to be proportional to the delay of the data line obtained by experiment or simulation.

The gate driving voltage generator 30 may include a voltage Von for making a gate-on signal, a voltage Voff for making a gate-off signal, and a common voltage Vcom serving as a reference for the data voltage difference in the TFT. Output to 40). In this case, the gate driver 40 may include a shift register, a level shifter, a buffer, and the like, and receive a gate clock signal and a vertical line start signal from the timing controller 10, and may supply voltages Von, Voff, and the like from the gate driving voltage generator. And Vcom) to open the way for the voltage value of each pixel on the LCD panel to be transferred to the pixel.

The gray voltage generator 20 generates a gray voltage suitable for a digital code value according to the number of bits of RGB data provided from the graphic controller and provides the gray voltage to the data driver 50. For example, if R data is applied with 6 bits (R (0: 5)), 26 = 64 gradations can be generated and R of 64 gradations can be represented.

The data driver 50 receives the R, G, and B digital data R (0: N), G (0: N), and B (0: N) from the timing controller 10 to receive the clock signal HCLK. When the load signal LOAD is applied to the LCD panel 60 after being shifted and stored, the data voltage for transferring the voltage to the LCD panel 60 by selecting a gray voltage corresponding to each data is applied. Outputs

The LCD panel 60 includes a plurality of gate lines that transmit gate voltages G1, G2,..., Gm, which are scan signals provided from the gate driver 40, and data voltages that are image signals crossing the gate lines. A plurality of source lines for transmitting D1, D2, ..., Dn), a TFT formed in an area surrounded by the gate line and the source line and connected to each gate line and the source line, and a TFT connected to the TFT It includes a pixel electrode in response to the operation of.

 Hereinafter, a liquid crystal display for compensating data charging time according to an exemplary embodiment of the present invention having the configuration of FIG. 2 will be described with reference to FIG. 3.

The timing controller 10 receives horizontal and vertical synchronization signals, data signals, and the like from a graphic controller (not shown) and outputs a signal for driving the gate driver 20 and the source driver 30.

In this case, the gate clock CPV and the gate-on enable signal OE output from the timing controller 10 to the gate driver 20 show a waveform as shown in FIG. 3. FIG. 3 is a waveform diagram of a signal output from a timing controller of a liquid crystal display for compensating for data charging time according to an exemplary embodiment of the present invention, and is represented based on one frame.

In FIG. 3, a is a gate clock CPV, b is an OE signal occurring at the n-1 th time, c is a data voltage Dn-1 charged at a pixel connected to the n-1 th gate line, and d is n The gate-on voltage Gn-1 applied to the -1th gate line. And e is the n-th generated OE signal, f is the data voltage Dn charged in the pixel connected to the n-th gate line, and g is the gate-on voltage Gn applied to the n-th gate line.

The CPV of a proceeds along the time axis with a certain period, and the OE signal of b generates a rising edge in synchronization with the rising edge of the gate clock CPV and a falling edge after a predetermined time.

The gate-on voltage Dn-1 of d toggles to a high level in synchronization with the falling edge of the OEn-1 signal and then toggles to a low level in synchronization with the rising edge of the next OEn signal. Accordingly, the gate-on signal Gn-1 is applied to the n-1th gate line to turn on the TFT, thereby charging the pixel with the data voltage Dn-1 applied through the data line.

In this case, assuming that the data voltage Dn-1 is not significantly affected by the delay of the data line, the data voltage Dn-1 is charged in the corresponding pixel during Tn-1 ', which is synchronized with the high period of the gate-on voltage Gn-1 as shown in d. .

However, as described with reference to FIG. 1, the data voltage charged in the pixel connected to the gate line after the n-th gate line is not synchronized with the high level period of the gate-on voltage due to the delay of the data line, thereby shortening the charging time. .

However, the present invention prevents the above charging time from being shortened by generating an OE signal, e.g., the nth OEn signal, which is delayed by A time as e, in proportion to the delay of the data line.

  In detail, the OE signal is a signal that determines the generation time of the gate-on voltage and is independent of the data voltage. Therefore, if OEn is delayed by A time as in d, the gate-on voltage Gn is delayed by A time, and accordingly, the high level period of the data voltage Dn delayed by A time as shown in g of FIG. The coincidence is made to be the target charging time Tn-1. That is, it makes Tn 'equal to Tn-1'.

Here, the delay time of the OE signal output from the timing controller 10 is not constant. This is because the delay time of the data voltage applied to the pixel connected to each gate line is different with respect to each gate line, and the present invention takes into account the delay of the data voltage depending on the position of the pixel. Determine the delay.

Therefore, the OE output from the timing controller 100 of the present invention may be generated by gradually delaying and varying the degree of delay based on a predetermined CPV.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, the present invention has the effect of compensating the data charging time by delaying the generation of the gate-on voltage in consideration of the application time of the data voltage delayed by the resistance component of the data line.

Claims (4)

A liquid crystal panel in which a plurality of data lines, a plurality of gate lines insulated and vertically intersected with the plurality of data lines, and pixels including pixel electrodes, common electrodes, and thin film transistors are arranged in a matrix form; Outputs the horizontal and vertical synchronizing signal, data voltage, and gate clock to display an image on the liquid crystal panel, Vstart indicating the start of the gate-on signal applied from the outside, and an output enable considering the resistance component of the data line. A timing controller configured to output a timing signal to be output; A source driver which drives according to a timing signal output from the timing controller and applies a data signal to the data line; And A gate driver sequentially applying a gate driving signal generated in synchronization with the gate clock, the Vstart, and the output enable signal output from the timing controller to a gate line; And a gate driving signal is delayed from a gate line applied first to a gate line applied last according to the output enable. The method of claim 1, The timing controller, And an output enable signal in which the final signal is delayed by a predetermined value based on one frame. The method of claim 2, The output enable signal, A liquid crystal display device for compensating for data charging time, wherein a delay time is gradually increased based on one frame. The method of claim 2, The output enable signal, A liquid crystal display device for compensating for data charging time, wherein the delay time is gradually increased by using the gate clock as a unit based on one frame.

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