KR19990060025A - Thin film transistor substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

In the thin film transistor substrate for a liquid crystal display device, the size of the pixel electrode is gradually reduced from the input terminal to the output terminal of the scan signal of the gate line. In this way, the decrease in the kickback voltage as the delay of the gate line signal increases and the increase in the kickback voltage as the liquid crystal capacitance gradually decreases, thereby making the kickback voltage constant.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof

This invention relates to the thin-film transistor substrate for liquid crystal display devices, and its manufacturing method.

The thin film transistor substrate for a conventional liquid crystal display device will now be described.

FIG. 1 is a layout view schematically showing a conventional thin film transistor substrate for a liquid crystal display device, in which a gate line 1 extends horizontally and a data line 2 extends vertically. And a rectangle formed by the intersection of two rows of data lines 2 form one pixel. Each thin film transistor 4 and one pixel electrode 3 are formed in each pixel. The gate electrode, the source electrode, and the drain electrode of the thin film transistor 4 are connected to the gate line 1, the pixel electrode 3, and the data line 2, respectively, and the pixel electrode 3 is adjacent to the gate line ( 1) and a part thereof are formed to overlap each other, so that the storage capacitor Cst is formed between the gate line 1 and the pixel electrode 3, and all pixel electrodes have a constant size.

In a liquid crystal display using the thin film transistor having such a structure, flicker of the screen serves as an important problem of degrading the image quality. However, screen flicker can be caused by delay capacitance (RC) of the gate line signal, current leakage by thin film transistors and liquid crystal materials, and kickback voltage due to parasitic capacitance (Cgs) between the gate electrode and the source electrode. As a result, the symmetry between the upper and lower sides of the pixel electrode voltage is broken based on the common electrode voltage. In order to eliminate flicker, efforts have been made to remove parasitic capacitance and prevent current leakage. However, there is no improvement in the effects of signal delay.

The technical problem to be achieved by the present invention is to eliminate the influence of the screen flicker of the liquid crystal display device due to the signal delay of the gate line of the liquid crystal display device.

1 is a layout view of a thin film transistor substrate for a conventional liquid crystal display device,

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating voltage waveforms of a gate line signal, a data line signal, and a pixel electrode applied to a thin film transistor for a liquid crystal display device.

In order to solve the above problems, the present invention forms different size of pixel electrodes for each pixel. The size of the pixel electrode is formed to decrease gradually from the input terminal to the output terminal of the gate line so that the kickback voltage is constant throughout the screen.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a gate line 10 having a pad 11 for connecting to a driving circuit at the left end thereof extends horizontally, and a data line 20 extends vertically. A rectangle formed by the intersection of 10) and the two rows of data lines 20 forms one pixel. In each pixel, one thin film transistor 40 and one pixel electrode 30 are formed. The gate electrode, the drain electrode, and the source electrode of the thin film transistor 40 are connected to the gate line 10, the data line 20, and the pixel electrode 30, respectively, and the pixel electrode 30 is adjacent to the gate line ( 10 and a portion overlap each other to form a storage capacitor Cst between the gate line 10 and the pixel electrode 30, and the pixel electrode (from the left side, which is an input terminal of the gate line signal, to the right side, which is an output terminal). 30) is formed to become smaller in size.

On the other hand, although not shown, the upper substrate on which the common electrode is formed is opposite to the substrate shown in FIG. 2, and the pixel electrode and the common electrode form a liquid crystal capacitor together with the liquid crystal material therebetween.

The reason why the size of the pixel electrode is gradually reduced from the input terminal to the output terminal of the gate line will be described.

3 is a diagram illustrating waveforms of a common electrode voltage, a gate signal voltage, a data line signal voltage, and a pixel electrode voltage, wherein the gate signal voltage Vg and the data line signal voltage Vd are assigned to one gate line and one data line, respectively. The voltage is applied and the common electrode voltage Vcom is a voltage applied to the common electrode.

Referring to Fig. 3, first, a kick back voltage will be described.

The gate signal applied to one gate line has a high voltage value VgH in the form of a pulse at regular intervals, and this high voltage VgH is applied to each gate line in turn. When a high voltage VgH is applied to a gate line, a data signal of a pixel connected to the gate line is applied to the pixel electrode of the pixel through each data line and the thin film transistor connected thereto. When the data signal Vd is applied to all the pixels in this manner, the high voltage VgH is applied to each gate line in turn, and the above-described operation is repeated. In this case, however, the data signal has a signal opposite to that of the previous data signal, that is, an inverted value, with respect to the common electrode voltage Vp. Accordingly, in FIG. 3, the gate voltage Vg applied to one gate line represents a waveform in which a high voltage in a pulse form is applied at a constant cycle, and the data voltage Vd is periodically inverted with respect to the common electrode voltage Vcom. Indicates the waveform.

3, when the data line voltage is inverted from VdL to VdH, and then a gate pulse is applied to increase the gate voltage from VgL to VgH, the channel of the thin film transistor is opened and through the channel to the drain electrode. Positive charges flow into the source electrode and accumulate in the pixel electrode. As positive charges accumulate in the pixel electrode, the pixel electrode voltage Vp gradually increases to rise to VdH. Subsequently, when the gate voltage drops from VgH to VgL, the channel of the thin film transistor is cut off, and at this moment, the voltage difference between the gate electrode and the source electrode becomes larger than the voltage difference between the pixel electrode and the common electrode. It is dispersed and received by the source electrode, so that the voltage of the pixel electrode drops slightly. The pixel electrode voltages falling together at the moment when the gate voltage falls from VgH to VgL are called kickback voltages. Subsequently, when the data line voltage held at VdH is inverted to VdL, and then the gate voltage is increased from VgL to VgH, the channel of the thin film transistor is opened again, and positive charge accumulated in the pixel electrode flows out through this channel. As the accumulated positive charges flow out, the pixel electrode voltage gradually decreases to VdL, and negative charges are distributed in the pixel electrode. Subsequently, when the gate voltage drops from VgH to VgL, the channel of the thin film transistor is cut off, and at this moment, the voltage VgL of the gate electrode becomes lower than the voltage VdL of the source electrode, and positive charges drawn from the pixel electrode accumulate on the source electrode. do. Thus, more negative charge remains on the pixel electrode, resulting in a slightly lower voltage.

That is, as shown in FIG. 3, the kickback voltage always acts in the direction of pulling down the pixel electrode voltage Vp regardless of the polarity of the voltage applied to the pixel electrode, and thus the pixel electrode voltage based on the common electrode voltage Vcom. This breaks the symmetry between (Vp) and up and down, which is caused by screen flicker.

Next, the relationship between the gate line signal delay and the kickback voltage will be described.

The circuit of the thin film transistor substrate has a resistance component and a capacitance component. Therefore, the scan signal applied through the gate line is slightly delayed, and the degree increases from the input side to the output side. However, the delay of the gate signal means that the signal waveform does not fall vertically but falls in a curved line. The dotted line in FIG. 3 represents the delay of the gate signal. That is, when the delay of the gate signal is large, the fall time of the gate signal pulse becomes long. During this time, the positive charge flows into the pixel electrode without the channel of the thin film transistor being completely blocked. In this case, due to the parasitic capacitance between the gate electrode and the source electrode, the positive charge received in the source electrode flows through the channel instead of being drawn from the pixel electrode. Thus, the kickback voltage is reduced. As a result, the kickback voltage decreases as the delay of the gate signal increases. However, since the gate signal delay increases as the distance from the input increases, the kickback voltage decreases as it moves away from the input, and this change in kickback voltage causes one of the screen flickers.

The kickback voltage is expressed as follows assuming no signal delay.

Vk: Kickback voltage, ΔVg = VgH-VgL, ΔVd = VdH-VdL,

Vth: threshold voltage of thin film transistor, Cst: storage capacitance,

Clc: liquid crystal capacitance, Cgson: parasitic capacitance between the gate and the source when the channel is connected,

Cgsoff: Parasitic capacitance between gate and source during channel disconnection

As can be seen from the above equation, the kickback voltage Vk increases as the liquid crystal capacitance Clc decreases. Therefore, when the size of the pixel electrode is gradually decreased from the gate line input terminal to the output terminal, and the liquid crystal capacitance is gradually reduced, the kickback voltage Vk can be prevented from becoming smaller due to the gate signal delay becoming larger, and thus the kickback voltage. The size of (Vk) can be made constant. In this case, the flicker of the entire screen may be eliminated by lowering the common electrode voltage Vcom by the kickback voltage Vk.

In view of the above equation, there is a method of changing the kickback voltage in addition to the liquid crystal capacitance, but also a method of changing the parasitic capacitance and the holding capacitance.

When there is no signal delay of the gate line, if the size of the pixel electrode is made smaller from the gate line input terminal to the output terminal, the liquid crystal capacitance becomes smaller and the kickback voltage becomes larger. However, as the distance from the input terminal of the gate line increases, the degree of signal delay increases, and thus the kickback voltage decreases. Therefore, the effects of the smaller and smaller pixel electrodes and the increasing degree of signal delay cancel each other out so that the kickback voltage becomes constant. In this case, it is possible to eliminate flicker of the entire screen by changing the common electrode voltage.

Claims (3)

A plurality of gate lines extending in a first direction, A plurality of gate line pads formed at one end of the gate line and configured to introduce a scan signal to the gate line; A plurality of data lines insulated from and intersecting the gate lines; A plurality of pixel regions in which the gate lines and the data lines cross each other, A plurality of thin film transistors having the gate line and the data line connected to the first and second terminals, respectively; And a plurality of pixel electrodes connected to the third terminal of the thin film transistor and having different areas. In claim 1, The pixel electrode is formed to occupy a smaller area as it is farther from the gate line pad. In claim 1, And the pixel electrode is formed to overlap a portion of the gate line adjacent to the gate line connected to the thin film transistor to which the pixel electrode is connected.