JPH0846204A - Display device - Google Patents

Abstract

PURPOSE:To bring field concentration generated in the drain-side P-N junction section of a transistor immediately after the completion of charging to zero, reduce the leakage current and prevent the deterioration of an image signal by connecting a thin-film transistor in series and mounting a capacitor on the connecting section of the thin-film transistor. CONSTITUTION:A capacitor 20 is connected previously to the connecting section 21 of transistors 18 and 19. When gate voltage 18V is applied to a wiring 17, voltage is applied to the gate electrodes of the transistors 18, 19, the transistors are brought to an on state, and an image signal is charged to capacitors 20 and 15 with a delay of 20 milliseconds. Gate voltage in pulse width of 200 milliseconds is changed into -15V, the transistors 18 and 19 are brought to an off state, and the image signal is also altered to 0V with a delay of 20 milliseconds. Voltage between the source and drain of the transistor 18 is 0V because the voltage of the capacitors 15 and 20 is equalized approximately. Accordingly, there is no field concentration in the drain-side P-N junction section of the transistor 18, thus extremely reducing leakage currents.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor thin film transistor circuit having a structure for reducing source / drain leakage current.

A case where the present invention is applied to an active matrix panel for realizing a thin display using an inexpensive insulating substrate or an image sensor will be described below, but the present invention is also applicable to other electric circuits using thin film transistors. It can be applied in exactly the same way. This is because the purpose of the present invention is to improve the essential characteristics of the thin film transistor, which is to reduce the leakage current.

[0003]

2. Description of the Related Art A liquid crystal display device in which a thin film transistor is applied to an active matrix panel is generally composed of a lower thin film transistor substrate, an upper glass substrate, and a liquid crystal enclosed between them. By selecting the liquid crystal active elements arranged in a matrix by an external selection circuit, and applying a voltage to the liquid crystal drive electrode connected to the liquid crystal active element,
Pixels are displayed. A general circuit diagram of the thin film transistor substrate is shown in FIGS.

FIG. 1 is a diagram in which liquid crystal driving elements on a thin film transistor substrate are arranged in a matrix. Reference numeral 1 in the drawing is a display area, in which liquid crystal driving elements 2 are arranged in a matrix. Reference numeral 3 is a data signal line to the liquid crystal drive element 2, to which a pixel signal is input. Reference numeral 4 is a timing signal line to the liquid crystal drive element 2. A circuit diagram of the liquid crystal drive element 2 is shown in FIG. Reference numeral 5 is a thin film transistor for switching data. Reference numeral 6 is a capacitor, which is used to hold a data signal. The capacity of this capacitor includes the capacity of the liquid crystal itself and the capacity of a capacitor provided as an element other than that, but it may be only the capacity of the liquid crystal depending on the panel. 7-1 is a liquid crystal drive electrode formed corresponding to each liquid crystal drive element, and 7-2 is an electrode provided on the upper glass panel. As can be seen from the above description, the thin film transistor 5 is used for switching the data of the voltage applied to the liquid crystal.

At this time, the thin film transistor 5 is required to have as much as possible when the thin film transistor is turned off.
It is to prevent the source / drain current from flowing.

The data written in the capacitor 6 must generally be held for one frame time. Since the capacitance of the capacitor 6 is a small value of 1 pF or less, the voltage of the capacitor 6 sharply decreases if there is a slight leak current when the thin film transistor is in the OFF state. That is, the voltage between the source and the drain decreases so as to be equal, and the written data cannot be held correctly. Therefore, the leakage current should be as small as possible. As a conventional technique for dealing with such leakage current, a plurality of thin film transistors are connected in series, the electrodes at both ends thereof are used as a source electrode and a drain electrode, and each gate electrode has a common structure in which the same voltage is applied. Japanese Patent Publication No. 5 using liquid crystal drive elements
The methods described in US Pat. Nos. 44195 and 5-44195 have been proposed. In this case, the intensity of the electric field generated at the drain end of each transistor is reduced to one-hundredth of that when there is only one transistor, so that the leak current is reduced.

[0007]

FIG. 3 shows the leak current characteristic of the N-channel thin film transistor. The channel length L of the transistor is 10 μm, and the channel width W is 100 μm. The horizontal axis of this graph is the drain voltage V _DS with respect to the source, and the vertical axis is the leak current when the gate voltage V _G = −3V. Hereinafter, there will be described problems when the thin film transistor having such characteristics is used in the liquid crystal display device of FIGS.

An image signal for driving the liquid crystal is input to the data signal wiring of FIG. 2, which normally has an amplitude of ± 7V. For example, assume that a + 7V signal is stored in the capacitor when the thin film transistor 5 is in the ON state.
After that, when -7V is input to the data signal line in the OFF state, a maximum voltage of 14V is applied between the source and the drain of the thin film transistor 5. From the leakage current characteristics shown in FIG. 3, when V _G = −3V is applied to turn off, the leakage current increases by 2.5 digits when V _DS increases from 0.5V to 15V, from 10 ⁻¹¹ A. 5 x 1
It becomes 0 ^-9 A.

As shown in FIG. 3, at the time of reverse bias in which V _G is negatively biased, leakage current causes a PN junction formed between the p-type region formed in the channel layer and the n-type region of the drain. It is defined by the current flowing through. Since many defects exist in the semiconductor of a thin film transistor, this PN junction is incomplete and a junction leak current easily flows. In addition, a tunnel current is generated via the energy gap level resulting from the defect in the semiconductor. As the gate voltage becomes negative and increases, and the drain voltage increases, electric field concentration occurs at the PN junction, and the leak current increases.

As a conventional technique for coping with such a leak current, a plurality of thin film transistors are connected in series, the electrodes at both ends thereof are used as a source electrode and a drain electrode, and a common voltage is applied to each gate electrode. Japanese Patent Publication No. 5-44195, using liquid crystal driving element having structure
The method described in 44196 has been proposed. FIG. 4 shows a circuit configuration when the number of thin film transistors is two. The N-channel thin film transistor characteristics when the present method is used are shown in FIG. The horizontal axis of FIG. 5 represents the gate voltage, and the vertical axis represents the current flowing between the electrodes at both ends connected in series, that is, the current between the source and the drain. The channel length L of each transistor is 15 μm, and the channel width W is also 15 μm.
Is. The voltage between the source and drain is 10V. The characteristic curve 8 is the case where the number of thin film transistors is one, the characteristic curve 9 is two in series, and the characteristic curve 10 is three. The leakage current decreases as the number of thin film transistors connected in series increases, but the rapid increase when the gate voltage is negatively biased is not improved.

[0011]

SUMMARY OF THE INVENTION The present invention provides a thin film transistor having the characteristic of improving the pixel signal holding ability due to such leak current. A configuration of the present invention for realizing this is shown in FIG. The transistor 11 is connected in series to the transistor 5, and the other electrode of the transistor 5 is connected to the capacitor 6 and the liquid crystal driving electrode 7
−1, the other electrode of the transistor 5 is connected to the data signal line 3, the gate electrodes of the transistors 5 and 11 are connected to the timing signal line 4, and the connecting portion 13 of the transistor 5 and the transistor 11 is connected to the capacitor 12 Connect to.

That is, a plurality of pixel electrodes arranged in a matrix on a substrate are provided, thin film transistors are connected to the pixel electrodes, and N (N ≧ 2) thin film transistors are formed in one pixel. The N thin film transistors are connected in series, one end of the thin film transistors connected in series is electrically connected to a video signal line, and the other end is electrically connected to a pixel electrode. A display device connected to a capacitive load is provided at each of the connection parts.

[0013]

The operation of the present invention will be described with reference to FIG. A signal is input from the timing signal line 4 and the transistor 5
And 11 are turned on, and the data signal line 3
The image signal held in the liquid crystal capacitor 7 and the signal holding capacitor 6 is input from. Transistors 5 and 11 are O
The voltage charged in the liquid crystal capacitor 7 during the N state is substantially equal to the image signal voltage. The transistors 5 and 11 are turned on until such a voltage state is reached, and when the charging is completed, the transistors 5 and 11 are turned off.
Set to F state. Thereafter, a voltage difference between the image signal charged in the capacitor 12 and the data signal line 3 is applied between the source and drain of the transistor 11. The voltage of the data signal line 3 changes with time, and a large voltage may be applied between the source and drain of the transistor 11. In that case, the charging voltage of the capacitor 12 decreases due to the leak current of the transistor 11.
On the other hand, a voltage that is the difference between the charging voltages of the capacitors 11 and 6 is applied between the source and drain of the transistor 5. Immediately after the transistors 11 and 5 are turned off, the charging voltages of the capacitor 12 and the capacitor 6 are equal, so that no voltage is applied between the source and drain of the transistor 5.

Therefore, since electric field concentration does not occur at the drain side PN junction of the transistor 5, as can be seen from the characteristic curve of FIG. 3, the leak current flowing through the transistor 5 is extremely small and the voltage of the capacitor 6 and the liquid crystal capacitance 7 is small. Also hardly decreases. After a lapse of time, the charging voltage of the capacitor 12 decreases due to the leak current of the transistor 11, so that a voltage is generated between the source and drain of the transistor 5 and the leak current starts to flow. However, unlike the transistor 11, since a large voltage is not applied between the source and the drain, the leak current is small and the voltage drop of the capacitor 6 and the liquid crystal capacitance 7 can be reduced.

According to the present invention, by providing the capacitor 12, the electric field concentration generated at the drain side PN junction portion of the transistor 5 immediately after the end of charging is reduced to 0, so that the leak current is reduced and the image signal is prevented from being lowered. Therefore, the operating state of the transistor different from the method described in JP-B-5-44195 and 5-44196 is used. Hereinafter, the content of the present invention will be described in detail with reference to examples.

[0016]

FIG. 9 is a circuit diagram of an embodiment used to show the effect of the present invention. Transistors 18 and 19 are thin film transistors using a polycrystalline silicon thin film as a channel active layer, and have a channel length of 10 μm and a channel width of 50 μm. The threshold voltage of the transistor is 3
It was V. Capacitor 15 represents the capacitive load of the instrument used to examine output 22 of transistor 18 and is approximately 18 pF. 7 and 8 show circuit diagrams of a conventional example for comparison with the present invention. FIG. 7 is a circuit diagram of a conventional example in which only one thin film transistor is used. FIG.
FIG. 4 is a circuit diagram of a conventional example using the method described in JP-B-5-44195 and 5-44196. The transistor 14 is shown in FIG.
Is a thin film transistor using a polycrystalline silicon thin film as a channel active layer like the transistors 18 and 19 of
The channel length is 10 microns and the channel width is 50 microns.

FIG. 10 shows a timing chart of voltage signals used in this embodiment. Transistors 14, 18, 1
The gate voltage signal applied to the gate electrode of No. 9 is applied through the timing signal line 17, and the pulse width is 200.
It is a millisecond and has an amplitude of -15V to 18V. The image signal input through the transistor is applied through the data signal line 16 and has a pulse width of 200 milliseconds, but is input at a timing 20 milliseconds behind the gate voltage signal. It has an amplitude of 0V to 12V. A measuring probe having a load capacitance of 12 pF was connected to the connecting portions 22, 23 and 24 in order to measure the time change of the voltage of the connecting portions 22, 23 and 24.

The result of the conventional example for the circuit configuration of FIG. 7 is shown by a curve 25 in FIG. After the voltage of 18V is applied to the gate electrode and the transistor 14 is turned on,
The image signal of 12V is applied with a delay of 20 milliseconds. The voltage of the connecting portion 23 increases accordingly and reaches 12V. 20
After 0 ms, the gate voltage becomes -15 V and the transistor 14 is turned off. After 20 ms, the image signal becomes 0 V. At this time, the source of the transistor 14,
There is a voltage difference of 18V between the drains, and -15V is applied to the gate electrode. Transistor 14 is in the reverse bias state, and its leakage current increases in the same manner as shown in characteristic curve 8 of FIG.
The voltage of is decreasing. After the image signal changed from 12V to 0V, the time at which the voltage at the point 23 became 50%, 6V, was about 0.18 milliseconds.

Next, the result of the conventional example for the circuit configuration of FIG. 11 is shown by a curve 26 in FIG. After a voltage of 18V is applied to the gate electrode and the transistors 18 and 19 are turned on, a 12V image signal is applied with a delay of 20 milliseconds. The voltage of the connecting portion 23 increases accordingly and reaches 12V. After 200 milliseconds, the gate voltage becomes -15V and the transistors 18 and 19 are turned off, and then the image signal becomes 0V with a delay of 20 milliseconds. At this time, 18V is applied between the electrodes at both ends where the transistors 18 and 19 are connected in series.
-15V is applied to the gate electrode. Transistors 18 and 19 are reverse biased and their leak electrodes are shown in characteristic curve 9 of FIG. At this time, the source-drain voltage per transistor is half, about 6 V, and the electric field strength generated at the PN junction of the transistor is reduced to 1/2, so that the leakage current of the transistor is also reduced. Point 2 when 0.18 milliseconds has elapsed after the image signal changed from 12V to 0V
The voltage of 4 was about 10.6V. Although it is improved as compared with the case of one transistor in FIG. 7, about 10% of the original image signal is lost.

Next, the results of the present invention will be described with reference to FIGS. 9 and 10. As shown in FIG. 9, the capacitor 20 is connected to the connecting portion 21 between the transistors 18 and 19. The capacitance of the capacitor 20 was 12 pF. It is desirable that the capacity of the capacitor 20 be substantially equal to or larger than that of the capacitor 15. The gate electrode has a pulse width of 200 milliseconds and an amplitude of -15V to 18V, as in the above-mentioned conventional example. The image signal has a pulse width of 200 milliseconds, but is input at a timing 20 milliseconds behind the gate voltage signal. When the gate voltage 18V is applied to the wiring 17, a voltage is applied to the gate electrodes of the transistors 18 and 19, the transistors are turned on, and the image signal is charged in the capacitors 20 and 15 from the wiring 16 with a delay of 20 milliseconds. Gate voltage with a pulse width of 200 milliseconds is -15
After changing to V and turning off the transistors 18 and 19, the image signal also changes to 0V with a delay of 20 milliseconds. At this time, the OFF state of the transistor differs between the transistors 18 and 19. First, the voltage between the source and drain of the transistor 18 is 0V because the voltages of the capacitors 15 and 20 are substantially equal. Therefore, since there is no electric field concentration at the drain side PN junction of the transistor 18, the leak current is extremely low.

On the other hand, in the bias state of the transistor 19, a voltage of 18V is applied between the source and the drain, and the gate voltage is in a reverse bias state of -18V. A large leak current flows through the transistor 19 in the reverse bias state, and the charging voltage of the capacitor 20 decreases. Since a voltage is generated between the source and drain of the transistor 18 as the voltage of the capacitor 20 drops, the leak current of the transistor 18 also slightly increases. However, the voltage between the source and the drain of the transistor 18 is still less than half of the total voltage of 12V, that is, 6V, and the electric field concentration generated in the drain side PN junction is smaller than that in the case of the conventional example FIG. Since it is weak, the leak current flowing through the transistor is smaller than that in the above embodiment. The result of measuring the time change of the voltage of the connection portion 22 is shown by the curve 2 in FIG.
7 shows. The voltage of the connection portion 22 after the lapse of 0.18 milliseconds after the image signal changed to 0V was about 11.7V.
It has been found that the voltage drop can be further suppressed as compared with the prior art.

In this embodiment, since the capacitive load of the measuring instrument for measuring the time change of the voltage is about 12 pF, the capacitance of the capacitor 15 is 12 pF, but in the case of a normal active matrix display device, The capacitance corresponding to the capacitor 15 is 1 pF or less. In that case, it is desirable that the capacitance of the capacitor 20 be equivalent to or larger than that of the capacitor 15. Even in that case, the effect of the present invention is not impaired.

In the present embodiment, two thin film transistors are connected in series. However, the number of thin film transistors is further increased, and a capacitor is connected to each connection in the same manner as the capacitor 20, so that the voltage drop at the connection 22 is further reduced. It becomes possible to suppress.

[0024]

As described above, the present invention provides a thin film transistor device having an excellent effect that can reduce the voltage drop of the charging signal due to the leak current by adopting the configuration as described above. It is a thing. By utilizing the present invention, a thin film transistor having a large leak current in a reverse bias state can be used in an active matrix display device and a high quality image can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram when a thin film transistor is applied to an active matrix display device.

FIG. 2 is a configuration diagram around a thin film transistor in a conventional display device.

FIG. 3 is a diagram showing a relationship between a drain current and a leak current between a source and a drain in a reverse bias state in which a gate voltage of an N-channel thin film transistor is made negative.

FIG. 4 is a configuration diagram when two transistors are connected in series.

FIG. 5 is a transistor characteristic diagram when a plurality of (1 to 3) transistors are connected in series.

FIG. 6 is a configuration diagram showing an embodiment of the present invention.

FIG. 7 is a configuration diagram showing a conventional example.

FIG. 8 is a configuration diagram showing a conventional example.

FIG. 9 is a diagram for explaining an example of the present invention.

FIG. 10 is a timing chart of voltage signals used in the examples of the present application.

FIG. 11 is a diagram showing changes in the voltage of the connection portion with time in the conventional example and the example of the present application.

[Explanation of symbols]

 1 Display Area 2 Liquid Crystal Driving Element 3,16 Data Signal Line 4,17 Timing Signal Line 5 Thin Film Transistor 6 Capacitor 7-1 Liquid Crystal Driving Electrode 7-2 Upper Glass Panel 8, 9, 10 Characteristic Curve of Thin Film Transistor 11, 14, 18, 19 Thin film transistor 12, 15, 20 Capacitor 13, 22, 23, 24 Connection part

Claims (1)

[Claims] 1. A plurality of pixel electrodes arranged in a matrix on a substrate, and a thin film transistor is connected to the pixel electrode. N (N ≧ 2) thin film transistors are formed in one pixel. The N thin film transistors are connected in series, one end of the thin film transistors connected in series is electrically connected to a video signal line, and the other end is electrically connected to a pixel electrode. A display device characterized in that a capacitive load is connected to each connection part of the display device.