JPH02154467A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02154467A
JPH02154467A JP30861388A JP30861388A JPH02154467A JP H02154467 A JPH02154467 A JP H02154467A JP 30861388 A JP30861388 A JP 30861388A JP 30861388 A JP30861388 A JP 30861388A JP H02154467 A JPH02154467 A JP H02154467A
Authority
JP
Japan
Prior art keywords
series
tpts
thin film
current
tpt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30861388A
Other languages
Japanese (ja)
Inventor
Kazuo Yudasaka
一夫 湯田坂
Hiroyuki Oshima
弘之 大島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP30861388A priority Critical patent/JPH02154467A/en
Publication of JPH02154467A publication Critical patent/JPH02154467A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To decrease only an OFF-state current without decreasing an ON-state current by connecting two or more thin film transistors of different threshold voltage in series and making a gate electrode common to all the transistors. CONSTITUTION:Two or more thin film transistors T1-Tn of different threshold voltage are connected in series, electrodes on both the ends of the thin film transistors T1-Tn connected in series are made a source electrode S and a drain electrode D, and a gate electrode G common to all the thin film transistors T1-Tn connected in series is made. Thereby only an OFF-state current can be decreased without decreasing an ON-state current and gate voltage can be decreased over a wide range.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、薄膜トランジスタ(以下TPTと略す)にお
いて、所僅の電気的特性を得るために、複数個のTPT
を接続する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) in which a plurality of TPTs are used in order to obtain certain electrical characteristics.
Regarding how to connect.

[従来の技術] 通常、1つのTPTにおいて、所望の電気的特性を得る
ための工夫は、該TPTの構造や製造条件が対象となる
。しかし、前記TPTの構造や製造条件を工夫しても、
1つのTPTだけでは所望の電気的特性が得られない場
合がある。前記場合には、従来電気的には同一の基本特
性を持つTPTを、直列乃至並列に接続していた。
[Prior Art] Usually, efforts to obtain desired electrical characteristics in a single TPT focus on the structure and manufacturing conditions of the TPT. However, even if the structure and manufacturing conditions of the TPT are devised,
Desired electrical characteristics may not be obtained with only one TPT. In the above case, TPTs having electrically the same basic characteristics were conventionally connected in series or in parallel.

例えば、高電圧で使用するため高耐圧のTPTが必要な
ときは、電気的には同一の基本特性を持つ基本となるT
PTを直列に接続していた。また、大電流が必要な時は
、電気的には同一の基本特性を持つ基本となるTPTを
並列に接続していた。
For example, when a high-voltage TPT is required for use at high voltage, a basic TPT with the same basic electrical characteristics is required.
The PTs were connected in series. Furthermore, when a large current was required, basic TPTs having the same basic electrical characteristics were connected in parallel.

また、TPTのリーク電流を低減したいときは、電気的
には同一の基本特性を持つ基本となるTPTを直列に接
続していた。
Furthermore, when it is desired to reduce the leakage current of TPTs, basic TPTs having electrically identical basic characteristics are connected in series.

[発明が解決しようとする課題] TPTの適用製品に液晶パネルがある。すでにTPTを
用いた数インチの液晶パネルが量産され、さらに大きな
サイズのパネルが研究されている。
[Problems to be Solved by the Invention] Liquid crystal panels are examples of products to which TPT is applied. Several-inch LCD panels using TPT have already been mass-produced, and even larger panels are being researched.

また前記パネルの解像度など表示品質の向上の研究もさ
れている。しかしTPTは通常ガラス基板上に、非結晶
Siを用いて形成されるため、その電気的特性は、大き
なサイズの液晶パネルを表示したり、液晶パネルの表示
品質を向上するためには必ずしも十分ではなかった。T
PTは非結晶Siを用いているため、本質的にオン電流
が小さく、オフ電流(リーク電流)が大きいからである
Research is also being conducted into improving display quality such as the resolution of the panel. However, since TPT is usually formed using amorphous Si on a glass substrate, its electrical characteristics are not necessarily sufficient for displaying large-sized liquid crystal panels or improving the display quality of liquid crystal panels. There wasn't. T
This is because PT uses amorphous Si, so its on-current is essentially small and its off-current (leakage current) is large.

特にTPTに要求されるオフ電流は、液晶パネルの駆動
方式の特徴のため、ゲート電圧の広い範囲にわたって低
い値である必要がある。例えばNチャネル型のTPTで
は、ゲート電圧がOvから一1Ov程度の範囲で、低い
オフ電流が要求される。
In particular, the off-state current required for the TPT needs to be a low value over a wide range of gate voltages due to the characteristics of the driving method of the liquid crystal panel. For example, in an N-channel type TPT, a low off-state current is required when the gate voltage ranges from Ov to about -1 Ov.

しかし、非結晶Siを用いて形成されるTPTは、ゲー
ト電圧がマイナス方向に大きくなると、オフ電流が大き
くなるという問題点を有する。ドレイン側に形成される
P−N接合のリーク電流が増加するためである。前記オ
フ電流の増加は、TPTから液晶パネルの画素に書き込
まれたデータ信号の電圧を低下させ、従って液晶パネル
の表示品質を低下させる。TPTのオフ電流を下げるた
め、従来電気的には同一の基本特性を持つ基本となるT
F′rを直列に接続する方法があった。しかし電気的に
同一の基本特性を持つT FTを複数個直列に接続する
と、オン電流は前記基本特性を持つTPTlつのオン電
流に比べて確実に低下する。
However, TPTs formed using amorphous Si have a problem in that off-state current increases as the gate voltage increases in the negative direction. This is because the leakage current of the PN junction formed on the drain side increases. The increase in the off-state current lowers the voltage of the data signal written from the TPT to the pixels of the liquid crystal panel, thereby degrading the display quality of the liquid crystal panel. In order to lower the TPT's off-state current, the basic TPT with the same basic electrical characteristics has been
There was a method of connecting F'r in series. However, when a plurality of TFTs having electrically identical basic characteristics are connected in series, the on-current is definitely lower than the on-current of one TFT having the basic characteristics.

従って本発明の目的は、オン電流を低下させることなく
、オフ電流がゲート電圧の広い範囲にわたって低いTP
Tを提供することである。
Therefore, an object of the present invention is to provide a TP with low off-current over a wide range of gate voltages without reducing on-current.
It is to provide T.

[課題を解決するための手段] 本発明において前記問題点を解決するための手段は、 (1)ソース電極とドレイン電極とゲート電極を備えた
薄膜トランジスタにおいて、閾値電圧が互いに異なる2
つ以上の前記薄膜トランジスタを直列に接続し、前記直
列に接続された薄膜トランジスタの両端の電極をソース
電極およびドレイン電極とし、且つ前記直列に接続され
た薄膜トランジスタの総てのゲート電極を共通にするこ
とを特徴とする。
[Means for Solving the Problems] Means for solving the problems in the present invention are as follows: (1) A thin film transistor including a source electrode, a drain electrode, and a gate electrode has different threshold voltages.
Two or more of the thin film transistors are connected in series, electrodes at both ends of the thin film transistors connected in series are used as a source electrode and a drain electrode, and gate electrodes of all the thin film transistors connected in series are common. Features.

[実施例] 本発明の詳細を実施例により、以下に説明する。第1図
は本発明による実施例である。第1図においてT工、T
2.・・・Tnはn個のTPTであり、直列に接続され
ている。前記直列に接続されたn個のTPTの両端は、
それぞれソースおよびドレインとなっている。前記n個
のTPTのゲートは総て共通となっている。従って前記
n個のT 、F Tは全体として1つのTPTと見なす
ことが出きる。前記n個のTPTにおいて、少なくとも
2つ以上のTPTでVthが異なっている。
[Examples] The details of the present invention will be explained below using Examples. FIG. 1 shows an embodiment according to the invention. In Figure 1, T-work, T
2. ...Tn is n TPTs connected in series. Both ends of the n TPTs connected in series are:
They serve as the source and drain, respectively. The gates of the n TPTs are all common. Therefore, the n T and F T can be regarded as one TPT as a whole. Among the n TPTs, at least two TPTs have different Vths.

前記全体として1つのTPTとみなせるTPTが、どの
ような電気的特性になるかを、簡単のため2つのNチャ
ネルTPTを直列に接続した場合を例にとり次に説明す
る。
For simplicity, the electrical characteristics of the TPT, which can be regarded as one TPT as a whole, will be described below, taking as an example a case in which two N-channel TPTs are connected in series.

第2図はvthが異なる2つのT P T (T 1 
、 T x )が直列に接続されていることを示してい
る。直列に接続されたTPTの両端がソースおよびドレ
インであり、ゲートが共通になつている点は第1図と同
じである。前記2つのTFT 、 T iおよびT2の
電気的特性と、前記2つのTPTを直列に接続したとき
の全体の電気的特性(T)を第3図に示す。第3図にお
いて、T1とT2のVthは異なっている。ドレイン電
流が最小となるゲート電圧は、T、が約−5V、”I’
2は0■である。どちらのTPTにおいても、ドレイン
電流が最小となるゲート電圧より、ゲート電圧がさらに
負の方向に大きくなると、ドレイン電流が増加している
。ゲート電圧が負の方向に大きくなると、チャネル部が
P型となりさらにそのP壁領域の濃度が高くなり、前記
P壁領域とN型領域であるドレインとで形成されるPN
接合を介したリーク電流が増加するからである。このよ
うにゲート電圧が負の方向に大きくなるとき、ドレイン
電極が増加する傾向は、特にTFTを液晶パネルの画素
駆動用トランジスタとして使用するときには望ましくな
い。TPTを介して画素電極に書き込まれたデータ信号
の電圧が、データ保持期間にゲート電圧が負の方向に大
きくなることによって、前記リーク電流のために、低下
し、その結果液晶パネルの表示品質が低下するからであ
る。第3図に示す太い実線(T)は、前記T1とT2の
2つのTPTを直列に接続したときの全体の電気的特性
を示している。オフ電流は2つのTPTの低いほうの値
に律則されるため、ゲート電圧が0〜−1OVの範囲で
殆ど一定であり、而もその値は前記2つの”l’ F 
T夫々の最小オフ電流より低い。一方前記直列に接続し
たTPTのオン電流は、同様に2つのTPTのうち低い
ほうのTPTのオン電流に律則されるが、T、のオン電
流は非常に大きいため、T2のオン電流と殆ど同じ値と
なる。即ち、2つのTPTを直列接続することにより、
オン電流を低下させることなく、オフ電流だけを低減し
かつゲート電圧の広い範囲にわたって低くすることがで
きる。以上の説明は2つのTPTを直列に接続した場合
について行ったが、3つ以上のTPTでも同様に考える
ことができる。
Figure 2 shows two T P T (T 1
, T x ) are connected in series. This is the same as in FIG. 1 in that the TPTs connected in series have a source and a drain at both ends, and have a common gate. FIG. 3 shows the electrical characteristics of the two TFTs, T i and T2, and the overall electrical characteristics (T) when the two TPTs are connected in series. In FIG. 3, the Vths of T1 and T2 are different. The gate voltage at which the drain current is minimum is T, approximately -5V, and "I"
2 is 0■. In both TPTs, when the gate voltage becomes more negative than the gate voltage at which the drain current becomes minimum, the drain current increases. When the gate voltage increases in the negative direction, the channel portion becomes P type and the concentration of the P wall region increases, resulting in a PN formed by the P wall region and the drain, which is an N type region.
This is because leakage current through the junction increases. This tendency for the drain electrode to increase when the gate voltage increases in the negative direction is undesirable, especially when the TFT is used as a pixel driving transistor of a liquid crystal panel. As the gate voltage increases in the negative direction during the data retention period, the voltage of the data signal written to the pixel electrode via the TPT decreases due to the leakage current, and as a result, the display quality of the liquid crystal panel decreases. This is because it decreases. The thick solid line (T) shown in FIG. 3 shows the overall electrical characteristics when the two TPTs T1 and T2 are connected in series. Since the off-state current is determined by the lower value of the two TPTs, it is almost constant in the gate voltage range of 0 to -1OV, and its value is determined by the lower value of the two TPTs.
lower than the minimum off-state current of each T. On the other hand, the on-current of the TPTs connected in series is similarly determined by the on-current of the lower one of the two TPTs, but since the on-current of T is very large, it is almost equal to the on-current of T2. The value will be the same. That is, by connecting two TPTs in series,
Only the off-state current can be reduced without reducing the on-state current, and can be made low over a wide range of gate voltages. Although the above explanation has been given for the case where two TPTs are connected in series, the same idea can be applied to three or more TPTs.

[発明の効果] 本発明によれば、オン電流を低下させることなく、オフ
電流だけを低減し、且つゲート電圧の広い範囲にわたっ
てオフ電流を低くすることができる。
[Effects of the Invention] According to the present invention, only the off-state current can be reduced without reducing the on-state current, and the off-state current can be made low over a wide range of gate voltages.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるn個のT P Tを直列に接続し
た図。第2図は本発明を分かりやすく説明するため2個
のTPTを直列に接続した図。第3図はTPTの電気的
特性を示す図。 S・・・ソース D・・・ドレイン G・・・ゲート 代理人弁理士 上柳雅誉 (他1名) (V>’Is@/−と匂
FIG. 1 is a diagram showing n TPTs connected in series according to the present invention. FIG. 2 is a diagram in which two TPTs are connected in series to explain the present invention in an easy-to-understand manner. FIG. 3 is a diagram showing the electrical characteristics of TPT. S... Source D... Drain G... Gate agent Masataka Kamiyanagi (and 1 other person) (V>'Is@/- and smell

Claims (2)

【特許請求の範囲】[Claims] (1)ソース電極とドレイン電極とゲート電極を備えた
薄膜トランジスタにおいて、閾値電圧が互いに異なる2
つ以上の前記薄膜トランジスタを直列に接続し、前記直
列に接続された薄膜トランジスタの両端の電極をソース
電極およびドレイン電極とし、且つ前記直列に接続され
た薄膜トランジスタの総てのゲート電極を共通にするこ
とを特徴とする半導体装置。
(1) In a thin film transistor equipped with a source electrode, a drain electrode, and a gate electrode, the threshold voltages are different from each other.
Two or more of the thin film transistors are connected in series, electrodes at both ends of the thin film transistors connected in series are used as a source electrode and a drain electrode, and gate electrodes of all the thin film transistors connected in series are common. Characteristic semiconductor devices.
(2)非結晶Siを用いることを特徴とする特許請求の
範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, characterized in that amorphous Si is used.
JP30861388A 1988-12-06 1988-12-06 Semiconductor device Pending JPH02154467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30861388A JPH02154467A (en) 1988-12-06 1988-12-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30861388A JPH02154467A (en) 1988-12-06 1988-12-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02154467A true JPH02154467A (en) 1990-06-13

Family

ID=17983156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30861388A Pending JPH02154467A (en) 1988-12-06 1988-12-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02154467A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506598A (en) * 1992-01-21 1996-04-09 Sharp Kabushiki Kaisha Active matrix substrate and a method for driving the same
JP2003308030A (en) * 2002-02-18 2003-10-31 Sanyo Electric Co Ltd Display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506598A (en) * 1992-01-21 1996-04-09 Sharp Kabushiki Kaisha Active matrix substrate and a method for driving the same
JP2003308030A (en) * 2002-02-18 2003-10-31 Sanyo Electric Co Ltd Display device

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