JPH0350528A - Active matrix substrate for liquid crystal display device - Google Patents

Active matrix substrate for liquid crystal display device

Info

Publication number
JPH0350528A
JPH0350528A JP1186748A JP18674889A JPH0350528A JP H0350528 A JPH0350528 A JP H0350528A JP 1186748 A JP1186748 A JP 1186748A JP 18674889 A JP18674889 A JP 18674889A JP H0350528 A JPH0350528 A JP H0350528A
Authority
JP
Japan
Prior art keywords
channel
liquid crystal
crystal display
display device
active matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1186748A
Other languages
Japanese (ja)
Inventor
Mikio Sakamoto
幹雄 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1186748A priority Critical patent/JPH0350528A/en
Publication of JPH0350528A publication Critical patent/JPH0350528A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • G02F1/136245Active matrix addressed cells having more than one switching element per pixel having complementary transistors

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To nearly eliminate a display flicker due to variance in liquid crystal cell thickness and variance in parasitic capacity by using a transfer gate of CMS constitution as an active element and equalizing the size ratio of an n channel transistor (TR) and a p channel TR. CONSTITUTION:On a c-Si wafer, the CMOS transfer gate is formed as the active element by combining an n channel TR 101 and a p channel TR 102 for each picture element by the CMOS technique of a normal silicon LSI process. The n channel TR 101 and p channel TR 102 of this CMOS transfer gate are equalized in size, i.e. channel length and channel width. When the channel length and channel width are equalized, it is equivalent that both the channel TRs 101 and 102 are equal in source-gate parasitic capacity. Consequently, the display flicker due to variance in liquid crystal cell thickness and variance in parasitic capacity is almost eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクティブ素子を有する液晶表示装置用アク
ティブマトリクス基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix substrate for a liquid crystal display device having active elements.

〔従来の技術〕[Conventional technology]

近年、CRTにかわる小型,薄型,軽量な表示装置とし
て液晶パネルを利用したテレビやプロジェクタの開発が
盛んである.特にスイッチング■・ランジスタやスイッ
チングダイオード等の半4体を用いたアクティブ素子を
各画素毎に設けた液晶パネルで高画質化を狙ったアクテ
ィブマトリクス液晶表示装置の開発が活発である.この
様な液晶表示装置は、液晶を2枚の基板ではさんだi造
で、一方は前記アクティブ素子をマトリクス状に形成し
たアクティブマトリクス基板、他方は少なくとも例えば
ガラス基板上全面に透明電極を形戒してなる対向基板か
ら構成されている。
In recent years, there has been active development of televisions and projectors that use liquid crystal panels as small, thin, and lightweight display devices to replace CRTs. In particular, there is active development of active matrix liquid crystal display devices that aim to achieve high image quality with liquid crystal panels in which each pixel is equipped with an active element using half-quartets such as switching transistors and switching diodes. Such a liquid crystal display device has an i-structure in which a liquid crystal is sandwiched between two substrates, one of which is an active matrix substrate in which the active elements are formed in a matrix, and the other is at least a glass substrate with transparent electrodes formed on the entire surface. It consists of a counter substrate consisting of a

この様な液晶表示装置用アクティブマトリクス基板の模
式的平面図を第2図に示す.この例ではアクティブ素子
としてスイッチングトランジスタ201を用いている。
A schematic plan view of such an active matrix substrate for a liquid crystal display device is shown in Figure 2. In this example, a switching transistor 201 is used as an active element.

スイッチングトランジスタ201としては、単結晶シリ
コン(c−Si)ウェハーに上に形成したMOSトラン
ジスタ、ガラス基板や石英基板等の透明基板上に形成し
た薄膜半導体を利用したアモルファスシリコン(a−S
i)やポリシリコン(p−Si)の薄膜トランジスタ(
TPT)が使用されている,MOS}ランジスタの場合
、基板となるウェハーが不透明なc−Siであるため画
素電極104がアルミ電極等の反射型として、又d−S
iやp−SLのTPTの場合、ガラス基板や石英基板等
の透明基板が使用できるため画素電極104を透明電極
のITOとした透過型として液晶パネルが構成されるの
が一般的である.駆動方法の概略としては、第2図に示
した水平駆動回路105内に外部から入力された映像信
号が1ライン分サンプルホールドされ、この時垂直駆動
回路106から出力されたパルスにより1ライン分のス
イッチングトランジスタ201がオンとなり信号が走査
されたラインに書き込まれる.以下順次走査され1フレ
ームで1画素が書き込まれる.スイッチングトランジス
タ201がオフしている時、すでに書き込まれた信号は
各画素電極104に蓄積されており、次のフレームで書
き換えられる.従って一般的に、水平駆動回路105は
サンプルホールド回路、垂直駆動回路106はシフトレ
ジスタ回路から構成されている.またこの様な回路はア
クティブ素子と同時に、同じ基板上に形成される場合も
あるし、また別途ICチップの形で図示していないが実
装基板上にハイブリッド的に搭載され、ワイヤボンディ
ングやTAB等で接続されている場合等がある. 第3図,第4図を用いて各画素電極104に書き込まれ
る電位を説明する。第3図は、液晶パネルとした時の1
画素の等価回路を、第4図は第3図の各点の電位を示し
たものである。スイッチングトランジスタ201のゲー
ト301にゲート電位VGが加わりハイレベルでオンす
ると、ドレイン302に印加された信号電位がソース(
画素電極〉303に加わり、対向電極304に印加され
た対向電位との電位差の大小により液晶をオンオフさせ
、従って光のオンオフを行う.ゲート電位VGがロウレ
ベルに戻るとソースの画素電位はそのまま保持される.
一般的に液晶に直流電圧を印加すると劣化するため、第
4図に示す様に信号ゼ位は、1フィード毎に対向電位に
対し交流的に加える方法がとられている.次に画素電位
の詳細について説明する.理想的には、ドレイン302
に印加された信号電位がそのまま加わるが、実際にはス
イッチングトランジスタ201のソース〜ゲート寄生容
量Csa305を通したフイードスルーの影響を受ける
.このフイードスルーは、スイッチングトランジスタ2
01がオフした時に働き、いずれの場合も画素電位をマ
イナス側に引っぱる.このため交流信号電位に対し奇数
フレームと偶数フレームではその電位形状を異にする.
この時対向電位は奇数フレームと偶数フレームで液晶に
加わる電位差を同じとする様にフイードスルー分マイナ
ス側に調整する.これを行なわないと30Hzのフリッ
カが発生し画面のちらつきとなる.フィードスルーの量
は、 以下余白 ゲート電位振幅 で表わされる.例えば100μm角の画素を考え、妥当
な値ゲート電位振幅20V,CLc=50fF,Cso
=15fFを挿入するとフィードスルーは約4V以上に
もなる. 〔発明が解決しようとする課題〕 ところで液晶パネルの2枚の基板ではさまれた液晶層厚
は一般的には5〜lOμmと薄いため、場所により厚さ
ムラを発生する.この厚さムラはコントラストの低下を
発生させるが、±10%程度であるならそれ程問題でも
なくまた生産性,歩留り等の点からも上記値を許容して
いる.ところがもう1つこの厚さムラは、液晶容JI 
C LC3 0 6のばらつきとなり従って前述した様
にフイードスルーがばらつく事になる.例えば前記値で
計算すると約IV近くなる.従って第4図に示した様に
フィードスルーのばらつきは、対向電位のばらつきとな
り、どちらか一方に合わせれば片方でフリッカが発生し
てしまう.つまり、液晶層厚のムラがそのまま画面ちら
つきのばらつきとなって画質劣化となってしまう.さら
にスイッチングトランジスタ201のソース〜ゲート寄
生容量05G305もアクティブマトリクス基板内でば
らつく事が予想されさらに画質劣化を促進する.特にこ
のソース〜ゲート奇数容量Cse305のばらつきは基
板内よりパネル間で大きく問題となるため、パネル間で
の対向電位の調整という工数増が必ず必要になってくる
. 本発明の目的は、この様な従来の欠点を取り除いた高性
能な液晶表示装置用アクティブマトリクス基板を提供す
る事にある. 〔課題を解決するための手段〕 上記目的を達成するために、本発明の液晶表示装置用ア
クティブマトリクス基板は、基板上にマトリクス状に形
戒された半導体アクティブ素子、該アクティブ素子に一
対一に接続された画素電極、該画素電極に前記アクティ
ブ素子を通じ信号を制御及び印加するためのマトリクス
配線から少なくとも構成された液晶表示装置用アクティ
ブマトリクス基板において、前記半導体アクティブ素子
がnチャネルとpチャネル両トランジスタがらなるCM
OS構成のトランスファーゲートとなっている. 〔実施例〕 以下、本発明の一実施例について図面を参照して説明す
る. 第1図は、本発明の一実施例を説明するための液晶表示
装置用アクティブマトリクス基板の模式的平面図である
.第1図において例えば図示していないがc−SLウェ
ハー上に通常のシリコンLSIプロセスにおけるCMO
S技術により各画素毎にnチャネルトランジスタ101
とpチャネルトランジスタ102の抱き合わせによるC
MOSトランスファーゲートをアクティブ素子として形
成する.このCMOSプロセスは、nウエル楕造であろ
うとpウェル楕造であろうとダブルウエル構造であろう
と特に限定は無い.このトランスファーゲート製作時に
、同時に各画素毎にCMOSインバータ103も形戒し
ておく。これらのトランジスタに要求される性能は1ラ
イン走査時間つまり動画対応で1フレーム1 6ms 
e cを水平ライン数で割った値で、例えばNTSC対
応525本とすれば1 6 m s e c / 5 
2 5Σ30μsecと遅い.従ってトランジスタの寸
法は、製造プロセスで制限される程度まで極力小さくで
きる. 本実施例の場合、c−Siウェハーを用いたMoSトラ
ンジスタで説明しているため、液晶パネルとしては反射
型の場合として取扱う.従って画素電極104は、水平
駆動回路105からの映像信号供給ラインと同じアルミ
電極で構成する事で液晶表示用アクティブマトリクス基
板が完成する.この時、本発明では前記CMOSトラン
スファーゲートのnチャネルトランジスタ101とpチ
ャネルトランジスタ102の寸法つまりチャネル長やチ
ャネル幅を同一寸法で構成している.チャネル長とチャ
ネル幅を等しくした場合、両チャネルトランジスタの持
つソース〜ゲート寄生容量を等しくしているのと同等と
なる.従ってこのCMOSトランスファーゲートがオフ
する時の画素電極104のフィードスルーは、両ゲート
に加わるゲートパルスが反転しているため打ち消し合っ
てほとんど発生しない.従って従来技術で問題となって
いたフィードスルーのばらつきだけでなくフィードスル
ーそのものも発生しない構或となっている.通常CMO
S}−ランスファーゲートは、nチャネルトランジスタ
101とpチャネルトランジスタ102の性能を合わせ
るためと集積度を上げるためにnチャネルトランジスタ
101の寸法つまりチャネル長とチャネル幅の比をpチ
ャネルトランジスタ102に比べ移動度の大きい分だけ
小さくしている.ところが液晶パネル用アクティブ素子
としては先に述べた様に速度的には早くないため性能と
集積度は、nチャネルトランジスタ101とpチャネル
トランジスタ102の寸法比にはほとんど無関係になっ
ている。このため、本発明の構成でも特に問題とならな
い。
The switching transistor 201 may be a MOS transistor formed on a single crystal silicon (c-Si) wafer, or an amorphous silicon (a-S) transistor using a thin film semiconductor formed on a transparent substrate such as a glass substrate or a quartz substrate.
i) and polysilicon (p-Si) thin film transistors (
In the case of a MOS} transistor that uses TPT, the substrate wafer is opaque c-Si, so the pixel electrode 104 is a reflective type such as an aluminum electrode, or a d-S
In the case of i- or p-SL TPT, a transparent substrate such as a glass substrate or a quartz substrate can be used, so the liquid crystal panel is generally constructed as a transmissive type in which the pixel electrode 104 is a transparent electrode of ITO. An outline of the driving method is that a video signal input from the outside into the horizontal drive circuit 105 shown in FIG. The switching transistor 201 is turned on and a signal is written to the scanned line. After that, it is sequentially scanned and one pixel is written in one frame. When the switching transistor 201 is off, the already written signals are accumulated in each pixel electrode 104 and will be rewritten in the next frame. Therefore, generally, the horizontal drive circuit 105 is composed of a sample and hold circuit, and the vertical drive circuit 106 is composed of a shift register circuit. In addition, such a circuit may be formed on the same substrate at the same time as the active element, or may be mounted in the form of a separate IC chip (not shown) in a hybrid manner on a mounting substrate, using wire bonding, TAB, etc. In some cases, it is connected with The potential written to each pixel electrode 104 will be explained using FIGS. 3 and 4. Figure 3 shows 1 when used as a liquid crystal panel.
FIG. 4 shows an equivalent circuit of a pixel, and FIG. 4 shows the potential at each point in FIG. When the gate potential VG is applied to the gate 301 of the switching transistor 201 and turns on at a high level, the signal potential applied to the drain 302 is applied to the source (
The liquid crystal is turned on and off depending on the magnitude of the potential difference between the pixel electrode 303 and the counter potential applied to the counter electrode 304, thereby turning the light on and off. When the gate potential VG returns to low level, the source pixel potential is maintained as it is.
In general, applying a DC voltage to a liquid crystal causes it to deteriorate, so as shown in Figure 4, a method is used in which the signal zero is applied in an AC manner to the opposing potential for each feed. Next, we will explain the details of the pixel potential. Ideally, the drain 302
Although the signal potential applied to the switching transistor 201 is applied as is, it is actually affected by the feedthrough through the source-to-gate parasitic capacitance Csa 305 of the switching transistor 201. This feedthrough is the switching transistor 2
It works when 01 is off, and in either case it pulls the pixel potential to the negative side. Therefore, the potential shape of the AC signal potential differs between odd and even frames.
At this time, the counter potential is adjusted to the negative side by the feedthrough amount so that the potential difference applied to the liquid crystal is the same in odd and even frames. If this is not done, 30Hz flicker will occur and the screen will flicker. The amount of feedthrough is expressed below by the amplitude of the margin gate potential. For example, considering a 100 μm square pixel, appropriate values gate potential amplitude 20 V, CLc = 50 fF, Cso
If =15fF is inserted, the feedthrough will be about 4V or more. [Problems to be Solved by the Invention] By the way, the thickness of the liquid crystal layer sandwiched between two substrates of a liquid crystal panel is generally as thin as 5 to 10 .mu.m, and therefore the thickness may vary depending on the location. This thickness unevenness causes a decrease in contrast, but if it is about ±10%, it is not that much of a problem, and the above value is acceptable from the viewpoint of productivity, yield, etc. However, there is another reason for this uneven thickness: LCD capacity JI.
This results in variations in CLC3 0 6, and therefore the feedthrough varies as described above. For example, if you calculate with the above value, it will be close to IV. Therefore, as shown in FIG. 4, variations in feedthrough result in variations in opposing potential, and if either one is matched, flicker will occur on the other. In other words, unevenness in the thickness of the liquid crystal layer directly leads to variations in screen flickering, which deteriorates image quality. Furthermore, the source-to-gate parasitic capacitance 05G305 of the switching transistor 201 is expected to vary within the active matrix substrate, further accelerating image quality deterioration. In particular, this variation in the source-to-gate odd capacitance Cse305 is a larger problem between panels than within the board, and therefore an increase in the number of steps required to adjust the opposing potential between panels is inevitably required. An object of the present invention is to provide a high-performance active matrix substrate for a liquid crystal display device that eliminates such conventional drawbacks. [Means for Solving the Problems] In order to achieve the above object, the active matrix substrate for a liquid crystal display device of the present invention includes semiconductor active elements arranged in a matrix on the substrate, and semiconductor active elements arranged one-on-one on the active elements. An active matrix substrate for a liquid crystal display device comprising at least a connected pixel electrode and a matrix wiring for controlling and applying a signal to the pixel electrode through the active element, wherein the semiconductor active element includes both an n-channel transistor and a p-channel transistor. Garanaru CM
It serves as a transfer gate for the OS configuration. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view of an active matrix substrate for a liquid crystal display device for explaining one embodiment of the present invention. For example, although not shown in FIG.
N-channel transistor 101 for each pixel using S technology
C by combining and p-channel transistor 102
A MOS transfer gate is formed as an active element. This CMOS process is not particularly limited, whether it is an n-well elliptical structure, a p-well elliptical structure, or a double-well structure. At the time of manufacturing this transfer gate, the CMOS inverter 103 is also designed for each pixel. The performance required of these transistors is one line scanning time, which is 16ms per frame for video.
The value is e c divided by the number of horizontal lines, for example, if 525 lines are compatible with NTSC, it is 1 6 m s e c / 5
2 5Σ30μsec slow. Therefore, the dimensions of the transistor can be made as small as possible within the limits of the manufacturing process. In the case of this example, since a MoS transistor using a c-Si wafer is explained, the liquid crystal panel will be treated as a reflective type. Therefore, by constructing the pixel electrode 104 with the same aluminum electrode as the video signal supply line from the horizontal drive circuit 105, an active matrix substrate for liquid crystal display is completed. At this time, in the present invention, the dimensions of the n-channel transistor 101 and the p-channel transistor 102 of the CMOS transfer gate, that is, the channel length and channel width, are configured to be the same. When the channel length and channel width are made equal, it is equivalent to making the source-to-gate parasitic capacitance of both channel transistors equal. Therefore, when the CMOS transfer gate is turned off, feedthrough of the pixel electrode 104 hardly occurs because the gate pulses applied to both gates cancel each other out because they are inverted. Therefore, the structure is such that not only the variation in feedthrough, which was a problem with conventional technology, but also the feedthrough itself does not occur. Usually CMO
S}-transfer gate is constructed by comparing the dimensions of the n-channel transistor 101, that is, the ratio of channel length to channel width, with that of the p-channel transistor 102 in order to match the performance of the n-channel transistor 101 and the p-channel transistor 102 and to increase the degree of integration. It is made smaller by the amount of mobility. However, as mentioned above, as an active element for a liquid crystal panel, the speed is not high, so the performance and degree of integration are almost unrelated to the size ratio of the n-channel transistor 101 and the p-channel transistor 102. Therefore, there is no particular problem with the configuration of the present invention.

本実施例では、c−Siウエハーを用いた反射型タイプ
の液晶表示装置用アクティブマドリクス基板で説明した
が、これに限らずガラス基板や石英基板等の透明基板を
用いたa−Siやp−SiTPTアクティブ素子の場合
であってもその効果は同じてある. また本実施例では各画素毎にインバータ103を設ける
構成で説明しているが、垂直駆動回路106が各ライン
毎へこの出力端子を持っていれば、このインバータ10
3は不要である.但し、この場合水平ラインの数がnチ
ャネルトランジスタ101制御用とpチャネルトランジ
スタ102制御用と2倍になる。
In this example, an active matrix substrate for a reflective type liquid crystal display device using a c-Si wafer was explained, but the invention is not limited to this, and it is not limited to this, but it is also possible to use an a-Si or p - The effect is the same even in the case of SiTPT active elements. Further, in this embodiment, the inverter 103 is provided for each pixel, but if the vertical drive circuit 106 has this output terminal for each line, the inverter 103
3 is not necessary. However, in this case, the number of horizontal lines is doubled for controlling the n-channel transistor 101 and for controlling the p-channel transistor 102.

なお、水平駆動回路,垂直駆動回路は従来と変らないの
で詳しい説明は省略する。
Note that the horizontal drive circuit and vertical drive circuit are the same as before, so detailed explanations will be omitted.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明の液晶表示装置用アクティブ
マトリクス基板によれば、アクティブ素子にCMS楕戒
のトランスファーゲートを用いしかもnチャネルトラン
ジスタ101とpチャネルトランジスタ102の寸法比
を同じにするという構成をとるため、液晶セル厚のばら
つきや寄生容量のばらつきによる画面ちらつきをほとん
ど無くす事ができ良好な表示画面を得る事が可能となる
.またフィードスルーそのものを発生しないためパネル
毎にフリッカを発生しない様に対向電極の電位を調整す
るという工数負担はなくなりコスト低減にもつながる.
As explained above, according to the active matrix substrate for a liquid crystal display device of the present invention, a CMS elliptical transfer gate is used as an active element, and the size ratio of the n-channel transistor 101 and the p-channel transistor 102 is made the same. Since the LCD screen has a high temperature, it is possible to almost eliminate screen flickering caused by variations in liquid crystal cell thickness and parasitic capacitance, making it possible to obtain a good display screen. In addition, since feedthrough itself does not occur, there is no need to adjust the potential of the opposing electrode on each panel to prevent flickering, leading to cost reductions.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を説明するための液晶表示
装置用アクティブマトリクス基板の模式的平面図、第.
2図は従来例を説明するための液晶表示装置用アクティ
ブマトリクス基板の模式的平面図、第3図は従来例を説
明するための1画素の等価回路、第4図は第3図の各点
の模式的電位波形図である.
FIG. 1 is a schematic plan view of an active matrix substrate for a liquid crystal display device for explaining one embodiment of the present invention.
Figure 2 is a schematic plan view of an active matrix substrate for a liquid crystal display device to explain a conventional example, Figure 3 is an equivalent circuit of one pixel to explain a conventional example, and Figure 4 shows each point in Figure 3. This is a schematic potential waveform diagram.

Claims (1)

【特許請求の範囲】[Claims] 基板上にマトリクス状に形成された半導体アクティブ素
子、該アクティブ素子に一対一に接続された画素電極、
該画素電極に前記アクティブ素子を通じ信号を制御及び
印加するためのマトリクス配線から少なくとも構成され
た液晶表示装置用アクティブマトリクス基板において、
前記半導体アクティブ素子がnチャネルとpチャネル両
トランジスタからなるCMOS構成のトランスファーゲ
ートである事を特徴とする液晶表示装置用アクティブマ
トリクス基板。
semiconductor active elements formed in a matrix on a substrate; pixel electrodes connected one-to-one to the active elements;
An active matrix substrate for a liquid crystal display device comprising at least matrix wiring for controlling and applying signals to the pixel electrode through the active element,
1. An active matrix substrate for a liquid crystal display device, wherein the semiconductor active element is a CMOS-structured transfer gate comprising both n-channel and p-channel transistors.
JP1186748A 1989-07-18 1989-07-18 Active matrix substrate for liquid crystal display device Pending JPH0350528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1186748A JPH0350528A (en) 1989-07-18 1989-07-18 Active matrix substrate for liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1186748A JPH0350528A (en) 1989-07-18 1989-07-18 Active matrix substrate for liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0350528A true JPH0350528A (en) 1991-03-05

Family

ID=16193956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1186748A Pending JPH0350528A (en) 1989-07-18 1989-07-18 Active matrix substrate for liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH0350528A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414091A (en) * 1990-05-07 1992-01-20 Fujitsu Ltd Active matrix type display device and its control method
JPH0643434A (en) * 1991-05-20 1994-02-18 Semiconductor Energy Lab Co Ltd Electro-optical device and its image display method
JPH0682759A (en) * 1991-06-14 1994-03-25 Semiconductor Energy Lab Co Ltd Image display method for electro-optical device
JPH06123873A (en) * 1991-05-31 1994-05-06 Semiconductor Energy Lab Co Ltd Image display method of electro-optic device
US8355015B2 (en) 2004-05-21 2013-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device and electronic device including a diode electrically connected to a signal line

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414091A (en) * 1990-05-07 1992-01-20 Fujitsu Ltd Active matrix type display device and its control method
JPH0643434A (en) * 1991-05-20 1994-02-18 Semiconductor Energy Lab Co Ltd Electro-optical device and its image display method
JP2754290B2 (en) * 1991-05-20 1998-05-20 株式会社半導体エネルギー研究所 Electro-optical device and driving method thereof
JPH06123873A (en) * 1991-05-31 1994-05-06 Semiconductor Energy Lab Co Ltd Image display method of electro-optic device
JPH0682759A (en) * 1991-06-14 1994-03-25 Semiconductor Energy Lab Co Ltd Image display method for electro-optical device
US8355015B2 (en) 2004-05-21 2013-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device and electronic device including a diode electrically connected to a signal line
US8917265B2 (en) 2004-05-21 2014-12-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device and electronic device including a current source and a diode electrically connected at an output of the current source
US9536937B2 (en) 2004-05-21 2017-01-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a rectifying element connected to a pixel of a display device
US10115350B2 (en) 2004-05-21 2018-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having rectifying elements connected to a pixel of a display device

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