JPH0414091A - Active matrix type display device and its control method - Google Patents

Abstract

PURPOSE:To prevent a DC component from being caused in an AC voltage impressed on a display cell by the parasitic capacity of a switching element by connecting plural switching elements having different acting polarities to respective picture element electrodes and independently impressing a control voltage for every kind. CONSTITUTION:Shift voltages DELTAVlcN and DELTAVlcP after writing a signal voltage in a liquid crystal cell 17 through N channel type and P channel type TFTs (switching elements) 14 and 15 are expressed by formulas I and II. Provided that Clc means the capacity of the liquid crystal cell, Cgsn and Cgsp mean the capacity between the gate and the source of the N type and p type TFTs 14 and 15 including the parasitic capacity between a scanning bus line 11 and the picture element electrode 21, and DELTAVgn and DELTAVgp mean the modulation width of a gate voltage after addressing the N type and p type TFTs. By making the absolute values of DELTAVlcn and DELTAVlcP obtained from the formulas I and II equal, they are mutually negated to make DELTAVlc zero, so that the Dc component in the AC voltage impressed on the liquid crystal cell is prevented from occurring.

Description

[Detailed Description of the Invention] (Summary) This invention relates to an active matrix display device and its control method, which prevents the generation of shift voltage caused by the parasitic capacitance of switching elements such as TPT, and reduces the amount of alternating current voltage applied to display cells. The purpose of the present invention is to provide an active matrix type display device that can prevent the generation of direct current components and a control method thereof. An active matrix display device comprising a plurality of display cells formed by pixel electrodes and electro-optic elements, and a switching element for controlling each of the display cells, wherein the switching element is connected to a control electrode. There are two types of switching elements: a switching element that becomes conductive when a positive voltage is applied, and a switching element that becomes conductive when a negative voltage is applied to the control electrode. A plurality of switching elements including two types of switching elements are connected, and a control voltage can be applied independently to each type of the plurality of switching elements connected to each of the pixel electrodes.

[Industrial application field]

The present invention relates to an active matrix display device and a control method thereof.

Active matrix display devices, along with simple matrix display devices, are used as thin display devices for information terminals, and liquid crystals are often used as the display medium.

Active matrix liquid crystal display devices (hereinafter sometimes referred to as "active liquid crystal panels") can drive a large number of pixels independently. Even though
Unlike the simple matrix type, there are no problems such as a reduction in driving duty ratio or contrast, or a reduction in viewing angle.

Therefore, in recent years, display devices that require high resolution, such as portable televisions, have become increasingly popular, and further improvements in display quality are expected.

[Conventional technology]

FIG. 9 is an equivalent circuit diagram of a conventional general active type liquid crystal panel 50.

The active liquid crystal panel 50 is provided with a liquid crystal cell 17 and a TPT (thin film transistor) 51 for driving the liquid crystal cell 17 for each pixel arranged in a matrix, and a gate electrode 61 of each TFT 51 is connected to a scanning electrode. The drain electrode 62 is connected to the bus line 11, the drain electrode 62 is connected to the data bus line 13, and the source electrode 63 is connected to the pixel electrode 21 of the liquid crystal cell 17.
are connected to each other.

The gate electrode 61 of the TPT 51 has a pulse width of 30 to 6
The address signal Sll, which is a pulse signal of approximately 0 μs, is
The data signal S12 is applied at a constant cycle through the scan bus line 11, and at that timing, the data signal S12 is applied to the pixel electrode 21 through the data bus line 13, thereby writing display data into the liquid crystal cell 17.

While the address signal Sll is off, the liquid crystal cell 17 is disconnected from the data bus line 13, but the data signal 51 written while the address signal Sll is on
2 is the electrostatic capacitance of the liquid crystal cell 17 (liquid crystal cell capacitance) Cj! c, the display state is maintained until the next address signal Sll is input.

However, in the TPT 51, since a parasitic capacitance (gate-source capacitance) Cgs exists between the gate electrode 61 and the scan canvas line 11 and the source electrode 63, the voltage change at the fall of the address signal Sll is caused by this parasitic capacitance. Capacity C
appears at the pixel electrode 21 of the liquid crystal cell 17 through gs, thereby causing the voltage of the pixel electrode 21 (liquid crystal cell voltage) Vj! c.
shifts in the negative direction.

The amount of shift of the liquid crystal cell voltage VIlc, that is, the shift voltage ΔVlc is expressed as ΔVfc=(CgsXΔve)+(C/!c+Cgs)−(1).

Here, Δ■. is the amplitude (voltage) of the address signal S11.

By this shift voltage ΔVffic, the data signal S1
2, even when using an AC voltage whose polarity is symmetrical in positive and negative for each frame, the effective voltage applied to the liquid crystal cell 17 is not symmetrical in positive and negative, and a DC component is generated.

Such a direct current component degrades display quality by causing flicker and afterimage phenomena of still images, and also shortens the life of the active liquid crystal panel 50.

As a countermeasure for this, for example, by applying a bias voltage to the counter electrode (common electrode) 22 of the liquid crystal cell 17 and correcting it so that the effective voltage of the liquid crystal cell 17 becomes symmetrical in positive and negative frames, the DC component is reduced. Is possible.

As another countermeasure, two complementary TPTs are used for one pixel electrode, and an address signal of opposite polarity is alternately applied every frame to each gate electrode of these TPTs, thereby reducing the voltage applied to the liquid crystal cell. An active type liquid crystal panel has been proposed (Japanese Patent Application Laid-open No. 144297/1983) in which the voltages applied are symmetrical in positive and negative directions as a whole.

[Problem to be solved by the invention]

However, in the former case, since the liquid crystal cell capacitance Cfc has voltage dependence due to the dielectric anisotropy of the liquid crystal cell 17, the shift voltage Δ■E depends on the display state of the liquid crystal cell 17.
There is a problem in that C varies and the direct current component cannot be removed to a certain extent just by applying a bias voltage to the opposing electric bridge 22.

In the latter case, an address signal of opposite polarity is applied to the gate electrode every frame, and the overall shift voltage Δ
■1C is canceled by positive and negative, making it almost symmetrical, but if you look at each frame, the shift voltage Δ■i! , C still occurs.

Therefore, this direct current component causes the image density of each frame to change, resulting in a problem of lowering the fidelity of image reproduction.

Furthermore, when the data signal S12 changes every frame, as in the case of a moving image, for example, there is a problem that the DC component cannot be completely removed as a whole.

In view of the above-mentioned problems, the present invention prevents the generation of shift voltage caused by the parasitic capacitance of switching elements such as TFTs, and
An active matrix display device that can prevent the generation of DC components in the AC voltage applied to display cells! The purpose of this invention is to provide a method for controlling the same.

[Means to solve the problem]

In order to solve the above-mentioned problem, the display device according to the invention of claim 1 applies a voltage in the positive direction to the control electrode 3I as the switching element 14, 15, as shown in FIGS. 1 to 8. Switching element 1 becomes conductive due to
4 and a switching element 15 that becomes conductive by applying a negative voltage to the control electrode 31. Each pixel electrode 21 has a plurality of switching elements including the above two types of switching elements. The plurality of switching elements 14.15 connected to each pixel electrode 21 are configured such that a control voltage Sl can be applied independently to each type of switching element 14.15.

In the display device according to the invention of claim 2, the two types of switching elements 1415 connected to each pixel electrode 21 are scanned line SN in which each control electrode 31 is independent from each other.
and SP, Sn and 5nl-ISn-1 and Sn are connected.

In the display device according to the third aspect of the invention, switching elements 14 and 15 of different types connected to one scan canvas line 11 and two pixels 1t8i21 arranged with the scan canvas line 11 in between are controlled. 'a electrode 3
1 is connected.

In the control method according to the invention of claim 4, each of the pixel electrodes 21
Pulse signals +VGN, with opposite polarities to each control electrode 31 of two types of switching elements 14 and 15 connected to
Apply VGP at the same time to make them conductive at the same time.

In the control method according to the invention of claim 5, two consecutive pulse signal elements VG N + -VG P having mutually opposite polarities are applied to the scan canvas line 11, and two types of pulse signal elements VG N + -VG P connected to each of the pixel electrodes 21 are applied. Switching element 14.15
conduct at the same time.

In the control method according to the invention of claim 6, one display cell 17
An N-channel switching element 14 and a P-channel switching element 15 are connected to the switching elements 14 and 15, and pulse signals of opposite polarity to each other are simultaneously applied to the display cell. 17
are simultaneously driven by two switching elements 14 and 15.

[Function] Next, regarding the case where TPT is used as the switching element 14.15 and liquid crystal is used as the electro-optical element, especially the first
The operation will be explained focusing on the state of shift voltage ΔVj2c with reference to the figure.

Shift voltage ΔV after writing the signal voltage (display data) to the liquid crystal cell 17 through the N-channel TFT 4
j! c, is ΔVI! based on the above equation (1). cN
= (-CgsnXΔVGN)+ (C1c+Cg
s n + Cg s p) (2) Here, Cff1c is the liquid crystal cell capacitance, and Cgsn is the gate/source of the N-channel TFT 14 including the parasitic capacitance between the scan canvas line 11 and the pixel electrode 21. capacity,
Cgsp is also the gate of P-channel type TFT15.
The source-to-source capacitance ΔVGN is the width of gate voltage change after addressing of the N-channel TFT 14.

Similarly, the shift voltage ΔVf after writing the signal voltage to the liquid crystal cell 17 through the P-channel TFT 15 is
c, ΔVj! c, -(+Cg s pXΔva P )
÷(Cj! c+Cg s n+Cg s p)...
...(3) Here, Δ■. , is the width of gate voltage change after addressing of the P-channel TFT 15.

ΔVjl! obtained from these equations (2) and (3)! By making the absolute values of c and Δ■Itcp equal, they cancel each other out and the shift voltage Δ■lc becomes zero, resulting in the signal voltage value written by the data signal. is held as is until the next address signal.

This prevents the generation of a DC component in the AC voltage applied to the liquid crystal cell.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is an equivalent circuit diagram of the active type liquid crystal panel 1 according to the present invention.

The active liquid crystal panel l has a plurality of scan canvas lines 11, 11, .
. . , and data bus lines 1313 are formed, and in each pixel area partitioned in a matrix by these scan canvas lines 11 and data bus lines 13,
A pixel electrode 21 is provided respectively.

Further, a transparent counter electrode 22 facing all the pixel electrodes 21 is commonly provided on the other glass substrate (not shown).

Liquid crystal is filled between these two glass substrates, and a liquid crystal cell 17 is formed for each pixel electrode 21.

In order to control each liquid crystal cell 17, an N-channel TF
Two types of TP: T14 and P-channel type TFT15
T14.15 is provided for each liquid crystal cell 17, respectively.

These TPT14.15 have a semiconductor layer made of amorphous silicon or polycrystalline silicon, and their source/drain electrodes are
In the case of a P-type, a P-type semiconductor doped with an impurity such as poron can be used, and in the case of an N-type, an N-type semiconductor doped with phosphorus, arsenic, etc. can be used.

In addition, when forming these, these two layers are doped by separately doping boron or arsenic into the semiconductor layer of the source/drain region using methods such as ion implantation or diffusion using a photosensitive material, oxide film, nitride film, etc. as a mask. Type of T
PT14.15 can be formed.

In the scan canvas line 11, two mutually independent scan canvas lines 5NSP are provided for one line, and the gate electrode 31 of the N-channel type TFT 14 is connected to the scan canvas line SN, and the gate electrode 31 of the N-channel type TFT 14 is connected to the scan canvas line SN. T
The gate electrodes 31 of the FTs 15 are respectively connected to the scan canvas lines SP.

Further, the drain bridge 32 of each TFT 14 15 is connected to the data bus line 13, and the source electrode 33 is connected to the pixel electrode 21, respectively.

In the following description and drawings, the scan canvas line 11
, data bus line 13, TFT 1415, and liquid crystal cell 17 are respectively referred to as scan line SN,
SP, data bus line D, TFT-N, TFT-P,
Alternatively, it may be indicated by a different symbol, such as liquid crystal cell E, or may be indicated by only that symbol. In that case, depending on the position of each element on the matrix,
For each code, rn, m'', 'n+1. It may be displayed with a code indicating the coordinates, such as "m+1".

FIG. 4 is a waveform diagram of address signals SIN and SIP that control the active type liquid crystal panel 1 of FIG. 2.

Address signals SIN and SIP are applied to the scan bus lines SN and SP, respectively, and a data signal S2 is applied to the data bus line D.

Note that the address signals SIN and SIP may be collectively referred to as the address signal S1.

Address signals SIN and SIP are mutually synchronized pulse signals of opposite polarity, and their magnitudes (voltage 1) are 1 and 2, respectively. , is. In other words, the address signal SIN
is a pulse signal of voltage +VGH, and address signal SIP is voltage -■. This is a pulse signal.

An address signal S1 delayed by the pulse width of the address signal Sl is sequentially applied to the scan canvas line 11 of each line, and thereby all the scan canvas lines 11 are scanned.

That is, for example, scan canvas line SNn.

Assuming that address signals 5INn and 5IPn applied to SPn are output between time t0 and time t1, the next scan line SNn11. The address signals 5INn+1 and 5IPn+1 applied to SPn+1 are output from time t1 to time t2, and thereafter are sequentially output after being delayed by a certain period of time.

The data signal S2 has a magnitude of V and is applied at almost the same timing as the address signal Sl, but the polarity is not limited to this, as the polarity is reversed every frame. However, in this embodiment, the data signal S2 has a wider pulse width than the address signal S1.

Now, TFT-N and TFT-P in each pixel are turned on simultaneously by the address signals SLN and SIP, and thereby the data signal S2 is transmitted to both TFT-N and TFT-P.
It is applied to the liquid crystal cell through P and written.

At this time, the gate-source capacitances Cgsn and Cgsp of TFT-N and TFT-P, and the address signal SIN
, between the voltage of SIP + VGNI VGP, G g s n XVes=Cg sp XVGP
--In order to hold the relationship (4), the voltage +VGN, -
The magnitudes of V and p are set.

Therefore, ΔV2c8 and ΔVj! explained in the section on effects above. The absolute values of cr become equal, and they cancel each other out, so that the shift voltage ΔVfc becomes zero. Therefore, above the signal voltage written by the data signal S2.

is held as is until the next address signal S1.

This prevents generation of a DC component in the AC voltage applied to the liquid crystal cell 17.

FIG. 3 is an equivalent circuit diagram showing an active type liquid crystal panel 2 according to another embodiment of the present invention.

This active type liquid crystal panel 2 has a data bus line (
This is a so-called facing matrix type active liquid crystal panel in which a panel (not shown) is provided on a glass substrate separate from the scan canvas line 11 and arranged to face the pixel electrode 21.

That is, in order to control each liquid crystal cell 17 constituting a pixel, an N-channel type TFT 14 and a P-channel type TF
Two types of TPT1415 are provided, and each gate electrode 31 is connected to the scan canvas line SN SP.
The source electrodes 33 are connected to the liquid crystal cells 17, respectively, as in the active type liquid crystal panel 1 described above, but the drain electrodes 32 of each TFT 14, 15 are connected in parallel to the scan canvas lines SN, SP. The difference is that it is connected to the provided ground path line 19 and is supplied with a constant reference potential (ground potential in this embodiment).

In controlling this active type liquid crystal panel 2, the address signal 5INSIP shown in FIG. 4 mentioned above is used.

That is, the address signals SIN and SIP are applied to two types of TPT-N and TPT-P connected to one pixel electrode 21.
These TFT-N and TFT-P are turned on at the same time by simultaneously applying voltage to the gate electrodes 31 of the TFT-N and TFT-P.

Therefore, by setting the magnitude of the voltage +V GMT V GP so that the relationship in equation (4) above is established, the shift voltage ΔVlC becomes zero, and the DC voltage in the AC voltage applied to the liquid crystal cell 17 becomes zero. Generation of components is prevented.

FIG. 5 is an equivalent circuit diagram showing an active type liquid crystal panel 3 according to another embodiment of the present invention.

In this active type liquid crystal panel 3, only one scan canvas line 11 is provided for each line, and this one scan canvas line 11 has two scan canvas lines arranged on both sides of the scan canvas line 11. Pixel electrode 21
．． TFT-N, TFT-N and TFT-N, which are different in type from each other, are connected to 21.
Gate electrodes 31.31 of FT-P are connected.

In other words, the gate electrode 31 of one type of TPT-N (or TPT-P) connected to one pixel electrode 21 and the gate electrode 31 of one type of TPT-N (or TPT-P) connected to the corresponding Wi element electrode 21 along the direction of the data bus line 13 Gate electrode 3 of the other type of TPT-P (or TPT-N) connected to the other pixel electrode 21
1 are connected to the same scan canvas line 11.

FIG. 6 is a waveform diagram of the address signal S1 that controls the active liquid crystal panel 3 of FIG.

Scan canvas line 5n-1, Sn, Sr+4-1...
・are respectively address signals 5in-1, Sln, S
1n+1... is applied.

Each address signal S1 consists of two consecutive pulse signals having mutually opposite polarities and equal pulse widths, and the respective magnitudes are VCS and VGP.

In addition, each address signal 5in-1, S1n, S1n+1
... are sequentially delayed by one pulse width, and the positive pulse signal is delayed by the negative pulse signal of the address signal applied one line before, and the negative pulse signal is delayed by one pulse width. They are each synchronized with the positive polarity pulse signal of the address signal applied after the line.

That is, for example, depending on the address signal Sin applied to the scan canvas line Sn, from time t0 to time 1. TFT-Nn-1,m is turned on during time 1. TPT-Pnm is turned on between time t2 and time t2. Note that the TPT-Nn1 that has been turned on once is connected to the gate electrode 3 at time t1.
1 is turned off by applying a negative pulse signal to it.

Therefore, two types of TFs connected to each pixel electrode 21
Since TN and TFT-P are turned on at the same time, the above (
4) Voltage +vcs, V so that the relationship in formula holds true.
By setting the magnitude of GP, the shift voltage Δ
(2) 1C becomes zero, and generation of a DC component in the AC voltage applied to the liquid crystal cell 17 is prevented.

Further, according to this active type liquid crystal panel 3, the number of scan canvas lines 11 can be reduced by half, so the area occupied by the scan canvas lines 11 and the electrodes for connecting them is reduced, and the control lines It is possible to simplify the substrate structure, control circuit, etc. by reducing the number of substrates.

FIG. 7 is an equivalent circuit diagram showing an active type liquid crystal panel 4 according to another embodiment of the present invention.

The second active type liquid crystal panel 4 corresponds to the facing matrix type active type liquid crystal panel 2 shown in FIG. 3, and is configured to reduce the number of scan canvas lines 11.

That is, in order to control each liquid crystal cell 17 constituting a pixel, an N-channel type TFT 14 and a P-channel type TF
Two types of TFTs 1415 are provided, each gate electrode 31 is provided on each of the two scan canvas lines 11 provided one line apart, the drain electrode 32 is provided on the ground pass line 19, and the source electrode 33 is provided on the liquid crystal cell. 17, respectively.

For example, scan canvas line 5n-1 includes TPT-P
The gate electrode 31 of n-1,m and TFT-Nn,m is
The gate electrodes 31 of the TPT-Nn-1,m and the TFT-Pn,m are respectively connected to the scan canvas line Sn.

FIG. 8 is a waveform diagram of the address signal S1 that controls the active type liquid crystal panel 4 of FIG.

The scan canvas lines 5n-1, 3n, Sn+1, . . . have address signals 5in-1, 5tn, S1n, respectively.
+1... is applied.

Each address signal S1 consists of two consecutive pulse signals having mutually opposite polarities and equal pulse widths.

Address signals 5in-1 and Sln, S1n+1 and 51n+2 applied to a pair of scan canvas lines 11.
. . . are synchronized with pulses of opposite polarity. For example, the address signal 5in-1 is a pulse signal of voltage -VGP and voltage V. The address signal S1n consists of a voltage V synchronized with these pulse signals.
It consists of a pulse signal of GH and a pulse signal of voltage -VGP. Further, each pair of address signals S1 is sequentially delayed by two pulse widths.

That is, for example, the voltage ■ of the address signal 5in-1 applied to the scan canvas line 5n-1. , between time t0 and time t, TFT-Nn,
m is turned on, and at the same time, TPT-Pn,m is turned on by a pulse signal of the voltage -VGP of the address signal Sin applied to the scan canvas line Sn.

Therefore, two types of TFs connected to each pixel electrode 21
Since TN and TFT-P are turned on at the same time, the above (
4) The voltage element vG N + −
By setting the magnitude of vG F, the shift voltage ΔV1c becomes zero, and generation of a DC component in the AC voltage applied to the liquid crystal cell 17 is prevented.

Further, according to this active type liquid crystal panel 4, the number of scan canvas lines 11 can be reduced compared to the active type liquid crystal panel 2 shown in FIG.

In addition, any of the active type liquid crystal panels 1 to 4 described above
Also, one liquid crystal cell 17 is connected to two TPTs 14.
Since it has a redundant configuration driven by 15, the TP
Even if one of the TFTs 4 and 15 becomes defective and becomes open, or even if it becomes short-circuited and is cut by laser, the liquid crystal cell 17 can be driven by the other TFTI 4, 15. The display function can be maintained.

In the above embodiment, two TPTs 14.15 were used for each liquid crystal cell 17, but three or more may be used. P using a semiconductor substrate instead of TPT14.15
It may also be a channel type or N channel type MOS transistor. Alternatively, control may be performed by switching the connections between the P-channel type and the N-channel type, and using the address signal S1 with the polarity of the pulse signal switched.

In the embodiments described above, a liquid crystal was used as the electro-optical element, but various other elements such as an electroluminescent element and an electrochromic element can be used. The structures, shapes, materials, etc. of the active liquid crystal panels 1 to 4 and their respective parts may be various other than those described above.

〔Effect of the invention〕

According to the present invention, it is possible to prevent the generation of a shift voltage due to the parasitic capacitance of a switching element such as a TPT, and to prevent the generation of a DC component in an AC voltage applied to a display cell.

Therefore, it is possible to provide an active matrix display device that has a long life and excellent display characteristics.

Further, since there is redundancy in the switching elements, even if one of the switching elements becomes defective, the display cell can be driven by the other switching element and the display function can be maintained.

Furthermore, according to the third aspect of the present invention, the number of scan canvas lines is reduced, and the structure of the board, control circuit, etc. can be simplified.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram for explaining the present invention in detail, Fig. 2 is an equivalent circuit diagram showing an active type liquid crystal panel according to the present invention, and Fig. 3 is an active type liquid crystal panel of another embodiment according to the present invention. An equivalent circuit diagram showing a liquid crystal panel, FIG. 4 is a waveform diagram of an address signal that controls the active type liquid crystal panel of FIGS. 2 and 3, and FIG. 5 is an active type liquid crystal panel of another embodiment according to the present invention. 6 is a waveform diagram of an address signal that controls the active type liquid crystal panel of FIG. 5. FIG. 7 is an equivalent circuit diagram showing an active type liquid crystal panel of another embodiment according to the present invention. FIG. 8 is a waveform diagram of an address signal that controls the active type liquid crystal panel of FIG. 7, and FIG. 9 is an equivalent circuit diagram of a conventional general active type liquid crystal panel. 15 is a TPT (switching element), 17 is a liquid crystal cell (display cell), 21 is a pixel electrode, 31 is a gate electrode (control ii t! ii), SL is an address signal (control voltage), SN SP 5n-I Sn, Sn+1 is a scan canvas line, and GN+ and GF are voltages (pulse signals). In the figure, 1 to 4 are active type liquid crystal panels (active matrix type display device), 11 is a scan canvas line, 13 is a data bus line, 14 is TPT (switching element), l is an active type liquid crystal panel according to the present invention Equivalent circuit diagram showing a liquid crystal panel Fig. 3 An equivalent circuit diagram showing an active type liquid crystal panel of another embodiment according to the present invention Fig. 3 Active type liquid crystal panel Fig. t-+ to t+ b h Fig. 7 Active type Waveform diagram of the address signal that controls the liquid crystal panel Near active type liquid crystal display diagram

Claims (6)

[Claims] (1) A plurality of scan canvas lines (11) and data bus lines (13) extending in directions orthogonal to each other, and a plurality of display cells (formed by pixel electrodes (21) and electro-optical elements arranged in a matrix) 17); and switching elements (14) and (15) for controlling each of the display cells (17).
(4), wherein the switching elements (14) and (15) include control electrodes (
A switching element (14) that becomes conductive by applying a positive voltage to 31), and a control electrode (31)
and a switching element (15) that becomes conductive when a negative voltage is applied to the pixel electrode (21). )(15)
The plurality of switching elements (14) and (15) connected to each pixel electrode (21) are configured such that a control voltage (S1) can be applied independently for each type. Features an active matrix type display device. (2) A plurality of scan canvas lines (11) and a data bus line (13) extending in directions orthogonal to each other, and a plurality of display cells (formed by pixel electrodes (21) and electro-optical elements arranged in a matrix) 17); and switching elements (14) and (15) for controlling each of the display cells (17).
(4) Each of the pixel electrodes includes a switching element (14) that becomes conductive by applying a positive voltage to the control electrode (31), and a negative voltage to the control electrode (31). A switching element (15
) are connected to each control electrode (31), and the two types of switching elements (14) (15) connected to each pixel electrode (21) are connected to each control electrode (31). are mutually independent scan canvas lines (SN) (SP), (
An active matrix type display device characterized in that the display device is connected to (Sn) (Sn+1), (Sn-1) (Sn). (3) Switching elements (14) (15) of different types connected to one scan canvas line (11) and two pixel electrodes (21) arranged across the scan canvas line (11) 4. The active matrix display device according to claim 2, wherein the control electrodes (31) are connected to each other. (4) Each control electrode (31) of two types of switching elements (14) (15) connected to each pixel electrode (21)
, pulse signals (+V_G_N) (-V
4. The method for controlling an active matrix display device according to claim 1, further comprising simultaneously applying _G_P) and making the display conductive at the same time. (5) Two consecutive pulse signals (+V_G_N) (-V
_G_P) to simultaneously make two types of switching elements (14) and (15) conductive connected to each of the pixel electrodes (21). . (6) Connect an N-channel type switching element (14) and a P-channel type switching element (15) to one display cell (17), and connect these switching elements (14) and (15) with opposite polarities. Pulse signals (+V_G_N) (-V_G_P) are applied simultaneously, and the display cell (17) is connected to the two switching elements (14).
) (15).