JPH0815728A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve the display characteristics of an active matrix type liquid crystal display device for which TFTs are used by decreasing the DC component voltages occurring in the parasitic capacitances between gates and sources. CONSTITUTION:This liquid crystal display device is composed of a structure to increase voltage dropping rates by setting the width of the source electrodes of the TFTs smaller than the width of the drain electrodes thereof to decrease the parasitic capacitors between the gates and the sources and increasing the impression voltages. As a result, the voltage dropping rate DELTAVs4 at the time of impressing the large negative source voltage Vs4 increases and, therefore, the DC component voltages as a whole are decreased by setting the canon electrode voltage Vcom in compliance with the voltage dropping rates DELTAVs2, DELTAVs3 at the time of impressing the small source voltages Vs2, Vs3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a liquid crystal display device in which the influence of a DC component voltage based on the dielectric anisotropy of liquid crystal is reduced to improve the display quality.

[0002]

2. Description of the Related Art Liquid crystal display devices have advantages such as thinness, light weight, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a thin film transistor (TFT) as a switching element can perform static driving with a duty ratio of 100% in multiplex in principle, and has a large screen and a high-definition moving image display. Is used for.

The active matrix type liquid crystal display device is
A substrate (TFF substrate) having display electrodes arranged in a matrix and TFTs connected to each display electrode and a substrate having a common electrode (counter substrate) are bonded together with a liquid crystal sandwiched therebetween. It The TFT is a switching element that selects a data signal input to the display electrode, and is a FET including a gate electrode, a drain electrode, a source electrode, and a non-single crystal semiconductor layer. Each electrode is connected to a gate line, a drain line and a display electrode. The non-single crystal semiconductor layer is made of amorphous silicon (aS
i) or polycrystalline silicon (p-Si), which functions as a channel layer. The gate line group is line-sequentially scan-selected to turn on all the TFTs on one scanning line, and during this ON period, a data signal is input to each display electrode via each drain line. A voltage is set in the common electrode in synchronization with the scanning signal, and a liquid crystal capacitance serving as a pixel is formed between the display electrodes facing each other and the voltage is held. This holding voltage drives the liquid crystal in the gap, and maintains the driving state of the liquid crystal for one scanning period until it is rewritten by positive / negative inversion in the next field. In the driving state of the liquid crystal, the holding characteristic is improved by disposing the auxiliary capacitance in parallel with the liquid crystal capacitance. As the auxiliary capacitance, C _S On formed by arranging the auxiliary capacitance electrode so as to overlap with the display electrode.
Common method and, there is a C _S On Gate scheme of superimposing extends to the display electrodes a portion of the gate line. In this way, the light transmittance is adjusted for each pixel, and each transmitted light is visually recognized as a desired display image by macroscopic synthesis.

FIG. 8 is an equivalent circuit diagram of such a liquid crystal display device. The TFTs (S) are formed at the intersections where the gate lines (G1 to Gm) and the drain lines (D1 to Dn) cross each other.
E) is formed, and its source is one electrode of the liquid crystal capacitance (Clc) and the auxiliary capacitance (Csc). The other electrode of the liquid crystal capacitance (Clc) is a common electrode on the counter substrate side (not shown), and the other electrode of the auxiliary capacitance (Csc) is the auxiliary capacitance electrode (Sc). In addition, a parasitic capacitance (Cgs) is generated between the gate and the source.

FIG. 9 shows the structure of a conventional TFT. (A)
Is a plan view and (b) is a sectional view. Glass substrate (1
0) on which a gate electrode (11) is formed of Cr or the like, and a gate insulating film (12) such as SiN _x is formed on the gate electrode (11).
Is coated. On the gate insulating film (12) corresponding to the gate electrode (11), a-Si (13), passivation (14), and N ⁺ a-Si (15) are sequentially stacked, and on both sides of these layers. , A source electrode (16) and a drain electrode (17) made of Al or the like are formed and partially overlap with the gate electrode (11). This overlapping portion is an alignment margin for mask alignment and is a parasitic capacitance (Cgs). Although not shown in the drawing, a display electrode made of ITO is provided so as to be connected to the source electrode (16), and a liquid crystal capacitor (not shown) is provided so as to face a common electrode (not shown) on a substrate arranged with a liquid crystal layer in between. Clc) is formed.

When the liquid crystal display device having such a structure is driven, when the gate voltage Vg becomes H level and is turned ON, the voltage Vs of the source electrode (16) is the data applied to the drain electrode (17). After reaching the same level as the signal voltage, when the gate voltage Vg falls to the L level, ΔVs is momentarily affected by the parasitic capacitance (Cgs).
The voltage drops by the amount of. After that, the source voltage Vs is held in the liquid crystal capacitance (Clc) and the auxiliary capacitance (Csc) by the OFF resistance of the TFT, and is kept at a constant level for one field period. The source voltage drop amount ΔVs is determined by the change amount ΔVg of the gate voltage Vg, the liquid crystal capacitance Clc, and the TFT.
It is expressed by the following equation depending on the parasitic capacitance Cgs and the auxiliary capacitance Csc of.

[0007]

[Equation 1]

Conventionally, by lowering the level of the common electrode voltage Vcom by ΔVs below the center voltage level Vc of positive / negative inversion of the data signal, the liquid crystal capacitance (Clc).
The direct current component voltage applied to was deleted.

[0009]

FIG. 10 is a waveform diagram when a conventional liquid crystal display device is driven. From a high level of applied source voltage, a large positive voltage (Vs1), a small positive voltage (Vs2), 4 types of small negative voltage (Vs3) and large negative voltage (Vs4) are shown. The source voltages (Vs1, Vs2, Vs3, Vs4) are set to the same level as the drain voltages Vd1, Vd2, Vd3, Vd4 during the H level period of the gate voltage (Vg), respectively, and then the gate voltage (Vg) is changed to L. At the time of falling to the level, ΔVs1, ΔVs2, ΔVs3, and ΔVs, respectively.
The voltage drops by a magnitude of four. After that, the source voltages (Vs1, Vs2, Vs3, Vs4) are equal to the liquid crystal capacitance (C
lc) and the auxiliary capacitance (Csc) keep the constant level for one field period.

The source voltage drop amount ΔVs is determined by the liquid crystal capacitance Clc, the TFT parasitic capacitance Cgs, and the auxiliary capacitance Cs.
Although represented by Formula 1 depending on c, there are the following problems due to the anisotropy of the dielectric constant of the liquid crystal. That is, the applied voltage Vlcn (= Vsn-Vco) to the liquid crystal capacitance (Clc).
By increasing m) (n = 1, 2, 3, 4), the alignment state of the liquid crystal changes, and the liquid crystal capacitance (Clc) accordingly.
The capacity value of increases. Therefore, a large source voltage Vs
When 1, Vs4 is applied, the capacitance values of the liquid crystal capacitors (Clc1, Clc4) in each case become large, so the voltage drop amounts ΔVs1, ΔVs4 become relatively small, and when small source voltages Vs2, Vs3 are applied, Since the capacitance values of the liquid crystal capacitors (Clc2, Clc3) are small, the voltage drop amounts ΔVs2 and ΔVs3 are relatively large.

As in the prior art, the common electrode voltage (Vcom)
In the method of lowering the level of (1) by the source voltage drop amount ΔVs, the voltage drop amount differs depending on the source voltage level, and thus it cannot be sufficiently dealt with and the DC component remains. For example, when the common electrode voltage (Vcom) is applied with the source voltages Vs2 and Vs3, the liquid crystal capacitance (Clc
2, Clc3), ΔVs becomes large. At this time, when the source voltage Vs1 is applied, the applied voltage Vlc1 to the liquid crystal capacitance (Clc1) is ΔVs−Δ.
While a direct current component of Vs1 (> 0) occurs, the applied voltage Vlc4 to the liquid crystal capacitance (Clc4) when the source voltage Vs4 is applied is ΔVs4−ΔVs (<
A DC component of 0) is generated. For this reason, a large DC component remains as a whole, which causes image sticking, flicker, a decrease in contrast ratio, and the like, and the display quality is deteriorated.

On the other hand, if the auxiliary capacitance (Csc) is increased in order to reduce the DC component, the TFT size and the auxiliary capacitance electrode must be increased, so that the effective display area is reduced, the aperture ratio is lowered, and the superimposition is reduced. There have been problems such as an increase in short circuits due to an increase in area. In particular, C _S On G
In the ate method, the auxiliary capacitance on the gate line is increased to cause signal distortion, resulting in deterioration of display characteristics.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and firstly, two liquid crystal display elements are arranged so as to face each other with a liquid crystal interposed therebetween.
A liquid crystal display device including display electrodes arranged in a matrix on one of the opposing surfaces of one substrate, thin film transistors for applying a voltage to the display electrodes, and a common electrode entirely disposed on the other opposing surface. In, the thin film transistor, depending on the magnitude of the voltage applied to the display electrode, while lowering the voltage of the display electrode by a predetermined amount,
The voltage of the common electrode is set in consideration of the amount of voltage drop of the display electrode.

Secondly, in the first structure, the switching element is formed at an intersection of a gate line and a drain line arranged on the substrate so as to intersect with each other, and has a gate electrode, a gate insulating film, and a non-single-crystal semiconductor. Layers and sources
This is a thin film transistor in which each electrode of the drain is sequentially laminated, and its source electrode is connected to the display electrode.

Thirdly, in the second configuration, the thin film transistor has a source electrode width narrower than a drain electrode width. Fourthly, in the second configuration, the thin film transistor has a configuration in which the source electrode is divided into a plurality of portions in the overlapping portion of the source electrode and the gate electrode. Fifth, in the fourth structure, the distance between the divided source electrodes is within the range of 1.5 to 2.5 μm.

[0016]

In the first structure, by using a switching element for applying a voltage to the display electrode, which drops the voltage of the display electrode depending on the applied voltage, the DC component voltage applied to the liquid crystal capacitance is reduced. It can be reduced. That is, when the common electrode voltage is set in accordance with the state in which the applied voltage is small and the voltage drop is large, the DC component changes in the positive direction by increasing the voltage drop when a large negative voltage is applied, and Since it approaches the DC component when a positive voltage is applied, the difference in the DC component is reduced, and the DC component is reduced as a whole.

In the second configuration, the thin film transistor is
Since the electric conductivity of the non-single crystal semiconductor layer changes due to the electric field effect, the capacitance value of the parasitic capacitance between the gate and the source is controlled by the voltage between the gate and the source. In particular, by reducing the source electrode width, The change in the capacitance value of the parasitic capacitance between the gate and the source becomes large depending on the voltage between the gate and the source. That is, by reducing the overlapping area between the gate and the source, the parasitic capacitance is small when the electric field effect is small, and the high conductivity region of the non-single-crystal semiconductor layer expands as the electric field effect increases. The overlapping area between them also increases and the parasitic capacitance increases. That is, the amount of drop in the source voltage changes depending on the level of the source voltage.

In the third structure, since the source electrode is divided into a plurality of portions in the overlapping portion with the gate electrode, the amount of drop of the source voltage greatly changes depending on the level of the source voltage and the width of the source electrode is increased. O due to narrowing
The decrease in N current is suppressed. That is, the carrier in the non-single-crystal semiconductor layer takes a moving path that spreads with respect to the source electrode whose width is narrower than that of the drain electrode. Therefore, dividing the source electrode into a plurality of channels effectively reduces the channel width. can avoid.

In the a-Si TFT having the above-mentioned fourth structure, the width of the movement path of the a-Si layer was experimentally set to 2 μm.
Since it is known that the distance is around m, the ON current is prevented from decreasing by setting the interval between the divided source electrodes within the range of 1.5 to 2.5 μm.

[0020]

Next, examples of the present invention will be described. First,
The present invention is characterized by the structure of the TFT. FIG. 1 shows a plan view (a) and a sectional view (b) of a TFT according to an embodiment of the present invention. The same components as those in FIG. 9 of the conventional example are denoted by the same reference numerals. On the glass substrate (10), the gate electrode (11), the gate insulating film (12) covering the gate electrode, and the gate insulating film (12) corresponding to the gate electrode (11) are a-
Si (13), passivation (14), N ⁺ a-S
i (15) are sequentially stacked, and a source electrode (16) and a drain electrode (17) are formed on both sides of i (15),
It partially overlaps the gate electrode (11). (A), the width of the source electrode (16) (W _S) is smaller than the width of the drain electrode (17) (W _D).

FIG. 2 shows the result of simulation of the relationship between the gate-source voltage Vgs and the parasitic capacitance Cgs when the TFT is turned on. Vg
It can be seen that the value of Cgs increases as s increases. From this, as the level of the source voltage Vs decreases with respect to the gate voltage VgH at the time of ON, the gate
The source-to-source voltage Vgs increases and the parasitic capacitance Cgs (V
s) increases.

The cause of the change in the parasitic capacitance Cgs (Vs) depending on the source voltage Vs as described above can be considered as follows. As the gate-source voltage Vgs increases and the electric field strength increases, the high conductivity region of a-Si (13) sequentially expands, which increases the parasitic capacitance Cgs. FIG. 3 shows an equivalent circuit diagram of parasitic capacitance in the TFT of the present invention. CgsA is a parasitic capacitance formed between the gate electrode (11) and the source electrode (16) across the gate insulating film (12), and CgsB is a gate insulating film (12).
Is a parasitic capacitance formed between the gate electrode (11) and the source electrode (16) with the a-Si (13) sandwiched between them and CgsC.
Is a parasitic capacitance formed between the a-Si (13) and the gate electrode (11) with the gate insulating film (12) interposed therebetween. Cgs
Although A is always constant, in CgsB, since the conductivity of a-Si (13) changes due to the field effect of the gate-source voltage Vgs, the capacitance value changes depending on Vgs, and Cs
Increase to gsb. Further, CgsC has a capacitance value of V since a-Si, which is one of the electrodes of the capacitance, changes the area of the high-conductivity region depending on the electric field strength between the gate and the source.
Varies depending on gs. Thus, the TFT of the present invention
Shows that as the gate-source voltage Vgs increases, the parasitic capacitance CgsA + CgsB increases and CgsA + increases.
It becomes Cgsb, and when Vgs becomes larger, CgsA +
The capacitance value is changed by sequentially increasing to Cgsb + CgsC. That is, by forming the source electrode (16) in a small size in advance, the overlapping portion between the gate and the source is reduced to reduce the parasitic capacitance Cgs, and
As the level of the source voltage Vs decreases and the gate-source voltage Vgs increases, the parasitic capacitance Cgs (Vgs) increases largely depending on this.

Further, FIG. 4 shows the channel width (W
It is an experimental result about the relationship between _S ) and ON current (I _DS ). I when W _S is 10, 15, 20, 25 (μm)
_{When the} optimum straight line is estimated from the measured value of _DS , the intersection with the W _S axis is −2 μm. From this, the source width (W _S )
It can be seen that when is smaller than the drain width (W _D ), the effective channel width is about 2 μm wider than the source width (W _S ). This phenomenon is also caused by the electric field effect of a-Si (13).
It is presumed to be caused by the change in conductivity of the layer. From this, it can be seen that even if the width of the source electrode (16) is narrowed, the decrease of the ON current is suppressed.

FIG. 5 is a waveform diagram showing a driving method of a liquid crystal display device using, as a switching element, a TFT whose parasitic capacitance changes depending on the level of the source voltage Vs described above. The large positive source voltage (Vs1), the small positive source voltage (Vs2), the small negative source voltage (Vs3) and the large negative source voltage (Vs4) are applied during the H level period of the gate voltage Vg. After reaching the same level as the drain voltages Vd1, Vd2, Vd3, and Vd4, when the gate voltage Vg falls to the L level, ΔVs1, ΔVs2, ΔVs3, and ΔVs1, respectively.
The voltage drops by the magnitude of Vs4. After that, each source voltage Vsn (n = 1, 2, 3, 4) is equal to the liquid crystal capacitance Clc.
And the auxiliary capacitance Cgs, and kept at a constant level for one field period. Amount of drop of each source voltage ΔVsn
(N = 1, 2, 3, 4) is the change amount Δ of the gate voltage Vg.
Vg and the liquid crystal capacitance Clc (Vsn) that changes depending on the level of the source voltage and the parasitic capacitance Cgs (Vs of the TFT).
n) and depending on the auxiliary capacitance Csc, it is expressed by the following equation.

[0025]

[Equation 2]

As is clear from this equation, the source voltage V
Compared with the liquid crystal capacitances Clc2 and Clc3 for s2 and Vs3, the liquid crystal capacitance Clc for the source voltages Vs1 and Vs4
1, Clc4 is large, and the parasitic capacitance Cgsn (n
= 1, 2, 3, 4) is the source voltage Vsn (n = 1, 2,
3, 4) increases as the level decreases, the amount of voltage drop depends on changes in both Clcn and Cgsn, and ΔVs2, ΔVs3, and ΔVs4 with respect to ΔVs1.
Is relatively large. Then, the level of the common electrode voltage Vcom is changed from the center level Vc of positive / negative inversion of the drain voltage to the liquid crystal capacitance (Clc2, Clc) when the applied voltage is small.
In accordance with 3), ΔVcom = (ΔVs2 + ΔVs3)
Decrease the size by 1/2. At this time, when the source voltage Vs1 is applied, the applied voltage Vlc1 to the liquid crystal capacitance Clc1
(= Vs1−Vcom) is ΔVcom−ΔVs1 (>
0) including the DC component and applying the source voltage Vs4, the voltage Vlc4 (= Vco) applied to the liquid crystal capacitance Clc4.
In m-Vs4), a DC component of ΔVs4-ΔVcom (<=> 0) is generated.

Next, another embodiment of the TFT in which the parasitic capacitance changes depending on the level of the source voltage Vs will be described. In the relationship between the channel width and the ON current shown in FIG.
If narrower than the source electrode width (W _S) and a drain electrode width (W _D), the effective channel width of the source side 2
As a result of the increase of μm, the structure shown in FIG. 6 was invented. (A) is a plan view and (b) is a sectional view.
As shown in (a), in the TFT of this embodiment, the source electrode (16) is divided into a plurality of portions at the overlapping portion with the gate electrode (11). As a result, the characteristic that the parasitic capacitance Cgs between the gate and the source is reduced and the parasitic capacitance Cgs changes depending on the gate-source voltage Vgs is obtained. Particularly, in the present embodiment, the gap between the divided portions of the source electrode (16) is set to about 2 μm, so that O
It is possible to completely eliminate the decrease in N current.

By using the TFT which changes the parasitic capacitance depending on the level of the source voltage Vs as described above, the parasitic capacitance Cgs is reduced, the voltage drop amount ΔVs is reduced, and the gate-source voltage is reduced. As Vgs increases, the parasitic capacitance Cgs increases, and the direct current component can be reduced as a whole. That is, as shown in FIG. 5, by applying the source voltages Vs2 and Vs3, the liquid crystal capacitance C
Large voltage drop Δ when driving lc2 and Clc3
The common electrode voltage Vcom is set according to Vs2 and ΔVs3. Accordingly, the applied voltage Vl of the liquid crystal capacitance Clc1
For c1 (= Vs1-Vcom) (> 0), ΔVcom
A DC component of −ΔVs1 (> 0) is included, and the applied voltage Vlc4 (= Vcom−Vs of the liquid crystal capacitance Clc4 is included.
4) In (> 0), ΔVs4−ΔVcom (<=> 0)
DC component of is included. DC component of liquid crystal capacitance Clc4 Δ
Vs4-ΔVcom is the direct current component ΔV of the liquid crystal capacitance Clc1
Although smaller than com-ΔVs1, the voltage drop amount ΔVs4 is larger than ΔVs1 and the DC component ΔVs4-ΔVcom of the liquid crystal capacitance Clc4 increases in the positive direction because of the dependence of the parasitic capacitance Cgs on the level of the source voltage Vsn. , DC component ΔVcom-ΔVs1 of liquid crystal capacitance Clc1
The difference between As a result, the applied voltages Vlc1 and Vlc of the liquid crystal capacitors Clc1 and Clc4 whose polarities are opposite to each other are applied.
4, the size approaches, and the direct current component is reduced as a whole.

FIG. 7 shows the relationship between the parasitic capacitance Cgs and the DC component according to the magnitude of the dependency of the parasitic capacitance Cgs on the gate-source voltage Vgs. Cgs on the horizontal axis is the capacitance value when no voltage is applied, and Cgs is increased by increasing Vgs.
Represents the degree of dependence by (1) when the degree of dependence is 1.2, (2) is the case of 2, and as a comparative example, the case where the degree of dependence is 1 is (3). It was shown to. The DC component is
It can be seen that the greater the dependence on the gate-source voltage Vgs, the smaller the parasitic capacitance Cgs.

[0030]

As is clear from the above description, by using a switching element that changes the amount of voltage drop depending on the level of the applied voltage, it is possible to reduce the direct current component as a whole, and burn in Flicker and reduction in contrast ratio were prevented, and display quality could be improved. As such a switching element, there is a TFT having a narrow source electrode width, and the amount of voltage drop increases as the voltage between the gate and the source increases.

Further, since the direct current component is reduced by such a configuration, the auxiliary capacitance can be reduced. Therefore, by reducing the area of the auxiliary capacitance electrode, the loss of the effective display area is suppressed and the aperture ratio is reduced. Is improved. Furthermore,
If the auxiliary capacity becomes small, the charge amount will be small, so T
The size of the FT can be reduced, which further improves the aperture ratio and reduces the parasitic capacitance to further reduce the DC component. In this way, the reduction of the TFT and the reduction of the direct current component mutually enhance the effects.

In the C _S On Gate system,
Since the auxiliary capacitance on the gate line is reduced, signal distortion is reduced and display characteristics are improved. Therefore, the load is reduced due to the disconnection of the gate line, and even if the display characteristics are improved only on that line, the difference from other lines is reduced, so by making corrections using auxiliary wiring at the peripheral portion, etc., The yield can be improved.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view of a TFT according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram of a TFT for explaining the function and effect of the present invention.

FIG. 3 is an equivalent circuit diagram of a parasitic capacitance of a TFT for explaining the function and effect of the present invention.

FIG. 4 is a characteristic diagram of a TFT for explaining the function and effect of the present invention.

FIG. 5 is a waveform diagram showing a driving method of a liquid crystal display device according to an embodiment of the present invention.

FIG. 6 is a plan view and a sectional view of a TFT according to another embodiment of the present invention.

FIG. 7 is a characteristic diagram showing the function and effect of the present invention.

FIG. 8 is an equivalent circuit diagram of a liquid crystal display device.

FIG. 9 is a plan view and a cross-sectional view of a conventional TFT.

FIG. 10 is a waveform diagram illustrating a problem of the conventional liquid crystal display device.

[Explanation of symbols]

G1 to Gm gate lines D1 to Dn drain lines SE TFT Sc auxiliary capacitance electrode Clc liquid crystal capacitance Csc auxiliary capacitance Cgs parasitic capacitance 10 glass substrate 11 gate electrode 12 gate insulating film 13 a-Si 14 passivation 15 N ⁺ a-Si 16 source electrode 17 drain electrode Vs source voltage Vg gate voltage Vcom common electrode voltage Vlc voltage applied to liquid crystal capacitance

Claims (4)

[Claims] 1. A display electrode arranged in a matrix on one of the opposing surfaces of two substrates arranged to face each other with a liquid crystal sandwiched therebetween, a switching element for applying a voltage to the display electrode, and the other facing the other. In a liquid crystal display device comprising a common electrode arranged entirely on the surface, the switching element lowers the voltage of the display electrode by a predetermined amount depending on the magnitude of the voltage applied to the display electrode, The liquid crystal display device, wherein the voltage of the common electrode is set in consideration of the amount of voltage drop of the display electrode. 2. The switching element is formed at an intersection of a gate line and a drain line arranged on the substrate so as to intersect with each other, and includes a gate electrode, a gate insulating film, a non-single-crystal semiconductor layer, and a source / drain. 2. The liquid crystal display device according to claim 1, wherein each of the electrodes is a thin film transistor in which the electrodes are sequentially laminated, and the width of the source electrode is narrower than the width of the drain electrode. 3. The liquid crystal display device according to claim 2, wherein in the thin film transistor, the source electrode is divided into a plurality of portions at a portion where the source electrode and the gate electrode overlap each other. 4. The distance between the divided source electrodes is 1.
The liquid crystal display device according to claim 3, wherein the liquid crystal display device has a thickness in the range of 5 to 2.5 μm.