JPH05251700A - Thin film field effect type transistor - Google Patents

Abstract

PURPOSE:To obtain a thin film electric field effect type transistor capable of giving the same field through voltage to any picture elements within a screen by making the parasitic capacity constant for the thin film field effect type transistor. CONSTITUTION:Two TFTs are connected in parallel to one picture element for a chromium gate electrode 3 in such a manner that a drain electrode and a source electrode are located oppositely each other. As a result, overlap between gate electrode and drain electrode is deviated. And even through the CGS of an upper TFT increases or decreases, the CGS of a lower TFT decreases or increases by the same capacity so that the total value of CGSs remains constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film field effect transistor used in an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art A thin film field effect transistor (hereinafter abbreviated as TFT) has been attracting attention as a device for a high quality liquid crystal display. 11 is a plan view of a pixel portion of a liquid crystal display using a conventional TFT, and FIG. 12 is FIG.
FIG. 13 is a signal waveform diagram of each bus line and pixel electrode of the TFT of the circuit of FIG. In FIG. 11, 1 is a chrome drain bus line for supplying an image signal to a pixel, 2 is a chrome gate bus line for supplying a signal for turning on / off the TFT, 3 is a chrome gate electrode of the TFT, and 5 is a TFT. Chrome drain electrode, 7
Is a chromium source electrode of the TFT, and 9 is an ITO pixel electrode. In FIG. 12, 10 is a drain bus line, 11
Is a gate bus line, 12 is a TFT, 14 is a parasitic capacitance CGS1 formed at an overlapping portion of the chromium gate electrode 3 and the chromium source electrode 7, and 16 is a pixel capacitance CLC.

When a drive voltage as shown by the solid line in FIG. 13 is applied to the drain bus line 10 and the gate bus line 11 of the pixel having the structure shown in FIG. 12, the pixel voltage becomes the value shown by the dotted line in FIG. First, the pixel voltage is once written to the same value as the drain voltage before the gate voltage is turned off. Next, when the gate is turned off, the pixel voltage fluctuates by ΔVFT1 from the applied drain voltage, and thereafter holds that value. The cause of this voltage fluctuation ΔVFT1 is
This is because the gate bus line 11 and the pixel capacitance 16 are coupled by the parasitic capacitance CGS14 as shown in FIG. 11, and the magnitude of the variation ΔVFT1 is given by the difference between the ON voltage and the OFF voltage of the gate being ΔVG.

[0004]

[Equation 1]

The value is expressed by the following equation.

[0006]

When it is desired to obtain a uniform display with no brightness unevenness over the entire screen and to extend the life of the liquid crystal, the drive voltage of the liquid crystal is driven by an AC voltage having no DC component. Is desirable. For this purpose, the value of ΔVFT1 must be the same for all pixels in the screen. However, in an actual display, overlay misalignment occurs for each pattern on the screen. For example, FIG. 14 illustrates a case where the gate electrode and the drain electrode are misaligned. In FIG. 14, the chromium source electrode 7 is displaced to the right with respect to the chromium gate electrode 3. Therefore, the area of the overlapping portion of the chromium gate electrode 3 and the chromium source electrode 7 increases. This causes an increase in the capacity of CGS, which causes a change in the value of ΔVFT in the equation (1). FIG. 13 shows the voltage across the CLC when the CGS changes, as a chain line, and the value of ΔVFT as ΔVFT2.

When the value of ΔVFT varies depending on the pixel as described above, when the liquid crystal is driven with the common electrode potential as the center value, for example, the common electrode voltage is set so that a DC voltage is not applied to the pixel where the voltage fluctuation of ΔVFT1 occurs. When adjusted, Δ
A DC component is applied to the pixel in which the VFT2 voltage fluctuation occurs, and it is impossible to drive all the pixels with an AC signal having no DC component.

[0008]

A first invention is a thin film field effect transistor having a structure in which a gate electrode formed on an insulating substrate and a drain electrode and a source electrode are formed so as to overlap the gate electrode. A drain electrode connected to the drain bus line and overlapping with the gate electrode and a source electrode connected to the pixel electrode to form a thin film field effect transistor, and the gate electrode or the gate electrode is connected. A source auxiliary electrode which is connected to the pixel electrode and overlaps with a gate auxiliary electrode different from the gate electrode connected to the same gate bus line is disposed, and the source electrode and the source auxiliary electrode are connected to each other. The width is the same, and the edge portion of the gate electrode overlapping the source electrode and the gate auxiliary electrode overlap with each other. The edges of the overlapping gate electrode or gate auxiliary electrode are parallel, and the source auxiliary electrode overlaps the gate electrode or the gate auxiliary electrode with the gate electrode in the same direction as the drain electrode. It is characterized by having a structure.

A second invention is a thin film field effect transistor having a structure in which a gate electrode formed on an insulating substrate and a drain electrode and a source electrode are formed so as to overlap with the gate electrode. A first thin film field effect transistor having a first source electrode connected to the pixel electrode and a first drain electrode connected to the drain bus line, and the gate electrode or the gate electrode. A second gate electrode different from the gate electrode connected to the same gate bus line connected to the second source electrode connected to the pixel electrode and the drain bus line connected to the pixel electrode. A second thin film field effect transistor having a second drain electrode disposed therein, the first source electrode and the second source field effect transistor. The width of the electrode is the same, and the edge portion of the gate electrode that overlaps with the first source electrode and the edge of the gate electrode or the second gate electrode that overlaps with the second gate electrode. A portion is parallel, and the second source electrode overlaps the gate electrode or the second gate electrode in the same direction as the first drain electrode that overlaps the first gate electrode. It is characterized by having.

[0010]

In the TFT of the first aspect of the invention, the overlapping portion of the gate electrode and the pixel electrode is formed separately from the conventional TFT. Then, when the gate electrode and the source electrode of the TFT are misaligned and the area of the overlapped portion is increased or decreased,
A structure is formed in which the area of the overlapping portion of the gate electrode and the pixel electrode provided separately from the TFT is reduced or increased by the same amount as this area.

The TFT of the second invention has a structure in which the source electrode and the drain electrode are arranged opposite to the gate electrode of the conventional TFT. As a result, even if the CGS capacitance of the TFT increases or decreases due to misalignment, the capacitance of the CGS of the other TFT or the capacitance of the overlapping portion of the gate electrode and the source electrode of the other TFT decreases or increases by the same amount. CG of TFT connected to 1 pixel
The total amount of S does not change. Therefore, a constant CGS value can always be obtained even if there is a variation in the overlay on the surface of the display, and the value of ΔVFT can be made constant on the screen.

[0012]

(First Embodiment) FIG. 1 shows the T of a pixel of a liquid crystal display using a TFT according to the first embodiment of the present invention.
It is a top view of an FT portion. In FIG. 1, 1 is a chrome drain bus line, 2 is a chrome gate bus line, 3 is a first chrome gate electrode forming a TFT, 4 is a second chrome gate electrode forming an overlap with a chrome source electrode, Reference numeral 5 is a first chromium drain electrode, 7 is a first chromium source electrode, 8 is a second chromium source electrode, and 9 is I.
It is a TO pixel electrode.

FIG. 2 shows an equivalent circuit of FIG. In FIG. 2, 10 is a drain bus line, 11 is a gate bus line, 12 is a TFT, and 14 is parasitic capacitances CGS1 and 15 formed at the overlapping portion of the first chrome gate electrode 3 and the first chrome source electrode 7. The parasitic capacitances CGS2 and 16 formed at the overlapping portion of the second chrome gate electrode 4 and the second chrome source electrode 8 are pixel capacitances CLC. Let ΔVFT be the variation amount of the pixel voltage when the signal of the gate bus line is turned off, ΔVFT is

[0014]

[Equation 2]

It is expressed by the following equation.

Next, FIG. 3 shows a case where the gate electrode and the drain electrode are misaligned in the TFT having the structure shown in FIG. FIG. 3 shows a case where the drain electrode is displaced leftward with respect to the gate electrode. At this time, since the width W of the source electrode is constant, the area of the overlapping portion of the first gate electrode 3 and the first source electrode 7 increases, but the second gate electrode 4 and the second source electrode 7 have the same area. The area of the overlapping portion of 8 is reduced. As a result, the capacity of CGS1 in FIG. 2 increases, but the capacity of CGS2 decreases by that amount, so that the total capacity of CGS1 and CGS2 does not change even if the overlay is shifted. In the formula (2), CGS1 + CG
If S2 is constant, ΔVFT does not change. This is the same even when the drain electrode is displaced in the opposite direction with respect to the gate electrode. Therefore, with this structure, it can be seen that ΔVFT takes a constant value regardless of misalignment.

FIG. 4 shows a TFT according to the first embodiment of the present invention.
A plan view of a TFT portion of a pixel of a liquid crystal display using is shown. This is an example in which the second chromium gate electrode 4 is not used. In FIG. 4, 1 is a chrome drain bus line, 2 is a chrome gate bus line, 3
Is a first chrome gate electrode forming a TFT, and 5 is a first
Chrome drain electrode, 7 is the first chrome source electrode,
Reference numeral 8 is a second chromium source electrode, and 9 is an ITO pixel electrode. The equivalent circuit of FIG. 4 becomes a circuit similar to that of FIG.

Next, FIG. 5 shows a case where the gate electrode and the drain electrode are misaligned in the TFT having the structure shown in FIG. FIG. 5 shows a case where the drain electrode is displaced leftward with respect to the gate electrode. At this time, since the width of the first source electrode 7 and the width W of the second source electrode 8 are the same, the area of the overlapping portion of the first gate electrode 3 and the first source electrode 7 increases, but the same area. Only, the area of the overlapping portion of the first gate electrode 3 and the second source electrode 8 is reduced. As a result, it can be seen that ΔVFT takes a constant value regardless of the misalignment due to the same principle as in the embodiment using the second chromium gate electrode 4 described above.

The first embodiment has one TFT and the second one
Since the TFT is not formed in the portion of the capacitor formed by the gate electrode 4 and the second source electrode 8 of
It has a feature that it can be created with a simpler structure than the embodiment. Further, there is a feature that a channel is not formed in a portion of the capacitance formed by the second gate electrode 4 and the second source electrode 8 and therefore there is no photosensitivity, so that it is not necessary to provide a light shielding layer.

(Second Embodiment) FIG. 6 is a plan view of a TFT portion of a pixel of a liquid crystal display using a TFT according to a second embodiment of the present invention. In FIG. 6, 1 is a chrome drain bus line, 2 is a chrome gate bus line, 3
Is a first chrome gate electrode forming a TFT, and 5 is a first
First chrome drain electrode forming a second TFT, 6 is a second chrome drain electrode forming a second TFT, 7 is a first chrome source electrode forming a first TFT, and 8 is a second TFT Is a second chromium source electrode and 9 is an ITO pixel electrode.

FIG. 7 shows an equivalent circuit of FIG. In FIG. 7, 10 is a drain bus line, 11 is a gate bus line, 12 and 13 are TFTs, and 14 is a parasitic capacitance CGS1 formed at the overlapping portion of the first chrome gate electrode 3 and the first chrome source electrode 7. , 15 are parasitic capacitances CGS2 formed at the overlapping portion of the first chrome gate electrode 3 and the second chrome source electrode 8, and 16 is a pixel capacitance CLC. Letting ΔVFT be the variation amount of the pixel voltage when the signal of the gate bus line is turned off, ΔVFT is

[0022]

[Equation 3]

It is expressed by the following equation.

Next, FIG. 8 shows a case where the gate electrode and the drain electrode are misaligned in the TFT having the structure shown in FIG. FIG. 8 shows a case where the drain electrode is displaced leftward with respect to the gate electrode. At this time, since the widths W1 and W2 of the source electrode are constant, the first chromium gate electrode 3
The area of the overlapping portion of the first chromium source electrode 7 and the area of the overlapping portion of the first chromium gate electrode 3 and the second chromium source electrode 8 is increased by the same area. As a result, the capacity of CGS1 in FIG. 6 increases, but the capacity of CGS2 decreases accordingly, so that the total capacity of CGS1 and CGS2 does not change even if the overlay is shifted. In Expression (3), if CGS1 + CGS2 is constant, ΔVFT does not change. This is the same even when the drain electrode is displaced in the opposite direction with respect to the gate electrode.
Therefore, with this structure, it can be seen that ΔVFT takes a constant value regardless of misalignment.

FIG. 9 shows a TFT according to the second embodiment of the present invention.
A plan view of a TFT portion of a pixel of a liquid crystal display using is shown. This is an embodiment in which the present invention is realized by using the second chromium gate electrode 4. In FIG. 9, 1 is a chrome drain bus line, 2 is a chrome gate bus line, 3 is a first chrome gate electrode forming a TFT, 4 is a second chrome gate electrode forming a TFT,
Reference numeral 5 is a first chromium drain electrode, 6 is a second chromium drain electrode, 7 is a first chromium source electrode, 8 is a second chromium source electrode, and 9 is an ITO pixel electrode. The equivalent circuit of FIG. 9 becomes a circuit similar to that of FIG.

Next, in the TFT having the structure shown in FIG. 9, a case where the overlapping of the gate electrode and the drain electrode is shifted is shown in FIG.
Shown in. FIG. 10 shows a case where the drain electrode is displaced leftward with respect to the gate electrode. At this time, since the widths W1 and W2 of the source electrodes are constant, the area of the overlapping portion of the first gate electrode 3 and the first source electrode 7 increases, but the area of the second gate electrode 4 and the second gate electrode 4 is the same area. The area of the overlapping portion of the source electrode 8 is reduced. As a result, the capacity of CGS1 in FIG. 9 increases, but the capacity of CGS2 decreases accordingly, so that even if the overlay is shifted, CGS1 and CGS1
The total capacity of GS2 does not change. In equation (3),
If CGS1 + CGS2 is constant, ΔVFT does not change. This is the same even when the drain electrode is displaced in the opposite direction with respect to the gate electrode. Therefore, with this structure, it can be seen that ΔVFT also takes a constant value regardless of misalignment.

The thin film field effect transistor of the present invention has one
Since two TFTs are arranged in each pixel, one TFT
Since the signal voltage is not completely stopped from being supplied to the pixel electrode even if the pixel is destroyed, the display defect of the pixel is reduced and the redundancy is provided. Also, since the gate electrode and the source electrode overlap each other at two locations to form a TFT and it is not necessary to provide an auxiliary electrode in addition to the TFT, the ratio of the area of the element occupied in the pixel to that in the first embodiment is smaller than that in the first embodiment. Can be made smaller.

Using the thin film field effect transistor of the present invention, 400 gate bus lines and drain bus lines R
When a display for a portable computer of 640 GB each was created, the brightness unevenness that had conventionally occurred in the display surface was reduced to the extent that it was not visually recognized. Further, the phenomenon of image sticking disappeared and the life of the liquid crystal was extended.

Although ITO is used as the transparent conductive film of the pixel electrode in the above two embodiments, In ₂ O ₃ and Sn ₂ O ₃ can also be used. Further, as each interlayer insulating film, S
SiO ₂ may be used instead of iN _x . Further, instead of chromium for the gate electrode and bus line, drain electrode and drain bus line, and source electrode, Ta, Al, M
It is also possible to use other metals such as o and Ti.

[0030]

As described above, the thin film field effect transistor of the present invention is capable of reducing the phenomenon such as uneven brightness and burn-in caused by the difference in feedthrough voltage ΔVFT caused by the difference in parasitic capacitance CGS. You can Also, since the direct current component applied to the liquid crystal can be reduced,
It has the effect of extending the life of the liquid crystal itself.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the first embodiment.

FIG. 3 is a plan view in the case where the overlay is deviated in the first embodiment.

FIG. 4 is a diagram showing a first example in which a second gate electrode is not used.

5 is a diagram showing a case where misalignment occurs in the TFT having the configuration of FIG.

FIG. 6 is a plan view showing the structure of the second exemplary embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of the second embodiment.

FIG. 8 is a plan view in the case where the overlay is shifted in the second embodiment.

FIG. 9 is a diagram showing a second example using a second gate electrode.

FIG. 10 is a diagram showing a case where misalignment occurs in the TFT having the configuration of FIG. 9;

FIG. 11 is a plan view showing the structure of a conventional TFT.

FIG. 12 is an equivalent circuit of a conventional TFT.

13 is a signal waveform diagram of each part of FIG.

FIG. 14 is a plan view when the conventional TFTs are misaligned.

[Explanation of symbols]

 1 Chromium Drain Bus Line 2 Chromium Gate Bus Line 3 First Chromium Gate Electrode 4 Second Chromium Gate Electrode 5 First Chromium Drain Electrode 6 Second Chromium Drain Electrode 7 First Chromium Source Electrode 8 Second Chromium Source electrode 9 ITO pixel electrode 10 Drain bus line 11 Gate bus line 12, 13 TFT 14 CGS1 15 CGS2 16 CLC

Claims (2)

[Claims] 1. In a thin film field effect transistor having a structure in which a gate electrode formed on an insulating substrate and a drain electrode and a source electrode are formed so as to overlap the gate electrode, the drain bus overlaps with the gate electrode. A drain electrode connected to the line and a source electrode connected to the pixel electrode are provided to form a thin film field effect transistor, and the gate electrode or the same gate bus line to which the gate electrode is connected is connected. A source auxiliary electrode which is overlapped with the gate auxiliary electrode different from the gate electrode and is connected to the pixel electrode,
The source electrode and the source auxiliary electrode have the same width, and the edge portion of the gate electrode overlapping the source electrode and the gate electrode or the edge portion of the gate auxiliary electrode overlapping the gate auxiliary electrode. Are parallel to each other, and the source auxiliary electrode has a structure in which the source auxiliary electrode overlaps the gate electrode or the gate electrode in the same direction as the drain electrode overlapping the gate electrode. .. 2. A thin film field effect transistor having a structure in which a gate electrode formed on an insulating substrate and a drain electrode and a source electrode are formed so as to overlap with the gate electrode. A first source electrode connected to the pixel electrode and a first drain electrode connected to the drain bus line are provided.
And a second gate electrode different from the gate electrode connected to the gate electrode or the same gate bus line to which the gate electrode is connected, to the pixel electrode. A second thin film field effect transistor in which a second source electrode connected to the drain bus line and a second drain electrode connected to the drain bus line are arranged is configured, and the first source electrode and the second source electrode are connected to each other. The source electrodes have the same width, and the edge portion of the gate electrode that overlaps the first source electrode and the edge of the gate electrode or the second gate electrode that overlaps the second gate electrode. The first portion is parallel and the second source electrode overlaps the first gate electrode with respect to the gate electrode or the second gate electrode. The thin film field-effect transistor characterized by having a structure overlapping the same direction as the drain electrode.