CN108598155A - Thin film transistor (TFT), array substrate and display device - Google Patents
Thin film transistor (TFT), array substrate and display device Download PDFInfo
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- CN108598155A CN108598155A CN201810349168.1A CN201810349168A CN108598155A CN 108598155 A CN108598155 A CN 108598155A CN 201810349168 A CN201810349168 A CN 201810349168A CN 108598155 A CN108598155 A CN 108598155A
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 239000010409 thin film Substances 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000010586 diagram Methods 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- Engineering & Computer Science (AREA)
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of thin film transistor (TFT)s, including grid, source-drain electrode metal layer and semiconductor layer；The grid setting is on the transparent substrate；It is additionally provided with gate insulating layer on the transparent substrate and covers the grid；The semiconductor layer setting is on the gate insulating layer and positioned at the top of the grid；The source-drain electrode metal layer is arranged on the semiconductor layer, including source electrode and drain electrode, the source electrode and the drain electrode are separated from each other and are contacted with the semiconductor layer, the semiconductor layer is equipped with raceway groove, the raceway groove is arranged between the source electrode and the drain electrode, the grid and the source-drain electrode metal layer have an overlapping region on the transparent substrate direction, at least one engraved structure being provided with for reducing the facing area between the grid and the source-drain electrode metal layer in the grid and the source-drain electrode metal layer.The invention further relates to a kind of array substrate and display devices.
Description
Technical field
The present invention relates to the technical fields of display, more particularly to a kind of thin film transistor (TFT), array substrate and display device.
Background technology
Display device, such as liquid crystal display device (liquid crystal display, LCD) has that image quality is good, volume
Small, light-weight, low driving voltage, low-power consumption, radiationless and relatively low manufacturing cost advantage account for master in flat display field
Lead status.Liquid crystal display device includes several parts such as array substrate, colored optical filtering substrates and backlight module.Array substrate includes：
It transparent substrate and is formed in multi-strip scanning line (Scan Line) and multiple data lines (Data Line) on transparent substrate, it is more
Scan line and multiple data lines intersect to form multiple pixel units, and each pixel unit includes thin film transistor (TFT) (Thin
Film Transistor, TFT) and pixel electrode, state of the thin film transistor (TFT) as switching device for controlling pixel unit.
As shown in Figure 1, the equivalent circuit of each pixel unit is by thin film transistor (TFT), pixel liquid crystal layer capacitance in array substrate
Clc, pixel storage capacitor Cst compositions, and the pixel unit is electrically connected grid by the grid G of thin film transistor (TFT) via scan line
Pole driving chip (Gate Driver IC), and driven via data line electrical connection source electrode by the source S of thin film transistor (TFT)
Dynamic chip (Source Driver IC), the drain D of thin film transistor (TFT) be electrically connected a pixel electrode, pixel liquid crystal layer capacitance and
Pixel storage capacitor.When gate turn-on of the grid drive chip by scanning line driving thin film transistor (TFT), from source drive core
The data voltage signal of piece input can be transferred to pixel liquid crystal layer electricity via data line from the source electrode and drain electrode of thin film transistor (TFT)
Hold and pixel storage capacitor, and stores the voltage signal received by it by pixel liquid crystal layer capacitance and pixel storage capacitor.
There is also several parasitic capacitances for the pixel circuit of array substrate.As shown in Fig. 2, existing thin film transistor (TFT) includes
Grid 10, source electrode 21, drain electrode 22 and the semiconductor layer 30 being arranged in transparent substrate (not shown), semiconductor layer 30 are arranged in grid
The top of pole 10, source electrode 21 and 22 same layers of drain electrode are arranged and are separated from each other and are contacted with semiconductor layer 30, part of semiconductor layer 30
Expose between source electrode 21 and drain electrode 22 and forms raceway groove 31.On the direction perpendicular to transparent substrate, grid 10 and source electrode 21, grid
There is overlapping region between pole 10 and drain electrode 22, which will generate parasitic capacitance, as between grid and drain electrode
Overlap capacitance Cgs between overlap capacitance Cgd, grid and source electrode etc..When the voltage in scan line is raised to by grid drive chip
When scan line high voltage Vgh, the voltage on data line also is risen to start to charge to pixel electrode by source driving chip.
When the voltage of pixel electrode rises to predetermined voltage, the voltage in scan line drops to scan line low-voltage Vgl.At this point, scanning
Pressure drop on line causes coupling effect to pixel electrode and the voltage on pixel electrode is made also to generate a pressure drop Δ Vp.The pressure drop Δ
Vp is also referred to as feed-trough voltage (Feed Through Voltage), with the overlap capacitance Cgd between grid and drain electrode, pixel
Liquid crystal layer capacitance Clc, pixel storage capacitor Cst, scan line high voltage (Vgh) and the number represented by scan line low-voltage (Vgl)
It is as follows to learn relational expression：
△ Vp=(Vgh-Vgl) × { Cgd/ (Cgd+Clc+Cst) }
Feed-trough voltage can lead to problems such as to show film flicker, image retention and gray scale entanglement, reduce the display product of display device
Matter.During forming feed-trough voltage, influences of the overlap capacitance Cgd to feed-trough voltage between grid and drain electrode is maximum.Again
Have, the width and length of raceway groove 31 can also have an impact feed-trough voltage, and the width of raceway groove 31 and long selection also relate to film crystal
ON state current, off-state current, aperture opening ratio of pipe etc., it is therefore desirable to selection can take into account the raceway groove 31 optimized after each side width and
It is long.Under the premise of the width of raceway groove 31 and a length of definite value, how to further decrease feed-trough voltage to promote display quality is in the industry
One of personnel's problem to be solved.
Invention content
The purpose of the present invention is to provide a kind of thin film transistor (TFT), array substrate and display devices, can reduce feed-trough voltage,
Improve the display quality of display device.
The embodiment of the present invention provides a kind of thin film transistor (TFT), including grid, source-drain electrode metal layer and semiconductor layer；It is described
Grid is arranged on the transparent substrate；It is additionally provided with gate insulating layer on the transparent substrate and covers the grid；The semiconductor layer
It is arranged on the gate insulating layer and positioned at the top of the grid；The source-drain electrode metal layer is arranged in the semiconductor layer
On, including source electrode and drain electrode, the source electrode and the drain electrode are separated from each other and are contacted with the semiconductor layer, the semiconductor layer
Equipped with raceway groove, the raceway groove is arranged between the source electrode and the drain electrode, and the grid is hanging down with the source-drain electrode metal layer
Directly in having overlapping region on the transparent substrate direction, the grid is provided with at least one in the source-drain electrode metal layer
Engraved structure for reducing the facing area between the grid and the source-drain electrode metal layer.
Further, the engraved structure is the first engraved structure being arranged on the grid.
Further, the grid has the first crossover region with the source electrode on the transparent substrate direction
Domain, the grid have the second overlapping region with drain electrode on the transparent substrate direction；First engraved structure
Second including the first pierced pattern in first overlapping region is arranged and is arranged in second overlapping region engraves
Null pattern.
Further, the engraved structure is the second engraved structure being arranged on the source electrode and the drain electrode.
Further, the source electrode has the first overlapping region, institute with grid on the transparent substrate direction
State drain electrode and grid has the second overlapping region on the transparent substrate direction；Second engraved structure includes setting
The 4th pierced pattern set the third pierced pattern in first overlapping region and be arranged in second overlapping region.
Further, the engraved structure is the first engraved structure being arranged on the grid and is arranged in the source
The second engraved structure on pole, the drain electrode.
Further, the grid has the first overlapping region, institute with source electrode on the transparent substrate direction
State grid and drain electrode has the second overlapping region on the transparent substrate direction；First engraved structure includes setting
The second pierced pattern set the first pierced pattern in first overlapping region and be arranged in second overlapping region；
Second engraved structure includes that the third pierced pattern being arranged in first overlapping region and setting are handed over described second
The 4th pierced pattern in folded region.
Further, first engraved structure and second engraved structure are on the transparent substrate direction
Overlapping area be more than first overlapping region and second overlapping region the gross area 80% or more.
The embodiment of the present invention provides a kind of array substrate, and the array substrate includes multi-strip scanning line and multiple data lines,
The multi-strip scanning line and the multiple data lines, which intersect, limits multiple pixel units, and each pixel unit includes pixel
Electrode, each pixel unit further include above-mentioned thin film transistor (TFT), the grid of the thin film transistor (TFT) and corresponding scanning
Line connects, and the drain electrode of the thin film transistor (TFT) is connect with the pixel electrode.
The embodiment of the present invention provides a kind of display device, including above-mentioned array substrate.
In thin film transistor (TFT) provided in an embodiment of the present invention, grid is with source-drain electrode metal layer perpendicular to transparent substrate direction
Upper have an overlapping region, grid in source-drain electrode metal layer it is at least one be provided with for reduce grid and source-drain electrode metal layer it
Between facing area engraved structure, by reducing the facing area between grid and source electrode, grid and drain electrode, and then reduce
Overlap capacitance (parasitic capacitance) between grid and source electrode, grid and drain electrode is opened for pixel electrode charging in thin film transistor (TFT)
In the process, the feed-trough voltage for being coupled to and making on pixel electrode is effectively reduced, the display quality of display device is improved.
Description of the drawings
Fig. 1 is the equivalent circuit diagram of a pixel unit in a kind of existing array substrate.
Fig. 2 is the partial structural diagram of thin film transistor (TFT) shown in FIG. 1.
Fig. 3 is the partial structural diagram of the thin film transistor (TFT) of first embodiment of the invention.
Fig. 4 is the structural schematic diagram of the grid of the thin film transistor (TFT) of first embodiment of the invention.
Fig. 5 is the structural schematic diagram of the source-drain electrode of the thin film transistor (TFT) of first embodiment of the invention.
Fig. 6 is the schematic cross-section along line A-A in Fig. 3.
Fig. 7 is the partial structural diagram of the thin film transistor (TFT) of second embodiment of the invention.
Fig. 8 is the structural schematic diagram of the grid of the thin film transistor (TFT) of second embodiment of the invention.
Fig. 9 is the structural schematic diagram of the source-drain electrode of the thin film transistor (TFT) of second embodiment of the invention.
Figure 10 is the schematic cross-section along line B-B in Fig. 7.
Figure 11 is the partial structural diagram of the thin film transistor (TFT) of third embodiment of the invention.
Figure 12 is the structural schematic diagram of the grid of the thin film transistor (TFT) of third embodiment of the invention.
Figure 13 is the structural schematic diagram of the source-drain electrode of the thin film transistor (TFT) of third embodiment of the invention.
Figure 14 is the schematic cross-section along line C-C in Figure 11.
Specific implementation mode
It is of the invention to reach the technical approach and effect that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Specific implementation mode, structure, feature and its effect of the present invention is described in detail as after in accompanying drawings and embodiments.
[first embodiment]
It please join Fig. 3 to Fig. 6, the thin film transistor (TFT) that first embodiment of the invention provides includes being arranged on transparent substrate 100
Grid 110, source-drain electrode metal layer 120 and semiconductor layer 300.Wherein, grid 110 is arranged on transparent substrate 100；It is transparent
It is additionally provided with gate insulating layer 101 on substrate 100 and covers the grid 110；Semiconductor layer 300 is arranged on gate insulating layer 101 simultaneously
Positioned at the top of grid 110；Source-drain electrode metal layer 120 is arranged on semiconductor layer 300, including source electrode 121 and drain electrode 122, source
Pole 121 and drain electrode 122 are separated from each other and are contacted with semiconductor layer 300, and semiconductor layer 300 is equipped with raceway groove 301, and raceway groove 301 is arranged
Between source electrode 121 and drain electrode 122.
Source electrode 121 is U-typed or " C " type structure, but is not limited thereto.The U-typed of the source electrode 121 or " C " type structure
Opening towards drain electrode 122.
Drain electrode 122 is wherein long strip type close to one end of source electrode 121 and partly stretches into the U-typed or " C " type of source electrode 121
The opening of structure.The other end of drain electrode 122 with pixel electrode for connecting.
Grid 110 has overlapping region, grid 110 with source-drain electrode metal layer 120 on 100 direction of transparent substrate
With at least one right opposite being provided with for reducing between grid 110 and source-drain electrode metal layer 120 in source-drain electrode metal layer 120
Long-pending engraved structure.In the present embodiment, grid 110 is equipped with for reducing between grid 110 and source-drain electrode metal layer 120 just
To the first engraved structure 130 of area.
Specifically, grid 110 has the first overlapping region S1, grid with source electrode 121 on 100 direction of transparent substrate
Pole 110 has the second overlapping region S2 with drain electrode 122 on 100 direction of transparent substrate.First engraved structure 130 is arranged
In the first overlapping region S1 and the second overlapping region S2.
In the present embodiment, the first engraved structure 130 includes the first pierced pattern 131 being arranged in the first overlapping region S1
With the second pierced pattern 132 being arranged in the second overlapping region S2.But it is not limited thereto, in other embodiments, also may be used
Pierced pattern only is arranged in a wherein overlapping region.
In the present embodiment, the gross area of the first engraved structure 130 is more than the first overlapping region S1 and the second overlapping region S2
The gross area 50% or more.
As shown in figure 4, in the present embodiment, the first pierced pattern 131 is two arcuate structures being arranged concentrically with source electrode 121
1311,1312, the second pierced pattern 132 is a U-typed structure, but is not limited thereto.
First engraved structure 130 is set on grid 110, reduces grid 110 and source electrode 121, grid 110 and drain electrode
Facing area between 122, and then reduce the overlap capacitance between grid 110 and source electrode 121, grid 110 and drain electrode 122
(parasitic capacitance) is opened in thin film transistor (TFT) in pixel electrode charging process, and effectively reducing to be coupled to makes on pixel electrode
Feed-trough voltage.
Width and a length of definite value of the following table for the thin film transistor (TFT) of the present embodiment and the thin film transistor (TFT) of the prior art in raceway groove
Under the premise of Property comparison, as can be seen from the table, between the grid 110 of the thin film transistor (TFT) of the present embodiment and drain electrode 122
Overlap capacitance is reduced (have dropped 35%) compared with prior art, the minimum of the feed-trough voltage of the thin film transistor (TFT) of the present embodiment
Value and maximum value have reduction (having dropped 36% and 34%) by a relatively large margin compared with prior art.
[second embodiment]
It please join Fig. 7 to Figure 10, the thin film transistor (TFT) that second embodiment of the invention provides includes being arranged on transparent substrate 100
Grid 110, source-drain electrode metal layer 120 and semiconductor layer 300.Wherein, grid 110 is arranged on transparent substrate 100；It is transparent
It is additionally provided with gate insulating layer 101 on substrate 100 and covers the grid 110；Semiconductor layer 300 is arranged on gate insulating layer 101 simultaneously
Positioned at the top of grid 110；Source-drain electrode metal layer 120 is arranged on semiconductor layer 300, including source electrode 121 and drain electrode 122, source
Pole 121 and drain electrode 122 are separated from each other and are contacted with semiconductor layer 300, and semiconductor layer 300 is equipped with raceway groove 301, and raceway groove 301 is arranged
Between source electrode 121 and drain electrode 122.
Source electrode 121 is U-typed or " C " type structure, but is not limited thereto.The U-typed of the source electrode 121 or " C " type structure
Opening towards drain electrode 122.
Drain electrode 122 is wherein long strip type close to one end of source electrode 121 and partly stretches into the U-typed or " C " type of source electrode 121
In the opening of structure.The other end of drain electrode 122 with pixel electrode for connecting.
Grid 110 has overlapping region, grid 110 with source-drain electrode metal layer 120 on 100 direction of transparent substrate
With at least one right opposite being provided with for reducing between grid 110 and source-drain electrode metal layer 120 in source-drain electrode metal layer 120
Long-pending engraved structure.In the present embodiment, source-drain electrode metal layer 120 is equipped with for reducing grid 110 and source-drain electrode metal layer 120
Between facing area the second engraved structure 140.
Specifically, source electrode 121 has the first overlapping region S1, leakage with grid 110 on 100 direction of transparent substrate
Pole 122 has the second overlapping region S2 with grid 110 on 100 direction of transparent substrate.Second engraved structure 140 is arranged
In the first overlapping region S1 and the second overlapping region S2.
In the present embodiment, the second engraved structure 140 includes the third pierced pattern 141 being arranged in the first overlapping region S1
With the 4th pierced pattern 142 being arranged in the second overlapping region S2.But it is not limited thereto, in other embodiments, also may be used
Pierced pattern only is arranged in a wherein overlapping region.
In the present embodiment, the gross area of the second engraved structure 140 is more than the first overlapping region S1 and the second overlapping region S2
The gross area 30% or more.
As shown in fig. 7, in the present embodiment, third pierced pattern 141 is an arc knot being arranged concentrically with source electrode 121
Structure, the 4th pierced pattern 142 are a long strip type knot identical with the close drain electrode length extending direction of 122 one end of drain electrode 122
Structure, but be not limited thereto.
Second engraved structure 140 is set on source-drain electrode metal layer 120, reduces grid 110 and source electrode 121, grid 110
With the facing area between drain electrode 122, and then reduce overlapping between grid 110 and source electrode 121, grid 110 and drain electrode 122
Capacitance (parasitic capacitance) is opened in thin film transistor (TFT) in pixel electrode charging process, and effectively reducing to be coupled to keeps pixel electric
Feed-trough voltage on extremely.
Width and a length of definite value of the following table for the thin film transistor (TFT) of the present embodiment and the thin film transistor (TFT) of the prior art in raceway groove
Under the premise of Property comparison, as can be seen from the table, between the grid 110 of the thin film transistor (TFT) of the present embodiment and drain electrode 122
Overlap capacitance is reduced (have dropped 3.2%) compared with prior art, and the feed-trough voltage of the thin film transistor (TFT) of the present embodiment is most
Small value and maximum value are also reduced and (have dropped 4%) compared with prior art.
[3rd embodiment]
It please join Figure 11 to Figure 14, the thin film transistor (TFT) that third embodiment of the invention provides includes being arranged in transparent substrate 100
On grid 110, source-drain electrode metal layer 120 and semiconductor layer 300.Wherein, grid 110 is arranged on transparent substrate 100；Thoroughly
It is additionally provided with gate insulating layer 101 on bright substrate 100 and covers the grid 110；Semiconductor layer 300 is arranged on gate insulating layer 101
And positioned at the top of grid 110；Source-drain electrode metal layer 120 is arranged on semiconductor layer 300, including source electrode 121 and drain electrode 122,
Source electrode 121 and drain electrode 122 are separated from each other and are contacted with semiconductor layer 300, and semiconductor layer 300 is equipped with raceway groove 301, and raceway groove 301 is set
It sets between source electrode 121 and drain electrode 122.
Source electrode 121 is U-typed or " C " type structure, but is not limited thereto.The U-typed of the source electrode 121 or " C " type structure
Opening towards drain electrode 122.
Drain electrode 122 is wherein long strip type close to one end of source electrode 121 and partly stretches into the U-typed or " C " type of source electrode 121
The opening of structure.The other end of drain electrode 122 with pixel electrode for connecting.
Grid 110 has overlapping region, grid 110 with source-drain electrode metal layer 120 on 100 direction of transparent substrate
With at least one right opposite being provided with for reducing between grid 110 and source-drain electrode metal layer 120 in source-drain electrode metal layer 120
Long-pending engraved structure.In the present embodiment, grid 110 is equipped with for reducing between grid 110 and source-drain electrode metal layer 120 just
To the first engraved structure 130 of area；Source-drain electrode metal layer 120 is equipped with for reducing grid 110 and source-drain electrode metal layer 120
Between facing area the second engraved structure 140.
Specifically, grid 110 has the first overlapping region S1, grid with source electrode 121 on 100 direction of transparent substrate
Pole 110 has the second overlapping region S2 with drain electrode 122 on 100 direction of transparent substrate.First engraved structure 130 and
Two engraved structures 140 are arranged at the first overlapping region S1 and the second overlapping region S2.
In the present embodiment, the first engraved structure 130 includes the first pierced pattern 131 being arranged in the first overlapping region S1
With the second pierced pattern 132 being arranged in the second overlapping region S2.But it is not limited thereto, in other embodiments, also may be used
Pierced pattern only is arranged in a wherein overlapping region.
In the present embodiment, the second engraved structure 140 includes the third pierced pattern 141 being arranged in the first overlapping region S1
With the 4th pierced pattern 142 being arranged in the second overlapping region S2.But it is not limited thereto, in other embodiments, also may be used
Pierced pattern only is arranged in a wherein overlapping region.
In the present embodiment, the first engraved structure 130 and the second engraved structure 140 are on 100 direction of transparent substrate
80% or more of the gross area of the gross area of coincidence more than the first overlapping region S1 and the second overlapping region S2.
In the present embodiment, as shown in figure 12, the first pierced pattern 131 is two arc knots being arranged concentrically with source electrode 121
Structure 1311,1312, the second pierced pattern 132 are a U-typed structure；As shown in figure 13, third pierced pattern 141 be one with
The arcuate structure that source electrode 121 is arranged concentrically, the 4th pierced pattern 142 are the length with drain electrode 122 close to 122 one end of drain electrode
The identical long strip type structure of extending direction.As shown in Figure 10, the first pierced pattern 131 and third pierced pattern 141 perpendicular to
Most of first overlapping region S1 will be occupied after being overlapped on 100 direction of transparent substrate.Second pierced pattern 132 and the 4th is engraved
Null pattern 142 will occupy most of second overlapping region S2 after overlapping.
The first engraved structure 130 is set on grid 110 and the second hollow out knot is set on source-drain electrode metal layer 120 simultaneously
Structure 140 greatly reduces the facing area between grid 110 and source electrode 121, grid 110 and drain electrode 122, and then reduces grid
Overlap capacitance (parasitic capacitance) between pole 110 and source electrode 121, grid 110 and drain electrode 122, picture is opened in thin film transistor (TFT)
During plain electrode charge, the feed-trough voltage for being coupled to and making on pixel electrode is effectively reduced.
Width and a length of definite value of the following table for the thin film transistor (TFT) of the present embodiment and the thin film transistor (TFT) of the prior art in raceway groove
Under the premise of Property comparison, as can be seen from the table, between the grid 110 of the thin film transistor (TFT) of the present embodiment and drain electrode 122
Overlap capacitance has reduction (having dropped 49.8%) by a relatively large margin, the feedthrough electricity of the thin film transistor (TFT) of the present embodiment compared with prior art
The minimum value and maximum value of pressure have reduction (having dropped 51% and 50%) by a relatively large margin compared with prior art.
The invention further relates to a kind of array substrate, which includes multi-strip scanning line and multiple data lines, a plurality of to sweep
It retouches line and multiple data lines intersects and are arranged to limit multiple pixel units, each pixel unit includes pixel electrode,
Each pixel unit further includes above-mentioned thin film transistor (TFT), and the grid 110 of thin film transistor (TFT) and corresponding scan line connect, film
The drain electrode 122 of transistor is connect with the pixel electrode in the pixel unit.
The invention further relates to a kind of display device, which includes above-mentioned array substrate.The display device is for example
It is liquid crystal display device, includes colored optical filtering substrates opposed with the array substrate and be folded in the array substrate and colour filter
The other structures of liquid crystal layer between photopolymer substrate, display device are well known to those skilled in the art, and details are not described herein.
The above is only the preferred embodiment of the thin film transistor (TFT), array substrate and display device of the present invention, and
Present invention is not to be limited in any way, is not to limit although the present invention has been disclosed as a preferred embodiment
The fixed present invention, any person skilled in the art take off when using above-mentioned without departing from the scope of the present invention
The technology contents shown make a little change or the equivalent embodiment for being modified to equivalent variations, as long as being without departing from the technology of the present invention side
Case content, according to the technical essence of the invention to any simple modification, equivalent change and modification made by above example, still
Belong in the range of technical solution of the present invention.
Claims (10)
1. a kind of thin film transistor (TFT), including grid (110), source-drain electrode metal layer (120) and semiconductor layer (300)；The grid
Pole (110) is arranged on transparent substrate (100)；It is additionally provided on the transparent substrate (100) described in gate insulating layer (101) covering
Grid (110)；The semiconductor layer (300) is arranged on the gate insulating layer (101) and positioned at the upper of the grid (110)
Side；The source-drain electrode metal layer (120) is arranged on the semiconductor layer (300), including source electrode (121) and drain electrode (122), institute
It states source electrode (121) and the drain electrode (122) is separated from each other and is contacted with the semiconductor layer (300), the semiconductor layer (300)
Equipped with raceway groove (301), the raceway groove (301) is arranged between the source electrode (121) and the drain electrode (122), which is characterized in that
The grid (110) has crossover region with the source-drain electrode metal layer (120) on the transparent substrate (100) direction
Domain, the grid (110) are provided with at least one in the source-drain electrode metal layer (120) for reducing the grid (110)
The engraved structure of facing area between the source-drain electrode metal layer (120).
2. thin film transistor (TFT) according to claim 1, which is characterized in that the engraved structure is to be arranged in the grid
(110) the first engraved structure (130) on.
3. thin film transistor (TFT) according to claim 2, which is characterized in that the grid (110) exists with the source electrode (121)
There is the first overlapping region (S1), the grid (110) to exist with drain electrode (122) on the transparent substrate (100) direction
There is the second overlapping region (S2) on the transparent substrate (100) direction；First engraved structure (130) includes setting
It sets the first pierced pattern (131) in first overlapping region (S1) and is arranged in second overlapping region (S2)
Second pierced pattern (132).
4. thin film transistor (TFT) according to claim 1, which is characterized in that the engraved structure is to be arranged in the source electrode
(121) and it is described drain electrode (122) on the second engraved structure (140).
5. thin film transistor (TFT) according to claim 4, which is characterized in that the source electrode (121) is with grid (110) vertical
In having the first overlapping region (S1) on the transparent substrate (100) direction, the drain electrode (122) is with grid (110) vertical
In on the transparent substrate (100) direction have the second overlapping region (S2)；Second engraved structure (140) includes that setting exists
Third pierced pattern (141) in first overlapping region (S1) and be arranged in second overlapping region (S2) the 4th
Pierced pattern (142).
6. thin film transistor (TFT) according to claim 1, which is characterized in that the engraved structure is to be arranged in the grid
(110) the second engraved structure of the first engraved structure (130) and setting on the source electrode (121), the drain electrode (122) on
(140)。
7. thin film transistor (TFT) according to claim 6, which is characterized in that the grid (110) is with source electrode (121) vertical
In having the first overlapping region (S1) on the transparent substrate (100) direction, the grid (110) is with drain electrode (122) vertical
In on the transparent substrate (100) direction have the second overlapping region (S2)；First engraved structure (130) includes that setting exists
The first pierced pattern (131) in first overlapping region (S1) and be arranged in second overlapping region (S2) second
Pierced pattern (132)；Second engraved structure (140) includes the third hollow out being arranged in first overlapping region (S1)
Pattern (141) and the 4th pierced pattern (142) being arranged in second overlapping region (S2).
8. thin film transistor (TFT) according to claim 7, which is characterized in that first engraved structure (130) and described
Two engraved structures (140) are more than first overlapping region in the overlapping area on the transparent substrate (100) direction
(S1) and the gross area of second overlapping region (S2) 80% or more.
9. a kind of array substrate, the array substrate includes multi-strip scanning line and multiple data lines, the multi-strip scanning line and institute
It states multiple data lines and intersects and limit multiple pixel units, each pixel unit includes pixel electrode, which is characterized in that institute
It further includes such as claim 1 to 8 any one of them thin film transistor (TFT), the grid of the thin film transistor (TFT) to state each pixel unit
(110) it is connected with corresponding scan line, the drain electrode (122) of the thin film transistor (TFT) is connect with the pixel electrode.
10. a kind of display device, which is characterized in that including array substrate as claimed in claim 9.
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| CN201810349168.1A CN108598155A (en) | 2018-04-18 | 2018-04-18 | Thin film transistor (TFT), array substrate and display device |
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| CN201810349168.1A CN108598155A (en) | 2018-04-18 | 2018-04-18 | Thin film transistor (TFT), array substrate and display device |
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| CN110047853A (en) * | 2019-05-06 | 2019-07-23 | 合肥鑫晟光电科技有限公司 | A kind of array substrate, display panel and display device |
| WO2020103191A1 (en) * | 2018-11-21 | 2020-05-28 | 惠科股份有限公司 | Array substrate and display panel |
| WO2022233075A1 (en) * | 2021-05-07 | 2022-11-10 | 惠州华星光电显示有限公司 | Thin-film transistor device, backlight module, and display panel |
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| CN205229635U (en) * | 2015-12-18 | 2016-05-11 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
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| CN104393004A (en) * | 2014-11-14 | 2015-03-04 | 深圳市华星光电技术有限公司 | Liquid crystal display and array substrate thereof |
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| WO2020103191A1 (en) * | 2018-11-21 | 2020-05-28 | 惠科股份有限公司 | Array substrate and display panel |
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| CN110047853B (en) * | 2019-05-06 | 2021-04-13 | 合肥鑫晟光电科技有限公司 | Array substrate, display panel and display device |
| WO2022233075A1 (en) * | 2021-05-07 | 2022-11-10 | 惠州华星光电显示有限公司 | Thin-film transistor device, backlight module, and display panel |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
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