CN102081269A - Transistor array substrate - Google Patents
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- CN102081269A CN102081269A CN201010545741XA CN201010545741A CN102081269A CN 102081269 A CN102081269 A CN 102081269A CN 201010545741X A CN201010545741X A CN 201010545741XA CN 201010545741 A CN201010545741 A CN 201010545741A CN 102081269 A CN102081269 A CN 102081269A
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Abstract
The invention provides a transistor array substrate which comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel units. The scanning lines, the data lines and the pixel units are all arranged on the substrate. Each pixel unit comprises a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, a first storage capacitor and a second storage capacitor. The second transistors and the first transistors are electrically connected with the same scanning line and the same data line, and are connected in series. The first pixel electrodes are electrically connected with the first transistors, while the second pixel electrodes are electrically connected with the second transistors. The first storage capacitors are electrically connected with the first transistors and the second transistors while the second storage capacitors are electrically connected with the second transistors.
Description
Technical field
The invention relates to a kind of active assembly array substrate (active component array substrate), and particularly relevant for a kind of transistor (TFT) array substrate.
Background technology
[0002] (Liquid Crystal Display, LCD) in the technology, how solving colour cast is a very important problem at now wide-angle liquid crystal display.Specifically, so-called colour cast is meant that the color of the picture of LCD changes along with the change at visual angle, the white partially situation of picture can occur when causing display frame to increase at the visual angle.In order to solve this colour cast problem, two kinds of methods of improving colour cast have been proposed at present.
A kind of method is coupling capacitance of many making in single pixel cell.This coupling capacitance is utilized the effect of voltage coupling, and (pixel electrode can provide the electric fields of different sizes to make the interior pixel electrode of single pixel cell.By this, produce different Liquid Crystal Molecules Alignment, impel pixel cell to show different GTGs, to improve the colour cast problem.Yet this coupling capacitance easily is affected because of the change of process parameter, so that can't accurately control the electric field of pixel electrode, and then the image quality of LCD is caused bad influence.
Another kind method is to increase a transistor in single pixel cell, can have two transistors in the promptly single pixel cell.By these two transistors, allow pixel electrode in the single pixel cell that the electric fields of different sizes are provided, to reach the effect of improving colour cast.Yet, this practice need be made a large amount of sweep trace (scan line), and each bar sweep trace must import the signal of independent waveform, so manufacturing process is very complicated, and must cooperate customized driving circuit (driver IC), thereby significantly increase cost of manufacture.
Summary of the invention
The invention provides a kind of transistor (TFT) array substrate, solving above-mentioned colour cast problem, and then promote the display quality of LCD.
In order to achieve the above object, the present invention proposes a kind of transistor (TFT) array substrate, and it comprises a substrate, multi-strip scanning line, many data lines (data line) and a plurality of pixel cell.These sweep traces, these data lines and these pixel cells all are disposed on the substrate.Each pixel cell comprises a first transistor, a transistor seconds, one first pixel electrode, one second pixel electrode, one first storage capacitors (first storage capacitor) and one second storage capacitors.Transistor seconds and the first transistor electrically connect same sweep trace and same data line, and transistor seconds is connected with the first transistor.First pixel electrode electrically connects the first transistor, and second pixel electrode electrically connects transistor seconds.First storage capacitors electrically connects the first transistor and transistor seconds, and second storage capacitors electrically connects transistor seconds.
In an embodiment of the present invention, each the first transistor comprises a first grid (first gate), one first source electrode (first source) and one first drain electrode (first drain), and each transistor seconds comprises a second grid, one second source electrode and one second drain electrode.In each pixel cell, first grid and second grid electrically connect same sweep trace, first source electrode electrically connects data line, and first drain electrode electrically connects second source electrode, first storage capacitors and first pixel electrode, and second drain electrode electrically connects second storage capacitors and second pixel electrode.
In an embodiment of the present invention, above-mentioned transistor (TFT) array substrate also comprises many common lines (common line), wherein these common lines electrically connect these first storage capacitors and these second storage capacitors, and these first storage capacitors and these second storage capacitors are all a plurality of storage capacitors (Cst on common) of framework on these common lines.
In an embodiment of the present invention, wherein a sweep trace between adjacent two common lines.Wherein a common line electrically connects first storage capacitors, and another common line electrically connects second storage capacitors.
In an embodiment of the present invention, first storage capacitors in the same pixel cell and second storage capacitors electrically connect same common line.
In an embodiment of the present invention, first pixel electrode and second pixel electrode in each pixel cell forms a line along data line.
In an embodiment of the present invention, first pixel electrode and second pixel electrode in each pixel cell forms a line along sweep trace.
In an embodiment of the present invention, the passage breadth length ratio of each the first transistor is different from the passage breadth length ratio of each transistor seconds.
In an embodiment of the present invention, the passage breadth length ratio of each the first transistor is greater than the passage breadth length ratio of each transistor seconds.
In an embodiment of the present invention, the area of each first pixel electrode is different from the area of each second pixel electrode.
In an embodiment of the present invention, the area of each first pixel electrode is less than the area of each second pixel electrode.
In an embodiment of the present invention, the capacitance of each first storage capacitors is different from the capacitance of each second storage capacitors.
In an embodiment of the present invention, the capacitance of each first storage capacitors is less than the capacitance of each second storage capacitors.
Based on above-mentioned, the first transistor and transistor seconds by each pixel cell, the present invention can utilize the capacitance partial pressure principle, allow first pixel electrode and second pixel electrode each self-corresponding liquid crystal capacitance (liquid crystal capacitor) produce different feed-trough voltages (feed-through voltage), and then reach the effect of eliminating colour cast.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A is the schematic top plan view of the transistor (TFT) array substrate of first embodiment of the invention.
Figure 1B is the circuit diagram of the display panels of the transistor (TFT) array substrate among a kind of Figure 1A of having.
Fig. 2 is the schematic top plan view of the transistor (TFT) array substrate of second embodiment of the invention.
Fig. 3 is the schematic top plan view of the transistor (TFT) array substrate of third embodiment of the invention.
Fig. 4 is the schematic top plan view of the transistor (TFT) array substrate of fourth embodiment of the invention.
Embodiment
Enforcement means of the present invention mainly are two pixel electrodes of design in single pixel cell, and utilize the capacitance partial pressure principle, allow each self-corresponding liquid crystal capacitance of these two pixel electrodes institute produce different feed-trough voltages, and then the elimination colour cast.In detail, pixel electrode can receive the source electrode input signal earlier, so that liquid crystal capacitance is charged.Then, the source electrode input signal suspends output, allows liquid crystal capacitance begin discharge.At this moment, the first rapid drawdown of the voltage of pixel electrode meeting just can slowly descend afterwards, and the pressure reduction of above-mentioned this section rapid drawdown is called feed-trough voltage.
Hold above-mentioned, stop output at the source electrode input signal, and after the voltage dip of pixel electrode, this moment, these pixel electrodes can be provided for changing the pixel voltage of Liquid Crystal Molecules Alignment, and wherein this pixel voltage voltage of approximating the source electrode input signal is basically deducted the voltage after the feed-trough voltage.Because the feed-trough voltage that these liquid crystal capacitances produced is also inequality,, shows two kinds of different GTGs to impel single pixel cell, and then solve the colour cast problem so these pixel electrodes in the same pixel cell can produce different pixel voltages separately.
Particularly, see also Figure 1A, it is the schematic top plan view of the transistor (TFT) array substrate of first embodiment of the invention.The transistor (TFT) array substrate 100 of first embodiment can with a colored optical filtering substrates (color filter substrate, do not illustrate) assembling, and between transistor (TFT) array substrate 100 and colored optical filtering substrates, insert liquid crystal material, to form a display panels (LCD Panel does not illustrate).Transistor (TFT) array substrate 100 comprises a substrate 110, multi-strip scanning line 120s, many data line 120d, many common line 120c and a plurality of pixel cell 130.
Hold above-mentioned, these sweep traces 120s, data line 120d, common line 120c and pixel cell 130 all are disposed on the substrate 110, and each pixel cell 130 comprises a first transistor 131, a transistor seconds 132, one first pixel electrode 133, one second pixel electrode 134, one first storage capacitors 135 and one second storage capacitors 136, wherein first pixel electrode 133 in each pixel cell 130 and second pixel electrode 134 can form a line along data line 120d, shown in Figure 1A.
The first transistor 131 in the same pixel cell 130 all electrically connects same sweep trace 120s and same data line 120d with transistor seconds 132.Specifically, these the first transistors 131 are all field-effect transistor (Field-Effect Transistor with transistor seconds 132, FET), so each the first transistor 131 comprises a first grid G1, one first source S 1 and one first drain D 1, and each transistor seconds 132 comprises a second grid G2, one second source S 2 and one second drain D 2.
Figure 1B is the circuit diagram of the display panels of the transistor (TFT) array substrate among a kind of Figure 1A of having.See also Figure 1A and Figure 1B, display panels 10 comprises transistor (TFT) array substrate 100, and sweep trace 120s electrically connects a grid power supply Vg1, and the grid input signal that is provided by grid power supply Vg1 is provided, and wherein grid power supply Vg1 for example is grid-driving integrated circuit (Gate IC).In each pixel cell 130, first grid G1 and second grid G2 electrically connect same sweep trace 120s, thus the first transistor 131 and transistor seconds 132 the two can use same group of grid input signal.Therefore, the first transistor 131 in the same pixel cell 130 can be opened simultaneously and close basically with transistor seconds 132 by a sweep trace 120s.
In addition, first drain D 1 also electrically connects first storage capacitors 135 and first pixel electrode 133, and second drain D 2 also electrically connects second storage capacitors 136 and second pixel electrode 134, so first pixel electrode 133 and first storage capacitors 135 electrically connect the first transistor 131, and second pixel electrode 134 and second storage capacitors 136 electrically connect transistor seconds 132.In addition, second source S 2 also electrically connects first pixel electrode 133, and therefore first pixel electrode 133 and second pixel electrode 134 are to electrically connect mutually with transistor seconds 132.
Because first drain D 1 electrically connects first storage capacitors 135, first pixel electrode 133 and second drain D 2, second drain D 2 electrically connects second storage capacitors 136 and second pixel electrode 134, add that the first transistor 131 and transistor seconds 132 use same group of grid input signal and source electrode input signal, therefore from data line 120d and the source electrode input signal that comes can be passed to first pixel electrode 133 and second pixel electrode 134, and liquid crystal capacitance Clc1, Clc2, first storage capacitors 135 and second storage capacitors 136 are charged.
These common line 120c electrically connect these first storage capacitors 135 and second storage capacitors 136, and first storage capacitors 135 and second storage capacitors 136 are all a plurality of storage capacitors of framework on these common line 120c.Each pixel cell 130 can electrically connect two common line 120c, and wherein a common line 120c electrically connects first storage capacitors 135, and another common line 120c electrically connects second storage capacitors 136.So, these common line 120c can transmit common electrode signal Vc1 to liquid crystal capacitance Clc1, Clc2, first storage capacitors 135 and second storage capacitors 136.In addition, wherein a sweep trace 120s can be between adjacent two common line 120c.
In the operation of display panels 10, when the grid input signal that comes from sweep trace 120s is opened the first transistor 131 with transistor seconds 132, source electrode input signal from data line 120d can be passed to first pixel electrode 133 and second pixel electrode 134, and liquid crystal capacitance Clc1, Clc2, first storage capacitors 135 and second storage capacitors 136 are charged.When the grid input signal that comes from sweep trace 120s was closed the first transistor 131 with transistor seconds 132, liquid crystal capacitance Clc1, Clc2 utilized the capacitance partial pressure principle to produce different feed-trough voltages respectively.
Specifically, in the technology of known LCD, feed-trough voltage satisfies following formula (1):
Wherein △ Vp is a feed-trough voltage, and Cgd is the capacitance between interior transistorized grid of pixel cell and the drain electrode, and Clc is the capacitance of liquid crystal capacitance, and Cs is the capacitance of storage capacitors.Vgh and Vgl represent the high voltage and the low-voltage of grid input signal respectively, and wherein Vgh is the magnitude of voltage of grid input signal when turn-on transistor, and Vgl is the magnitude of voltage of finger grid input signal when closing transistor.
From Figure 1B, single with regard to first pixel electrode 133, because the electric capacity that is connected with sweep trace 120s is the electric capacity between first grid G1 and first drain D 1 in the first transistor 131, and the electric capacity between second grid G2 and second source S 2 in the transistor seconds 132, therefore according to formula (1), the feed-trough voltage △ Vp1 that liquid crystal capacitance Clc1 is produced satisfies following formula (2):
Wherein Cgd1 is the capacitance between first grid G1 and first drain D 1 in the first transistor 131, Cgs2 is the capacitance between second grid G2 and second source S 2 in the transistor seconds 132, Clc1 is the capacitance of liquid crystal capacitance Clc1, and Cs1 is the capacitance of first storage capacitors 135.Vgh is the magnitude of voltage of grid input signal when opening the first transistor 131 with transistor seconds 132, and Vgl is the magnitude of voltage of grid input signal when closing the first transistor 131 with transistor seconds 132.From formula (2), can find that the Cgd in the original formula (1) changes (Cgd1+Cgs2) into.
In like manner, single with regard to second pixel electrode 134, because the electric capacity that is connected with sweep trace 120s only is the electric capacity between the second grid G2 and second drain D 2 in the transistor seconds 132, therefore according to formula (1), the feed-trough voltage △ Vp2 that liquid crystal capacitance Clc2 is produced satisfies following formula (3):
Wherein Cgd2 is the capacitance between second grid G2 and second drain D 2 in the transistor seconds 132, and Clc2 is the capacitance of liquid crystal capacitance Clc2, and Cs2 is the capacitance of second storage capacitors 136.From formula (3), can find that the Cgd in the original formula (1) has changed Cgd2 into.
Learn by formula (2) and formula (3), capacitance, the capacitance of first storage capacitors 135, the capacitance of second storage capacitors 136 and the capacitance of liquid crystal capacitance Clc1, Clc2 by between capacitance, second grid G2 and second drain D 2 between capacitance, second grid G2 and second source S 2 adjusted between the first grid G1 and first drain D 1 can make liquid crystal capacitance Clc1, Clc2 produce different feed-trough voltage △ Vp1 and △ Vp2 respectively.So, each pixel cell 130 can show two kinds of different GTGs, to solve the colour cast problem.
About utilizing above-mentioned capacitance to produce the method for different feed-trough voltage △ Vp1, △ Vp2, the present invention has multiple enforcement means, and for example first embodiment controls feed-trough voltage △ Vp1 and △ Vp2 through capacitance between capacitance, second grid G2 and second source S 2 adjusted between the first grid G1 and first drain D 1 and the capacitance between the second grid G2 and second drain D 2.
See also Figure 1A, the passage breadth length ratio of each the first transistor 131 is different from the passage breadth length ratio of each transistor seconds 132, and wherein the channel breadth length ratio is the ratio of channel width and channel length.For example, from Figure 1A, the passage length of the passage length of the first transistor 131 and transistor seconds 132 is roughly the same, but the channel width of the first transistor 131 is but greater than the channel width of transistor seconds 132, therefore the passage breadth length ratio of each the first transistor 131 can be greater than the passage breadth length ratio of each transistor seconds 132, to such an extent as to the capacitance between the second grid G2 and second drain D 2, and the capacitance between the second grid G2 and second source S 2 is all less than the capacitance between the first grid G1 and first drain D 1.
Hold above-mentioned, according to formula (2) and formula (3), identical at the two capacitance of liquid crystal capacitance Clc1, Clc2, and under first storage capacitors 135 prerequisite identical with second storage capacitors, 136 the two capacitance, feed-trough voltage △ Vp1 can be greater than feed-trough voltage △ Vp2.So, pixel cell 130 can show two kinds of different GTGs, to eliminate colour cast.
In addition, what must illustrate is, though in first embodiment, the passage breadth length ratio of the first transistor 131 is greater than the passage breadth length ratio of transistor seconds 132, but in other embodiments, even the passage breadth length ratio of the first transistor 131 is less than the passage breadth length ratio of transistor seconds 132, pixel cell 130 still can show two kinds of different GTGs, to reach the effect of eliminating colour cast.Therefore, the first transistor shown in Figure 1A 131 and transistor seconds 132 are only for illustrating, and non-limiting the present invention.
Except adjusting the first transistor 131 and transistor seconds 132 the two passage breadth length ratio, the present invention also can see through and adjust liquid crystal capacitance Clc1, the two capacitance of Clc2 is controlled feed-trough voltage △ Vp1 and △ Vp2.Specifically, see also Fig. 2, it is the schematic top plan view of the transistor (TFT) array substrate of second embodiment of the invention, wherein the transistor (TFT) array substrate 200 of second embodiment is similar to the transistor (TFT) array substrate 100 of first embodiment, for example transistor (TFT) array substrate 200 also can by with the assembling of colored optical filtering substrates (not illustrating) and inserting of liquid crystal material, form display panels (not illustrating).Therefore, first embodiment and the two something in common of second embodiment be repeated description no longer, below only introduces the two difference.
In a second embodiment, the area of each first pixel electrode 233 is different from the area of each second pixel electrode 234.Specifically,, can learn that the area of each first pixel electrode 233 is less than the area of each second pixel electrode 234 from Fig. 2.After formation one has the display panels of transistor (TFT) array substrate 200, because the area of first pixel electrode 233 is less than the area of second pixel electrode 234, therefore first pixel electrode, 233 pairing liquid crystal capacitances also can be less than second pixel electrode, 234 pairing liquid crystal capacitances.
In Fig. 2, first storage capacitors 135 is identical with second storage capacitors, 136 the two capacitance, and the first transistor 231 is similar to the first transistor 131 of first embodiment, only the first transistor 231 is identical with transistor seconds 132 the two passage breadth length ratio, therefore according to formula (2) and formula (3), less than second pixel electrode, 234 pairing liquid crystal capacitances, the feed-trough voltage of first pixel electrode 233 can be greater than the feed-trough voltage of second pixel electrode 234 based on first pixel electrode, 233 pairing liquid crystal capacitances.So, each pixel cell 230 of transistor (TFT) array substrate 200 also can show two kinds of different GTGs, and then reaches the effect of eliminating colour cast.
In addition, what must illustrate is, though in a second embodiment, the area of first pixel electrode 233 is less than the area of second pixel electrode 234, but in other embodiments, even the area of first pixel electrode 233 is greater than the area of second pixel electrode 234, pixel cell 230 still can show two kinds of different GTGs.Therefore, the size of first pixel electrode 233 shown in Figure 2 and second pixel electrode, 234 the two area is only for illustrating, and non-limiting the present invention.
Except the mode of above first and second embodiment described control feed-trough voltage △ Vp1 and △ Vp2, the present invention also can see through adjustment first storage capacitors and second storage capacitors the two capacitance Cs1, Cs2 control feed-trough voltage △ Vp1 and △ Vp2.Specifically, see also Fig. 3, it is the schematic top plan view of the transistor (TFT) array substrate of third embodiment of the invention, wherein the transistor (TFT) array substrate 300 of the 3rd embodiment is similar to the transistor (TFT) array substrate 100,200 of previous embodiment, so transistor (TFT) array substrate 300 also can by with the assembling of colored optical filtering substrates (not illustrating) and inserting of liquid crystal material, form display panels (not illustrating).Therefore, the 3rd embodiment and previous embodiment something in common be repeated description no longer, below only introduces difference between the 3rd embodiment and the previous embodiment.
In the 3rd embodiment, the capacitance of each first storage capacitors 135 is different from the capacitance of each second storage capacitors 336.Specifically, from Fig. 3, can learn, each first storage capacitors 135 at area occupied on the substrate 110 less than each second storage capacitors 336 occupied area on substrate 110, to such an extent as to the capacitance of each first storage capacitors 135 can be less than the capacitance of each second storage capacitors 336.
Hold above-mentioned, according to formula (2) and formula (3), first pixel electrode 133 in Fig. 3 is identical with second pixel electrode, 134 the two area, and under the first transistor 231 prerequisite identical with transistor seconds 132 the two passage breadth length ratio, the feed-trough voltage of first pixel electrode 133 can be greater than the feed-trough voltage of second pixel electrode 134.So, each pixel cell 330 of transistor (TFT) array substrate 300 also can show two kinds of different GTGs, and then eliminates colour cast.
In addition, what must illustrate is, though in the 3rd embodiment, the capacitance of first storage capacitors 135 is less than the capacitance of second storage capacitors 336, but in other embodiments, even the capacitance of first storage capacitors 135 is greater than the capacitance of second storage capacitors 336, pixel cell 330 still can show two kinds of different GTGs.Therefore, first storage capacitors 135 shown in Figure 3 and second storage capacitors 336 are only for illustrating, and non-limiting the present invention.
Fig. 4 is the schematic top plan view of the transistor (TFT) array substrate of fourth embodiment of the invention.See also Fig. 4, the transistor (TFT) array substrate 400 of the 4th embodiment is similar to the transistor (TFT) array substrate 100 of first embodiment, and the two circuit structure is identical.Specifically, transistor (TFT) array substrate 400 comprises a substrate 110, multi-strip scanning line 120s, many data line 120d, many common line 120c and a plurality of pixel cell 430, and each pixel cell 430 comprises a first transistor 431, a transistor seconds 432, one first pixel electrode 433, one second pixel electrode 434, one first storage capacitors 435 and one second storage capacitors 436, and wherein sweep trace 120s, data line 120d, common line 120c and pixel cell 430 all are disposed on the substrate 110.
The first transistor 431 is all field-effect transistor with transistor seconds 432, so each the first transistor 431 comprises a first grid G3, one first source S 3 and one first drain D 3, and each transistor seconds 432 comprises a second grid G4, one second source S 4 and one second drain D 4.Pixel cell 430 electrically connects sweep trace 120s and data line 120d, and wherein the electric connection mode is identical with first embodiment between the three.
In detail, in each pixel cell 430, first grid G3 and second grid G4 electrically connect same sweep trace 120s, and first source S 3 electrically connects data line 120d.First drain D 3 electrically connects second source S 4, first storage capacitors 435 and first pixel electrode 433, and second drain D 4 electrically connects second storage capacitors 436 and second pixel electrode 434.In addition, the means that transistor (TFT) array substrate 400 is eliminated colour casts are identical with previous embodiment, therefore how to eliminate the means of colour cast about transistor (TFT) array substrate 400, below repeated description no longer.
Yet transistor (TFT) array substrate 400 and 100 still has difference between the two, and it mainly is: the arrangement difference of the two pixel cell.Specifically, in the 4th embodiment, first pixel electrode 433 and second pixel electrode 434 in each pixel cell 430 form a line along data line 120d.Be different from vertical arrangement that first pixel electrode 133 and second pixel electrode 134 are presented among first embodiment, first pixel electrode 433 of present embodiment and second pixel electrode 434 be present transversely arranged.In addition, in same pixel cell 430, first storage capacitors 435 and second storage capacitors 436 can electrically connect same common line 120c, as shown in Figure 4.
In sum, the present invention utilizes the capacitance partial pressure principle, and see through capacitance, the capacitance of first storage capacitors, the capacitance of second storage capacitors and the capacitance of first pixel electrode and second the two each self-corresponding liquid crystal capacitance of pixel electrode between capacitance, second grid and second drain electrode between capacitance, second grid and second source electrode of adjusting between the first grid and first drain electrode, can produce different feed-trough voltages respectively at first pixel electrode and second pixel electrode.So, each pixel cell can show two kinds of different GTGs, and then solves the colour cast problem.
Compared to prior art, the present invention is not vulnerable to the influence of process parameter, thereby has preferable voltage accuracy, and can comparatively accurately control the electric field of pixel electrode, avoids the image quality of LCD is exerted an adverse impact.Secondly, though the present invention adopts two transistors (being first, second transistor) in single pixel cell, not needing increases the multi-strip scanning line as the picture prior art, and also do not need to import the signal of independent waveform, so the customized driving circuit of must not arranging in pairs or groups.Hence one can see that, and transistor (TFT) array substrate of the present invention has the advantage that manufacturing process is simple and reduce cost of manufacture.
In addition, transistor (TFT) array substrate of the present invention can adopt existing display panels processing procedure to make substantially, and transistor (TFT) array substrate processing procedure of the present invention is similar to the processing procedure of present transistor (TFT) array substrate, therefore transistor (TFT) array substrate of the present invention does not need significantly to change the manufacturing equipment and the manufacturing process of existing transistor (TFT) array substrate on making.So, transistor (TFT) array substrate of the present invention can be continued to use existing manufacturing equipment and manufacturing process is made, and saves the expense of the equipment of additionally buying more.
Though the present invention with preferred embodiment openly as above, so it is not in order to limiting the present invention, anyly has the knack of alike skill person, and without departing from the spirit and scope of the present invention, institute does to change and the equivalence replacement of retouching, and still is in the scope of patent protection of the present invention.
Claims (13)
1. a transistor (TFT) array substrate is characterized in that, comprising:
One substrate;
The multi-strip scanning line is disposed on this substrate;
Many data lines are disposed on this substrate;
A plurality of pixel cells be disposed on this substrate, and respectively this pixel cell comprise:
One the first transistor;
One transistor seconds electrically connect same sweep trace and same data line with this first transistor, and this transistor seconds is connected with this first transistor;
One first pixel electrode electrically connects this first transistor;
One second pixel electrode electrically connects this transistor seconds;
One first storage capacitors electrically connects this first transistor and this transistor seconds; And
One second storage capacitors electrically connects this transistor seconds.
2. transistor (TFT) array substrate as claimed in claim 1, it is characterized in that, respectively this first transistor comprises a first grid, one first source electrode and one first drain electrode, and respectively this transistor seconds comprises a second grid, one second source electrode and one second drain electrode, in this pixel cell respectively, this first grid and this second grid electrically connect same sweep trace, this first source electrode electrically connects this data line, this first drain electrode electrically connects this second source electrode, this first storage capacitors and this first pixel electrode, and this second drain electrode electrically connects this second storage capacitors and this second pixel electrode.
3. transistor (TFT) array substrate as claimed in claim 1, it is characterized in that, also comprise many common lines, wherein those common lines electrically connect those first storage capacitors and those second storage capacitors, and those first storage capacitors and those second storage capacitors are all a plurality of storage capacitors of framework on those common lines.
4. transistor (TFT) array substrate as claimed in claim 3 is characterized in that, a sweep trace is between adjacent two common lines, and wherein a common line electrically connects this first storage capacitors, and another common line electrically connects this second storage capacitors.
5. transistor (TFT) array substrate as claimed in claim 3 is characterized in that, this first storage capacitors in the same pixel cell and this second storage capacitors electrically connect same common line.
6. transistor (TFT) array substrate as claimed in claim 1 is characterized in that, respectively this first pixel electrode and this second pixel electrode in this pixel cell forms a line along this data line.
7. transistor (TFT) array substrate as claimed in claim 1 is characterized in that, respectively this first pixel electrode and this second pixel electrode in this pixel cell forms a line along this sweep trace.
8. transistor (TFT) array substrate as claimed in claim 1 is characterized in that, respectively the passage breadth length ratio of this first transistor is different from the respectively passage breadth length ratio of this transistor seconds.
9. transistor (TFT) array substrate as claimed in claim 8 is characterized in that, respectively the passage breadth length ratio of this first transistor is greater than the passage breadth length ratio of this transistor seconds respectively.
10. transistor (TFT) array substrate as claimed in claim 1 is characterized in that, respectively the area of this first pixel electrode is different from the respectively area of this second pixel electrode.
11. transistor (TFT) array substrate as claimed in claim 10 is characterized in that, respectively the area of this first pixel electrode is less than the area of this second pixel electrode respectively.
12. transistor (TFT) array substrate as claimed in claim 1 is characterized in that, respectively the capacitance of this first storage capacitors is different from the respectively capacitance of this second storage capacitors.
13. transistor (TFT) array substrate as claimed in claim 12 is characterized in that, respectively the capacitance of this first storage capacitors is less than the capacitance of this second storage capacitors respectively.
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| CN102967977A (en) * | 2012-10-08 | 2013-03-13 | 友达光电股份有限公司 | Pixel array substrate |
| CN103353697A (en) * | 2013-07-19 | 2013-10-16 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN103676383A (en) * | 2013-12-27 | 2014-03-26 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display method with 2D display mode and D display mode compatible |
| CN103984173A (en) * | 2014-03-26 | 2014-08-13 | 友达光电股份有限公司 | Pixel structure |
| CN104267554A (en) * | 2014-10-14 | 2015-01-07 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN104834142A (en) * | 2015-06-03 | 2015-08-12 | 合肥鑫晟光电科技有限公司 | Pixel structure, array substrate and display device |
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| KR101789947B1 (en) | 2013-07-26 | 2017-10-25 | 센젠 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Array substrate and liquid crystal display panel |
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| CN108363246A (en) * | 2018-02-26 | 2018-08-03 | 惠科股份有限公司 | Display panel and curved surface display device |
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