CN104393004A - Liquid crystal display and array substrate thereof - Google Patents
Liquid crystal display and array substrate thereof Download PDFInfo
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- CN104393004A CN104393004A CN201410650057.6A CN201410650057A CN104393004A CN 104393004 A CN104393004 A CN 104393004A CN 201410650057 A CN201410650057 A CN 201410650057A CN 104393004 A CN104393004 A CN 104393004A
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- drain electrode
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- base palte
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a liquid crystal display and an array substrate thereof, belongs to the technical field of display, and aims at effectively solving the problem that a drain electrode and a source electrode cannot be accurately aligned during manufacturing the array substrate to cause the change on the stray capacitance Cgs of a sub-pixel. The array substrate comprises a plurality of sub-pixel units which are arranged in an array form; each sub-pixel unit comprises a thin film transistor and a pixel electrode; each thin film transistor comprises a grid electrode, and a drain electrode connected with each pixel electrode; a hollow areas is formed by each grid electrode and is correspondingly arranged at one end of each drain electrode, far from each pixel electrode; the end part of each drain electrode is positioned into each hollow area. The array substrate can be applied to a liquid crystal television, the liquid crystal display, a mobile phone, a tablet personal computer and other display devices.
Description
Technical field
The present invention relates to Display Technique field, specifically, relate to a kind of liquid crystal display and array base palte thereof.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, be called for short TFT-LCD) be current main flow display unit, the pixel cell that its viewing area is generally repeated by up to a million forms, and a pixel cell is generally made up of red, green, blue three sub-pixel unit.The structure of sub-pixel unit as shown in Figure 1, primarily of compositions such as grid line 1, data wire 2, TFT, pixel electrode 3, public electrode wires 4, wherein, TFT is comprised grid 5 (being connected with grid line 1), active layer 6, source electrode 7 (being connected with data wire 2) from the bottom to top successively and drained for 8 (being connected with pixel electrode 3 by conductive hole 9).
Concrete, this sub-pixel unit can be equivalent to the equivalent circuit diagram shown in Fig. 2.As shown in Figure 2, the main composition electric capacity of the structure of this sub-pixel unit comprises storage capacitance C
st, liquid crystal capacitance C
lcwith parasitic capacitance C
gsdeng.Wherein, storage capacitance C
stbe made up of pixel electrode 3 and the public electrode wire 4 be positioned on array base palte, liquid crystal capacitance C
lcthen be made up of the public electrode on pixel electrode 3 and color membrane substrates.
When TFT-LCD work, grid line 1 is powered for grid 5, and grid 5 applies voltage and makes TFT conducting, and the data-signal that data wire 2 carries is transferred to pixel electrode 3 via source electrode 7, active layer 6 and drain electrode 8.By inputting different data-signals toward data wire 2, thus control liquid crystal capacitance C
lcthe voltage at two ends.Liquid crystal capacitance C
lcthe voltage at two ends is different, and the yawing moment of the liquid crystal between array base palte and color membrane substrates can be different, and the photoconduction passband of sub-pixel also can change thereupon, the final display brightness realizing each sub-pixel of control.
In addition, in Pixel Design, some parasitic capacitances are inevitably introduced.Wherein, as shown in Figure 2, the drain electrode 8 of TFT and grid 5 overlapping causing form parasitic capacitance C
gs, this parasitic capacitance C
gslarger on the display quality impact of TFT-LCD.Further, Fig. 3 be in the equivalent electric circuit shown in Fig. 2, the output waveform figure of the signal such as grid line 1 voltage and pixel electrode 3 voltage.As can be seen from Fig. 3: at the trailing edge of grid line 1 signal, due to parasitic capacitance C
gsexistence, pixel electrode 3 voltage meeting and input data-signal between voltage difference delta V, its size can be calculated by following formula:
Wherein, the Δ V in above formula
gfor the high voltage of grid line 1 signal and the difference of low-voltage.Above-mentioned phenomenon is called Feed-through effect.
Due to the existence of Feed-through effect, in the process of sub-pixel design, technical staff can by the electric design automation of some advanced persons (Electronic Design Automation, being called for short EDA) instrument carries out board design to sub-pixel, such as shown in Figure 3, best public electrode voltages (the Best V of sub-pixel is set
com).But in the manufacture process of array base palte, usually need several roads film formation process, in every procedure, all relate to the problem of contraposition.If therefore in the fabrication process, be arranged in the data wire 2 on upper strata, source electrode 7 and structure such as drain electrode 8 etc. and the bit errors being positioned at the positive and negative x directions of structure generation Fig. 1 such as the grid 5 of lower floor and grid line 1, cause each Rotating fields contraposition not accurate, the each electric capacity originally set making this sub-pixel changes, and the performance of sub-pixel also can change.If parasitic capacitance C
gsthere occurs change, the best common electric voltage of sub-pixel of original setting will be no longer applicable, by abnormal for the TFT-LCD display frame causing making, increase the weight of the bad phenomenon such as ghost (Image Stacking is called for short IS).
Summary of the invention
The present invention proposes a kind of liquid crystal display and array base palte thereof, efficiently solves in the process of manufacturing array substrate, because drain and gate contraposition is forbidden, makes the parasitic capacitance C of sub-pixel
gsthe problem changed.
First aspect present invention provides a kind of array base palte, comprises the sub-pixel unit of multiple array arrangement, and each sub-pixel unit comprises thin-film transistor and pixel electrode, and described thin-film transistor comprises grid and the drain electrode being connected pixel electrode;
Wherein, described grid is formed with void region, and the correspondence drain electrode of described void region is arranged away from one end of described pixel electrode, and the end of described drain electrode is arranged in described void region.
Further, described void region is circular, polygon or irregularly shaped.
Further, described void region is square.
Further, the length of described void region is 4 ~ 6 microns.
Further, larger than the width of described drain electrode 2 ~ 6 microns of the width of described void region.
Further, described thin-film transistor also comprises the active layer between described grid and described drain electrode.
Further, described active layer comprises amorphous silicon layer and N-type doped amorphous silicon layer.
Further, the corresponding described drain electrode of described N-type doped amorphous silicon layer is arranged.
Further, described array base palte is applicable to the liquid crystal display of more than 24 inches.
Present invention offers following beneficial effect: the invention provides a kind of array base palte, this array base palte comprises the sub-pixel unit of multiple array arrangement, each sub-pixel unit comprises thin-film transistor and pixel electrode, and described thin-film transistor comprises grid and the drain electrode being connected pixel electrode; Wherein, described grid is formed with void region, and the correspondence drain electrode of described void region is arranged away from one end of described pixel electrode, and the end of described drain electrode is arranged in described void region.Void region be arranged so that in the aligning accuracy of preparation facilities, drain electrode and the relative area of grid can not change, and prevent the parasitic capacitance C formed with grid that drains
gscapacitance change, ensure that the finished product of this array base palte conforms to design, prevent the generation of the bad phenomenon such as TFT-LCD display frame exception, ghost being provided with this array base palte.
Second aspect present invention provides a kind of liquid crystal display, comprises above-mentioned array base palte.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in specification, claims and accompanying drawing and obtain.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, accompanying drawing required in describing is done simple introduction below to embodiment:
Fig. 1 is the schematic diagram of the structure of the sub-pixel unit that prior art provides;
Fig. 2 is the equivalent circuit diagram of Fig. 1;
Fig. 3 is the output waveform figure of Fig. 2;
Fig. 4 be the drain and gate contraposition in Fig. 1 accurate time cooperation schematic diagram;
The cooperation schematic diagram of Fig. 5 when to be drain electrode in Fig. 1 relative to grid the skew in x direction occurs;
The cooperation schematic diagram of Fig. 6 when to be drain electrode in Fig. 1 relative to grid the skew in-x direction occurs;
Fig. 7 is the schematic diagram of the structure of the sub-pixel unit that the embodiment of the present invention provides;
Fig. 8 be the drain and gate contraposition in Fig. 7 accurate time cooperation schematic diagram;
The cooperation schematic diagram of Fig. 9 when to be drain electrode in Fig. 7 relative to grid the skew in x direction occurs;
Figure 10 ~ Figure 12 is the schematic shapes of the void region in Fig. 7;
Figure 13 is the schematic diagram in the A-A cross section in Fig. 1;
Figure 14 is the schematic diagram in the B-B cross section in Fig. 7.
Description of reference numerals:
1-grid line; 2-data wire; 3-pixel electrode;
4-public electrode wire; 5-grid; 6-active layer;
7-source electrode; 8-drain electrode; 9-conductive hole;
10-void region; The end of 11-drain electrode; 12-underlay substrate;
13-gate insulator; 14-amorphous silicon layer; 15-N-type doped amorphous silicon layer;
16-passivation layer.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Embodiments provide a kind of array base palte, this array base palte comprises the sub-pixel unit of multiple array arrangement.As shown in Figure 7, each sub-pixel unit comprises thin-film transistor and pixel electrode 3, and thin-film transistor comprises grid 5 and the drain electrode 8 being connected pixel electrode 3.
Wherein, grid 5 is formed with void region 10, and void region 10 correspondence drain electrode 8 is arranged away from one end of pixel electrode 3, and the end 11 of drain electrode is arranged in void region 10.
Concrete, be illustrated in figure 1 existing sub-pixel structure.Can find out in Fig. 1, grid 5 and the drain electrode 8 of TFT partly overlap, and make to define parasitic capacitance C between grid 5 and drain electrode 8
gs.
In the preparation process of array base palte, carry out grid 5 and drain electrode 8 patterning processes between, need array base palte repeatedly to move.In preparation drain electrode 8 isostructural process, if contraposition is accurate between drain electrode 8 and grid 5, so actual produced sub-pixel structure by with technical staff design consistent, i.e. parasitic capacitance C
gsthat designs with technical staff is more or less the same.As shown in Figure 4, suppose that the contraposition of drain electrode 8 now and grid 5 is accurate, 8 are parallel to each other, relative area is S for grid 5 and drain electrode
1.
But be subject to the impact of the aligning accuracy of preparation facilities, in preparation process, the contraposition of drain electrode 8 and grid 5 is difficult to accurately, cause the position of drain electrode 8 and grid 5 usually to occur deviation.Suppose to there occurs between drain electrode 8 now and grid 5 the contraposition deviation in x direction (as shown in Figure 5) in Fig. 1 or-x direction (as shown in Figure 6), and the deviate of Fig. 5 and Fig. 6 is equal, is L.Drain electrode 8 then now in Fig. 4 and the relative area of grid 5 are S
1+ Δ S, the drain electrode 8 in Fig. 5 and the relative area of grid 5 are then S
1-Δ S, wherein Δ S=L × W, W are the width of drain electrode 8.
And according to parallel plate capacitor computing formula
known, the S in its Chinese style characterizes the relative area of two parallel-plate electrodes, and d characterizes the vertical range between two parallel-plate electrodes, and k is constant, and ε characterizes the dielectric dielectric constant between two parallel-plate electrodes.Obviously, vertical range between the drain electrode 8 of the grid 5 of Fig. 4, Fig. 5 and Fig. 6 is equal, dielectric (being active layer 6 and gate insulator 13) between grid 5 and drain electrode 8 remains unchanged, but the relative area between grid 5 and drain electrode 8 there occurs change, will cause parasitic capacitance C
gscapacitance (for Fig. 5) bigger than normal compared with design or (for Fig. 6) less than normal.
Therefore, if there occurs the contraposition deviation in x direction between grid 5 and drain electrode 8, the parasitic capacitance C that grid 5 and drain electrode 8 are formed
gscapacitance also will change, cause this parasitic capacitance C
gscapacitance no longer mate with the sub-pixel structure of designer's board design in advance, best common electric voltage etc., certainly will the display quality of this TFT-LCD be reduced.
And as shown in FIG. 7 and 8, in the technical scheme of the embodiment of the present invention, grid 5 is formed with void region 10, and this void region 10 is arranged with drain electrode 8 one end away from pixel electrode 3, makes the end 11 drained be arranged in void region 10.Be equivalent to drain electrode 8 all not relative with grid 5, thus reduce the parasitic capacitance C that drain electrode 8 and grid 5 formed
gscapacitance size.
It should be noted that, as shown in Figure 7, in embodiments of the present invention, the end 11 of drain electrode represents that drain electrode 8 and pixel electrode 3 are apart from Na Yichu farthest.
The more important thing is, the end 11 of this drain electrode is arranged in void region 10, the end 11 being equivalent to this drain electrode all has certain distance with each edge of void region 10, and the size and shape of void region 10 can according to the aligning accuracy design of preparation facilities (as produced board).Now, even if in the process of preparation drain electrode 8, there is the contraposition deviation in allowed band in preparation facilities (as produced board), the relative area of grid 5 and drain electrode 8 still can remain unchanged.
Concrete, as shown in Figure 8, when drain electrode 8 is accurate with grid 5 contraposition, the length in the region that drain electrode 8 is relative with grid 5 is L
1.If the deviation L ' in x direction occurs for drain electrode 8 and grid 5, as shown in Figure 9, obviously, drain electrode 8 remains unchanged with the relative area of grid 5.Because as shown in Figure 9, although drain electrode 8 there occurs the deviation in x direction relative to grid 5, cause drain electrode 8 to add Δ S '=L ' × W with the relative area of grid 5 more, but also make drain electrode 8 add Δ S '=L ' × W with the relative area of void region 10, the relative area that obviously drain electrode 8 and void region 10 increase has balanced out the relative area of the increase of drain 8 and grid 5 more.
Obviously, similar, occur-x direction, deviation in preparation facilities aligning accuracy allowed band time, drain electrode 8 still can remain unchanged with the relative area of grid 5.
In the technical scheme of the embodiment of the present invention, provide a kind of array base palte, this array base palte comprises the sub-pixel unit of multiple array arrangement, and each sub-pixel unit comprises thin-film transistor and pixel electrode, and thin-film transistor comprises grid and the drain electrode being connected pixel electrode; Wherein, grid is formed with void region, and void region correspondence drain electrode is arranged away from one end of pixel electrode, and the end of drain electrode is arranged in void region.Void region be arranged so that in the aligning accuracy of preparation facilities, drain electrode and the relative area of grid can not change, and prevent the parasitic capacitance C formed with grid that drains
gscapacitance change, ensure that the finished product of this array base palte conforms to design, prevent the generation of the bad phenomenon such as TFT-LCD display frame exception, ghost being provided with this array base palte.
Further, the void region 10 in the embodiment of the present invention can be arranged according to actual conditions, such as, as shown in Figure 10, Figure 11 and Figure 12, can be circle, polygon or irregularly shaped.But for the consideration of manufacture craft and the design factor such as easy, preferably, this void region 10 is square, as shown in Figure 8.
Discussed in the preceding article, in order to prevent in actual production process, the parasitic capacitance C that grid 5 and the contraposition deviation draining 8 cause
gswith presetting inconsistent, cause the appearance of the problems such as the bad display of this TFT-LCD.When grid 5 and drain electrode 8 contrapositions are accurate, end 11 and the two edges of void region 10 in the positive negative direction of x of drain electrode should have certain distance.Preferably, when this void region 10 is square, the length of void region 10 is 4 ~ 6 microns.Namely, when grid 5 is accurate with drain electrode 8 contrapositions, the distance between the two edges in the positive negative direction of x of the end 11 of drain electrode and void region 10 is 2 ~ 3 microns.This preset value meets the aligning accuracy of the preparation facilitiess such as production board conventional at present.Can ensure drain electrode 8 and grid 5 because of preparation facilities there is the contraposition deviation within the scope of the positive and negative directional precision of x time, the relative area between drain electrode 8 and grid 5 is constant.
Except the deviation of the positive negative direction of x, be subject to the impact of the aligning accuracy of producing the preparation facilitiess such as board, also likely there is the deviation of the positive negative direction perpendicular to x in grid 5 and drain electrode 8, the deviation of the positive negative direction of the y namely shown in Fig. 8.Obviously, if the width of void region 10 is too small, when occurring the deviation in y direction or-y direction, drain electrode 8 will be caused to reduce with the relative area of void region 10, and drain 8 with void region 10 by the relative area of metallic region of grid 5 increase.Obviously, now drain the 8 parasitic capacitance C formed with grid 5
gsthe large young pathbreaker of capacitance and not conforming to of Software for Design.
In order to prevent the appearance of this problem, in embodiments of the present invention, based on the aligning accuracy of conventional preparation facilities, larger than the width of drain electrode 82 ~ 6 microns of the width of this void region 10.When drain electrode 8 and grid 5 contraposition are accurate, drain electrode 8 is 1 ~ 3 micron to the distance of the corresponding edge of void region 10.Can ensure in the alignment precision range of preparation facilities, drain electrode 8 can not cause due to the skew in the positive negative direction of y changing with the relative area of grid 5.
Because the aligning accuracy of different preparation facilitiess is inconsistent, therefore, the size of the void region 10 of the grid 5 in the embodiment of the present invention should adjust according to preparation facilities during actual production.But in order to ensure the unlatching ability of the conducting channel of the active layer 6 of grid 5 pairs of thin-film transistors, namely ensure the normal work of thin-film transistor, the size of void region 10 should be less than 1/12nd of the size of grid 5, and the smaller the better.
Concrete, this array base palte comprises underlay substrate 12, grid 5, gate insulator 13, active layer 6, the source electrode 7 arranged with layer and drain electrode 8 from bottom to top successively and covers the passivation layer 16 of source electrode 7 and drain electrode 8.Wherein, in fact active layer 6 comprises sandwich construction, as shown in Figure 13 or 14, comprises the amorphous silicon layer 14 that thickness is 0.1 ~ 0.3 micron, as working media; This active layer 6 also comprises and is positioned on this amorphous silicon layer 14, to have wider band gap N-type doped amorphous silicon layer 15.N-type doped amorphous silicon layer 15 is and within amorphous silicon layer 14, mixes pentavalent media element, as phosphorus, arsenic etc.In this N-type doped amorphous silicon layer 15, there is part free electron, to strengthen the conductive capability of amorphous silicon layer 14, this thin-film transistor is more easily excited.
Further, the effect of active layer 6 is in order to when grid 5 has the signal of telecommunication, conducting source electrode 7 and drain electrode 8.Therefore, in embodiments of the present invention, as shown in Figure 13 or 14, N-type doped amorphous silicon layer 15 correspondence drain electrode 8 and source electrode 7 are arranged.
Wherein, contrast Figure 13 and Figure 14, because the grid 5 in the embodiment of the present invention has void region 10, and this void region 10 is corresponding with the end 11 of drain electrode.Therefore, as shown in figure 14, the subregion of the drain electrode subregion of 8 and the subregion of the N-type doped amorphous silicon layer 15 between the subregion of this drain electrode 8 and grid 5, the subregion of amorphous silicon layer 14 and gate insulator 13, for prior art as shown in fig. 13 that, has decline to a certain degree.Obviously, this structural trickle change can't affect the normal display of this TFT-LCD.
Further, the array base palte that the embodiment of the present invention provides is applicable to liquid crystal display, is particularly useful for the large scale liquid crystal display of more than 24 inches.
Further, the embodiment of the present invention additionally provides a kind of liquid crystal display, and this liquid crystal display comprises above-mentioned array base palte.
Although execution mode disclosed in this invention is as above, the execution mode that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technical staff in any the technical field of the invention; under the prerequisite not departing from spirit and scope disclosed in this invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (10)
1. an array base palte, is characterized in that, comprises the sub-pixel unit of multiple array arrangement, and each sub-pixel unit comprises thin-film transistor and pixel electrode, and described thin-film transistor comprises grid and the drain electrode being connected pixel electrode;
Wherein, described grid is formed with void region, and the correspondence drain electrode of described void region is arranged away from one end of described pixel electrode, and the end of described drain electrode is arranged in described void region.
2. array base palte according to claim 1, is characterized in that, described void region is circular, polygon or irregularly shaped.
3. array base palte as claimed in claim 1, it is characterized in that, described void region is square.
4. array base palte as claimed in claim 3, it is characterized in that, the length of described void region is 4 ~ 6 microns.
5. array base palte according to claim 4, is characterized in that, larger than the width of described drain electrode 2 ~ 6 microns of the width of described void region.
6. array base palte according to claim 1, is characterized in that, described thin-film transistor also comprises the active layer between described grid and described drain electrode.
7. array base palte according to claim 6, is characterized in that, described active layer comprises amorphous silicon layer and N-type doped amorphous silicon layer.
8. array base palte according to claim 7, is characterized in that, the corresponding described drain electrode of described N-type doped amorphous silicon layer is arranged.
9. the array base palte according to claim 7 or 8, is characterized in that, described array base palte is applicable to the liquid crystal display of more than 24 inches.
10. a liquid crystal display, is characterized in that, comprises the array base palte as described in any one of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410650057.6A CN104393004A (en) | 2014-11-14 | 2014-11-14 | Liquid crystal display and array substrate thereof |
| PCT/CN2014/092894 WO2016074295A1 (en) | 2014-11-14 | 2014-12-03 | Liquid crystal display and array substrate thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410650057.6A CN104393004A (en) | 2014-11-14 | 2014-11-14 | Liquid crystal display and array substrate thereof |
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| CN107482021A (en) * | 2017-08-21 | 2017-12-15 | 京东方科技集团股份有限公司 | Array base palte and display device |
| US20190057979A1 (en) * | 2017-08-21 | 2019-02-21 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN107482021B (en) * | 2017-08-21 | 2020-01-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US11004873B2 (en) | 2017-08-21 | 2021-05-11 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| US11810922B2 (en) | 2017-08-21 | 2023-11-07 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN108598155A (en) * | 2018-04-18 | 2018-09-28 | 昆山龙腾光电有限公司 | Thin film transistor (TFT), array substrate and display device |
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| WO2016074295A1 (en) | 2016-05-19 |
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