CN203422543U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203422543U CN203422543U CN201320416813.XU CN201320416813U CN203422543U CN 203422543 U CN203422543 U CN 203422543U CN 201320416813 U CN201320416813 U CN 201320416813U CN 203422543 U CN203422543 U CN 203422543U
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Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a substrate body, a data line and a scanning line, wherein the data line and the scanning line are arranged on the substrate body, the data line and the scanning line form a plurality of pixel regions in a surrounding mode, thin film transistors are arranged in the pixel regions, each thin film transistor comprises a grid electrode, a source electrode, a drain electrode and an active region, the grid electrodes are arranged above the active regions, the source electrodes and the drain electrodes are arranged on the two opposite sides of the active regions respectively, and shading metal layers are further arranged in the pixel regions. The shading metal layers and the data lines are arranged on the substrate body in a same-layer mode, the shading metal layers are arranged below the active regions, and the shading metal layers and the active regions are at least partially overlapped in the orthographic projection direction. The data lines are close to the source electrodes, and the data lines and the active regions are at least not partially overlapped in the orthographic projection direction. According to the array substrate and the display device, due to the fact that the shading metal layers and the data lines are formed in the same layer in the same step, the times of composition processes of the array substrate are reduced, and the preparation efficiency of the array substrate and the preparation efficiency of the display device are improved.
Description
Technical field
The utility model relates to display technique field, particularly, relates to a kind of array base palte and display device.
Background technology
Liquid crystal indicator (LCD:Liquid Crystal Display) has become the main product in current panel display apparatus because of features such as its volume are little, low in energy consumption, radiationless.
At present, more common liquid crystal indicator is the liquid crystal indicator of twisted nematic display mode (being TN display mode).Along with the development of display technique, also there is the liquid crystal indicator of senior super Wei Chang conversion display mode (being ADS display mode).At present, that comparative maturity is thin-film transistor LCD device (TFT-LCD) technically, liquid crystal indicator comprises array base palte and color membrane substrates, wherein, thin film transistor (TFT) is formed on array base palte, thin film transistor (TFT) comprises gate electrode, source electrode and drain electrode, and thin film transistor (TFT) adopts amorphous silicon (a-Si) material to form conventionally.
Along with the development of display technique, occurred that employing polysilicon (p-Si) material forms the mode of thin film transistor (TFT).Concrete, first adopt polysilicon (p-Si) material to be formed with source region, then crystallization and Implantation are carried out in active area, thereby form source electrode and the drain electrode of thin film transistor (TFT).Studies show that, the performance of the thin film transistor (TFT) that the Performance Ratio employing amorphous silicon material of the thin film transistor (TFT) that employing polysilicon (p-Si) material forms forms is high more than 100 times.Polysilicon comprises high temperature polysilicon (HTPS) and low temperature polycrystalline silicon (LTPS), wherein, the thin film transistor (TFT) that adopts low temperature polycrystalline silicon to form has higher electron mobility, can also dwindle the size of thin film transistor (TFT), therefore be widely used in array base palte, both realize high aperture, and made again corresponding display device there is high brightness, low power consumption.
Compare with the thin film transistor (TFT) that adopts amorphous silicon material to form, the thin film transistor (TFT) work hourglass current ratio that adopts low temperature polycrystalline silicon material to form is larger, therefore, in order to reduce leakage current, as shown in a kind of structural representation of array base palte in Fig. 1, in array base palte correspondence, thin film transistor (TFT) active area 4 below be provided with shading metal level 3, shading metal level 3 covers a part of light that is irradiated to the region between drain electrode 7 and source electrode 6, thereby leakage current is reduced; Or, in the process that forms drain electrode 7 and source electrode 6, adopt ion implantation (also claiming ion doping method) that lightly doped drain 8 is set in active area 4; Or thin film transistor (TFT) is set to double-grid structure (as having two gate electrodes 5 in Fig. 1) etc., can reduce to a certain extent leakage current.
The array base palte that includes the thin film transistor (TFT) of amorphous silicon material formation with employing is compared, the array base palte that employing includes the thin film transistor (TFT) that polycrystalline silicon material forms needs the composition technique of more times number while preparing, as shown in the preparation process figure of array base palte in Fig. 2 (as step P1-P10), in order to be formed for reducing the shading metal level 3 of thin-film transistor drain current, when prepared by array base palte, need increase the composition technique that shading metal level 3 comprises exposure technology (as step P1), add the original composition technique of other rete in array base palte preparation process, for example data line 2(is as step P6), public electrode 12(is as step P8), pixel electrode 14(is as step P10) and the first via hole 15(of being used to form the electrical connection between data line 2 and source electrode 6 as step P5), the 3rd via hole 17 being electrically connected between pixel electrode 14 and drain electrode 7, the 4th via hole 18 and the 5th via hole 19(are as step P5, P7 and P9, wherein, due to necessary mutual insulating between data line 2 and public electrode 12, and the two has overlapping or says intersection in orthogonal projection direction, therefore the flatness layer 20 that plays insulating effect between the two is indispensable, accordingly, in flatness layer 20, forming pixel electrode 14 is also absolutely necessary with the 5th via hole 19 composition techniques that are electrically connected between drain electrode 7), cause the preparation method's composition number of processes that adopts polycrystalline silicon material to prepare array base palte to increase, make the preparation section of corresponding array base palte various, preparation efficiency is low.
Summary of the invention
The utility model, for the above-mentioned technical matters existing in prior art, provides a kind of array base palte and display device.Described array base palte is by shading metal level and data line are formed on described substrate with layer in same step, thereby reduced the composition technique number of times of array base palte, improved the preparation efficiency of array base palte.
Described array base palte comprises substrate and is arranged on data line and the sweep trace on substrate, data line and sweep trace surround a plurality of pixel regions, in pixel region, be provided with thin film transistor (TFT), thin film transistor (TFT) comprises gate electrode, source electrode, drain electrode and active area, gate electrode is arranged on the top of active area, source electrode divides with drain electrode the relative both sides that are located at active area, in pixel region, be also provided with shading metal level, shading metal level and data line are arranged on substrate with layer, shading metal level is arranged on below, active area and overlapping at least partly with active area in orthogonal projection direction, data line is near source electrode and not overlapping at least partly with active area in orthogonal projection direction.
Preferably, shading metal level and data line adopt identical conductive material.
Preferably, active area adopts low temperature polycrystalline silicon material, and source electrode adopts the mode of Implantation to be formed on the relative both sides of active area with drain electrode.
Preferably, shading metal level is arranged between source electrode and region corresponding to drain electrode, and overlapping at least partly with gate electrode in orthogonal projection direction.
Preferably, be also provided with lightly doped drain in active area, lightly doped drain is arranged between source electrode and drain electrode, and separation is in the both sides in region corresponding to gate electrode.
Preferably, array base palte also comprises cushion, and cushion is arranged on the below of active area and the top of substrate, and shading metal level and data line are cushioned layer and cover.
Preferably, gate electrode is at least one, and shading metal level is a slice at least, the setting corresponding to gate electrode position of shading metal level.
Preferably, array base palte also comprises gate insulation layer, and gate insulation layer is arranged on the top of described active area and the below of gate electrode, and active area and cushion are covered by gate insulation layer.
Preferably, array base palte also comprises intermediate dielectric layer, the first electrode, passivation layer and the second electrode that is successively set on gate electrode top, the second electrode and the first electrode are overlapping at least partly in orthogonal projection direction, and the first electrode is tabular, and the second electrode is slit-shaped;
The position that cushion, gate insulation layer and intermediate dielectric layer data line in correspondence offers the first via hole, the position that gate insulation layer and intermediate dielectric layer source electrode in correspondence offers the second via hole, and data line and source electrode are electrically connected to by the first via hole and the second via hole.
Preferably, the first electrode is pixel electrode, and the second electrode is public electrode, and the position that gate insulation layer, intermediate dielectric layer drain electrode in correspondence offers the 3rd via hole, and pixel electrode and drain electrode are electrically connected to by the 3rd via hole;
Or, the first electrode is public electrode, the second electrode is pixel electrode, the position that gate insulation layer, intermediate dielectric layer drain electrode in correspondence offers the 3rd via hole, the position that passivation layer drain electrode in correspondence offers the 4th via hole, and pixel electrode and drain electrode are electrically connected to by the 3rd via hole and the 4th via hole.
Preferably, array base palte also comprises pixel electrode, and pixel electrode is arranged on the top of gate insulation layer, and the position that gate insulation layer drain electrode in correspondence offers the 3rd via hole, and pixel electrode is electrically connected to by the 3rd via hole with drain electrode;
Gate insulation layer and cushion offer the first via hole in the position of respective data lines, and the position that gate insulation layer source electrode in correspondence offers the second via hole, and data line and source electrode are electrically connected to by the first via hole and the second via hole.
The utility model also provides a kind of display device, comprises above-mentioned array base palte.
The beneficial effects of the utility model: in array base palte provided by the utility model, described shading metal level and described data line are formed on the same layer of described array base palte; Described shading metal level and described data line form by same composition technique, compare with the preparation of existing array base palte, reduced the independent composition technique to data line, thereby reduced the composition technique total degree in array base palte preparation, improved the preparation efficiency of array base palte and display device.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte in prior art;
Fig. 2 is preparation method's process flow diagram of array base palte shown in Fig. 1;
Fig. 3 is the structural representation of array base palte in the utility model embodiment 1;
Fig. 4 is preparation method's process flow diagram of array base palte shown in Fig. 3;
Fig. 5 is the structural representation of array base palte in the utility model embodiment 3;
Fig. 6 is preparation method's process flow diagram of array base palte shown in Fig. 5.
Description of reference numerals wherein:
1. substrate; 2. data line; 3. shading metal level; 4. active area; 5. gate electrode; 6. source electrode; 7. drain electrode; 8. lightly doped drain; 9. cushion; 10. gate insulation layer; 11. intermediate dielectric layer; 12. public electrodes; 13. passivation layers; 14. pixel electrodes; 15. first via holes; 16. second via holes; 17. the 3rd via holes; 18. the 4th via holes; 19. the 5th via holes; 20. flatness layers.
Embodiment
For making those skilled in the art understand better the technical solution of the utility model, below in conjunction with the drawings and specific embodiments, a kind of array base palte of the utility model and display device are described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte, as shown in Figure 3, described array base palte comprises substrate 1 and is arranged on data line 2 and the sweep trace (not shown in Fig. 3) on substrate 1, described data line 2 and described sweep trace surround a plurality of pixel regions, in described pixel region, be provided with thin film transistor (TFT), thin film transistor (TFT) comprises gate electrode 5, source electrode 6, drain electrode 7 and active area 4, gate electrode 5 is arranged on the top of active area 4, source electrode 6 and drain electrode are located at the relative both sides of active area 4 for 7 minutes, in described pixel region, be also provided with shading metal level 3, shading metal level 3 and data line 2 are arranged on substrate 1 with layer, shading metal level 3 is arranged on 4 belows, active area, and overlapping at least partly with active area 4 in orthogonal projection direction, data line 2 is near source electrode 6 and not overlapping at least partly with active area 4 in orthogonal projection direction.
Wherein, shading metal level 3 is arranged between the region that source electrode 6 is corresponding with drain electrode 7, and overlapping at least partly with described gate electrode 5 in orthogonal projection direction.Active area 4 adopts low temperature polycrystalline silicon material, and source electrode 6 adopts the mode (as Implantation boracic or phosphorated material) of Implantation to be formed on the relative both sides of active area 4 with drain electrode 7.
In the present embodiment, shading metal level and active area partly overlap, be that shading metal level is arranged between the region that source electrode is corresponding with drain electrode, object is in order to make shading metal level at least will cover a part of region of active area, thereby make the light that is irradiated to active area can be covered a part, and then reduce the leakage current of active area; Certainly, shading metal level also can be completely overlapping with active area, and like this, shading metal level just covers active area completely, thereby the light that is irradiated to active area is all covered, and can further reduce the leakage current of active area.
Wherein, shading metal level 3 adopts identical conductive material with data line 2, and the shading metal level 3 and the data line 2 that make to be arranged in same layer can form by a composition technique simultaneously; And because this conductive material is light tight, so shading metal level 3 plays simultaneously, cover the part light that is irradiated to active area 4, thereby reduce the effect of the leakage current of thin film transistor (TFT).
Preferably, in the present embodiment, be also provided with lightly doped drain 8 in active area 4, lightly doped drain 8 is arranged between source electrode 6 and drain electrode 7, and separation is in the both sides in the region of gate electrode 5 correspondences.In the present embodiment, lightly doped drain 8 can play the effect of the leakage current that reduces thin film transistor (TFT) simultaneously.
Wherein, gate electrode is at least one, and shading metal level is a slice at least.In the present embodiment, gate electrode 5 is two, and shading metal level 3 is two, shading metal level 3 and the gate electrode 5 corresponding settings in position.In the present embodiment, gate electrode is set to two effects that can simultaneously play the leakage current that reduces thin film transistor (TFT).
In the present embodiment, array base palte also comprises cushion 9, and cushion 9 is arranged on the below of active area 4 and the top of substrate 1, and shading metal level 3 and data line 2 are cushioned layer 9 and cover completely.Because active area in the present embodiment 4 adopts low temperature polycrystalline silicon material, described cushion 9 enters in the active area 4 of thin film transistor (TFT) for stopping the contained Impurity Diffusion of substrate 1, prevents the characteristics such as the threshold voltage of thin film transistor (TFT) and leakage current to exert an influence; Meanwhile, because low temperature polycrystalline silicon is normally formed on substrate 1 by the method for quasi-molecule laser annealing, cushion 9 is set and can further prevents that quasi-molecule laser annealing from causing the Impurity Diffusion in substrate 1, improve the quality of the thin film transistor (TFT) of low temperature polycrystalline silicon formation.
In the present embodiment, array base palte also comprises gate insulation layer 10 and is successively set on gate electrode 5 tops intermediate dielectric layer 11, the first electrode, passivation layer 13 and the second electrode; Wherein, gate insulation layer 10 is arranged on the top of described active area 4 and the below of gate electrode 5, and active area 4 and cushion 9 are covered by gate insulation layer 10; The second electrode and the first electrode are overlapping at least partly in orthogonal projection direction, and the first electrode is tabular, and the second electrode is slit-shaped.Now, the position that cushion 9, gate insulation layer 10 and intermediate dielectric layer 11 data line 2 in correspondence offers the first via hole 15, the position that gate insulation layer 10 and intermediate dielectric layer 11 source electrode 6 in correspondence offers the second via hole 16, and data line 2 and source electrode 6 are electrically connected to by the first via hole 15 and the second via hole 16.
In the present embodiment, the first electrode is public electrode 12, the second electrode is pixel electrode 14, the position that gate insulation layer 10, intermediate dielectric layer 11 drain electrode 7 in correspondence offers the 3rd via hole 17, the position that passivation layer 13 drain electrode 7 in correspondence offers the 4th via hole 18, and pixel electrode 14 is electrically connected to by the 3rd via hole 17 and the 4th via hole 18 with drain electrode 7.
It should be noted that, between intermediate dielectric layer 11 and the first electrode, flatness layer can also be set, flatness layer can make intermediate dielectric layer keep smooth; Certainly, between intermediate dielectric layer 11 and the first electrode, also can flatness layer be set, as described in the present embodiment, this can make the thickness of array base palte relatively thin.In the present embodiment, all take the first electrode as tabular explanation, be understandable that, the first electrode can also be slit-shaped.
Structure based on above-mentioned array base palte, the preparation method of this array base palte comprises: on substrate, form data line, sweep trace, the step of the step of shading metal level and formation thin film transistor (TFT), form described thin film transistor (TFT) and comprise formation gate electrode, source electrode, the step of drain electrode and active area, described thin film transistor (TFT) and described shading metal level are all formed in a plurality of pixel regions that surrounded by described sweep trace and described sweep trace, shading metal level and data line are formed on substrate with layer in same step, shading metal level is formed on below, active area and overlapping at least partly with active area in orthogonal projection direction, data line is near source electrode and not overlapping at least partly with active area in orthogonal projection direction.
As shown in Figure 4, described preparation method specifically comprises:
Step S1: adopt a composition technique simultaneously to form the figure that comprises data line 2 and shading metal level 3 on substrate 1, the setting of being separated by of data line 2 and shading metal level 3.
Wherein, described composition technique, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technological processs such as comprising film forming, exposure, development form the technique of figure.
In the present embodiment, described composition technique comprises: first, form the conductive material that (as sputter or coating etc.) one deck is used to form data line 2 and shading metal level 3 on substrate 1; Then, on conductive material, apply one deck photoresist; Then, with the mask plate that is provided with the figure that comprises data line and shading metal level, photoresist is exposed; Finally by forming the figure that comprises data line 2 and shading metal level 3 after development, etching.In the preparation method of the present embodiment array base palte, the preparation technology who relates to the rete forming by composition technique is identical therewith, is no longer described in detail.
Step S2: form cushion 9 and the figure that includes source region 4 on the substrate 1 of completing steps S1; Cushion 9 covers shading metal level 3 and data line 2 completely, and the figure of active area 4 is formed on cushion 9, and the figure of active area 4 is overlapping at least partly with shading metal level 3 in orthogonal projection direction.
Step S3: form gate insulation layer 10 and the figure that comprises gate electrode 5 on the substrate 1 of completing steps S2, the figure of gate electrode 5 is formed on the top corresponding with described shading metal level 3 positions of gate insulation layer 10.
Step S4: form source electrode 6 and drain electrode 7 on the substrate 1 of completing steps S3, source electrode 6 adopts Implantation mode to be formed on the relative both sides of active area 4 with drain electrode 7.
Described preparation method also comprises the step that forms the figure that comprises the first electrode and the second electrode, and wherein, the first electrode is that public electrode 12, the second electrodes are pixel electrode 14, and concrete preparation method is:
Step S5 ': the figure that forms intermediate dielectric layer 11 and comprise the first via hole 15, the second via hole 16 and the 3rd via hole 17 on the substrate 1 of completing steps S4, wherein: the first via hole 15 is formed on the position of corresponding data line 2 and runs through cushion 9, gate insulation layer 10 and intermediate dielectric layer 11, the second via hole 16 is formed on the position of corresponding source electrode 6 and runs through gate insulation layer 10 and intermediate dielectric layer 11, the three via holes 17 are formed on the position of corresponding drain electrode 7 and run through gate insulation layer 10 and intermediate dielectric layer 11.
Step S6 ': form the figure that comprises public electrode 12 on the substrate 1 of completing steps S5 ', data line 2 is electrically connected to by the first via hole 15 and the second via hole 16 with source electrode 6, in the 3rd via hole 17, is filled with the conductive material that is used to form public electrode 12 simultaneously.
Step S7 ': form passivation layer 13 and form the figure that comprises the 4th via hole 18 on the substrate 1 of completing steps S6 ' in passivation layer 13, the 4th via hole 18 is formed on corresponding the position of drain electrode 7, and the position of the 4th via hole 18 is corresponding with the position of the 3rd via hole 17.
Step S8 ': form the figure that comprises pixel electrode 14 on the substrate 1 of completing steps S7 ', pixel electrode 14 is electrically connected to by the 3rd via hole 17 and the 4th via hole 18 with drain electrode 7.
Preferably, this preparation method's step S4 also further comprises: adopt Implantation mode in active area 4, to form lightly doped drain 8, lightly doped drain 8 is formed between source electrode 6 and drain electrode 7, and separation is in the both sides in the region of gate electrode 5 correspondences.
Preferably, the shading metal level 3 forming in step S1 is two, and the gate electrode 5 forming in step S3 is two, shading metal level 3 and the gate electrode 5 corresponding settings in position.
As the preparation method corresponding with a kind of preferred structure of array base palte, when forming flatness layer between intermediate dielectric layer 11 and the first electrode, the composition technique that forms the via hole being electrically connected between pixel electrode 14 and drain electrode 7 in flatness layer can be same with the composition technique that forms the 3rd via hole 17, can't increase extra technological process (can not increase the composition technique of corresponding prior art array base palte preparation method's step P7).
Embodiment 2:
The array base palte that the present embodiment provides, as different from Example 1: the first electrode is tabular pixel electrode, the public electrode that the second electrode is slit-shaped; Accordingly, in this array base palte, the position that gate insulation layer, intermediate dielectric layer drain electrode in correspondence offers the 3rd via hole, and pixel electrode is electrically connected to by the 3rd via hole with drain electrode.Difference based on above-mentioned array base-plate structure does not need to offer the 4th via hole in the present embodiment array base palte, and other structure of array base palte and material are all identical with embodiment 1, do not repeat them here.
Correspondingly, structure based on above-mentioned array base palte, the preparation method of this array base palte is different from the preparation method of array base palte in embodiment 1: with the structure of above-mentioned array base palte accordingly, array base palte in the present embodiment is not offered the step of the 4th via hole, and public electrode is formed on pixel electrode.
In the present embodiment, in described preparation method, formation comprises that the step of the figure of the first electrode and the second electrode is specially:
Step S5: the figure that forms intermediate dielectric layer and comprise the first via hole, the second via hole and the 3rd via hole on the substrate of completing steps S4, wherein: the first via hole is formed on the position of corresponding data line and runs through cushion, gate insulation layer and intermediate dielectric layer, the second via hole is formed on the position of corresponding source electrode and runs through gate insulation layer and intermediate dielectric layer, and the 3rd via hole is formed on the position of corresponding drain electrode and runs through gate insulation layer and intermediate dielectric layer.
Step S6: form the figure that comprises pixel electrode on the substrate of completing steps S5, data line is electrically connected to by the first via hole and the second via hole with source electrode, and pixel electrode is electrically connected to by the 3rd via hole with drain electrode.
Step S7: the figure that forms passivation layer and comprise public electrode on the substrate of completing steps S6, passivation layer covers pixel electrode completely, and the figure of public electrode is formed on the top of passivation layer.
Other step of the preparation method of the array base palte providing in the present embodiment is identical with embodiment 1, repeats no more here.
Embodiment 3:
The present embodiment provides a kind of array base palte, as shown in Figure 5, described array base palte comprises substrate 1 and is arranged on data line 2 and the sweep trace (not shown in Fig. 3) on substrate 1, described data line 2 and described sweep trace surround a plurality of pixel regions, in described pixel region, be provided with thin film transistor (TFT), thin film transistor (TFT) comprises gate electrode 5, source electrode 6, drain electrode 7 and active area 4, institute's gate electrode 5 is arranged on the top of active area 4, source electrode 6 and drain electrode are located at the relative both sides of active area 4 for 7 minutes, in described pixel region, be also provided with shading metal level 3, shading metal level 3 and data line 2 are arranged on substrate 1 with layer, shading metal level 3 is arranged on below, active area, and overlapping at least partly with active area 4 in orthogonal projection direction, data line 2 is near source electrode 6 and not overlapping at least partly with active area 4 in orthogonal projection direction.
Wherein, described array base palte also comprises: lightly doped drain 8, cushion 9 and gate insulation layer 10.
Structure in above-mentioned array base palte and material are identical with embodiment 1 or embodiment 2, repeat no more here.
Different with embodiment 2 from embodiment 1: the array base palte in the present embodiment also comprises pixel electrode 14, pixel electrode 14 is arranged on the top of gate insulation layer 10, the position that gate insulation layer 10 drain electrode 7 in correspondence offers the 3rd via hole 17, and pixel electrode 14 is electrically connected to by the 3rd via hole 17 with drain electrode 7; Gate insulation layer 10 and cushion 9 offer the first via hole 15 in the position of respective data lines 2, the position that gate insulation layer 10 source electrode 6 in correspondence offers the second via hole 16, and data line 2 and source electrode 6 are electrically connected to by the first via hole 15 and the second via hole 16.
Correspondingly, structure based on above-mentioned array base palte, in the preparation method of this array base palte, front four steps (being step S1, S2, S3, S4) are identical with front four steps of array base palte preparation method in embodiment 1 or embodiment 2, in addition, the preparation method of this array base palte also comprises the step that forms pixel electrode, as shown in Figure 6, is specially:
Step S5 ": on the substrate 1 of completing steps S4, form the figure comprise the first via hole 15, the second via hole 16 and the 3rd via hole 17; wherein: the first via hole 15 is formed on the position of corresponding data line 2 and runs through cushion 9 and gate insulation layer 10; the second via hole 16 is formed on the position of corresponding source electrode 6 and runs through gate insulation layer 10, the three via holes 17 and is formed on the position of corresponding drain electrode 7 and runs through gate insulation layer 10.
Step S6 ": at completing steps S5 " substrate 1 on form the figure comprise pixel electrode 14, data line 2 is electrically connected to source electrode 6 by the first via hole 15 and the second via hole 16; Pixel electrode 14 is electrically connected to by the 3rd via hole 17 with drain electrode 7.
It should be noted that, embodiment 1 and embodiment 2 are that the array base palte with senior super Wei Chang conversion display mode (being ADS display mode) is specifically described embodiment of the present utility model as example, embodiment 3 is that the array base palte with twisted nematic display mode (being TN display mode) is specifically described embodiment of the present utility model as example, but above embodiment is only preferred implementation of the present utility model, and practical ranges of the present utility model is not limited to this.
Wherein, ADS(ADvanced Super Dimension Switch, senior super Wei Chang conversion) pattern is the wide visual angle of plane electric fields core technology, its core technology characteristic description is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal work efficiency and increased light transmission efficiency.The switching technique of ADS pattern can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).For different application, the improvement technology of ADS technology has high permeability I-ADS technology, high aperture H-ADS and high resolving power S-ADS technology etc.
The beneficial effects of the utility model: in array base palte provided by the utility model, shading metal level and data line are formed in the same layer of described array base palte; Described shading metal level and data line are to form by same composition technique (comprising exposure technology); In existing array base palte, shading metal level and data line do not form in same composition technique, and the two is not arranged in the same layer of array base palte yet and compares, reduced independent composition technique to data line (having reduced the composition technique in corresponding prior art array base palte preparation method's step P6) thus the composition number of processes of array base palte is reduced, improved the preparation efficiency of array base palte and display device.
Embodiment 4:
The present embodiment provides a kind of display device, comprises the array base palte that above-mentioned any one embodiment provides.
Described display device, owing to having adopted the array base palte described in above-described embodiment, has therefore reduced the quantity of the composition technique of array base palte, thereby has improved the preparation efficiency of display device.
Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Be understandable that, above embodiment is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (12)
1. an array base palte, comprise substrate and be arranged on data line and the sweep trace on described substrate, described data line and described sweep trace surround a plurality of pixel regions, in described pixel region, be provided with thin film transistor (TFT), described thin film transistor (TFT) comprises gate electrode, source electrode, drain electrode and active area, described gate electrode is arranged on the top of described active area, described source electrode divides with described drain electrode the relative both sides that are located at described active area, in described pixel region, be also provided with shading metal level, it is characterized in that, described shading metal level and described data line are arranged on described substrate with layer, described shading metal level is arranged on below, described active area, and overlapping at least partly with described active area in orthogonal projection direction, described data line is near described source electrode and not overlapping at least partly with described active area in orthogonal projection direction.
2. array base palte according to claim 1, is characterized in that, described shading metal level and described data line adopt identical conductive material.
3. array base palte according to claim 2, is characterized in that, described active area adopts low temperature polycrystalline silicon material, and described source electrode adopts the mode of Implantation to be formed on the relative both sides of described active area with described drain electrode.
4. array base palte according to claim 3, is characterized in that, described shading metal level is arranged between described source electrode and region corresponding to described drain electrode, and overlapping at least partly with described gate electrode in orthogonal projection direction.
5. array base palte according to claim 4, is characterized in that, is also provided with lightly doped drain in described active area, and described lightly doped drain is arranged between described source electrode and described drain electrode, and separation is in the both sides in region corresponding to described gate electrode.
6. array base palte according to claim 5, it is characterized in that, described array base palte also comprises cushion, and described cushion is arranged on the below of described active area and the top of described substrate, and described shading metal level and described data line are covered by described cushion.
7. array base palte according to claim 6, is characterized in that, described gate electrode is at least one, and described shading metal level is a slice at least, described shading metal level and the corresponding setting in described gate electrode position.
8. array base palte according to claim 7, it is characterized in that, described array base palte also comprises gate insulation layer, and described gate insulation layer is arranged on the top of described active area and the below of described gate electrode, and described active area and described cushion are covered by described gate insulation layer.
9. array base palte according to claim 8, it is characterized in that, described array base palte also comprises intermediate dielectric layer, the first electrode, passivation layer and the second electrode that is successively set on described gate electrode top, described the second electrode and described the first electrode are overlapping at least partly in orthogonal projection direction, described the first electrode is tabular or slit-shaped, and described the second electrode is slit-shaped;
The position that described cushion, described gate insulation layer and described intermediate dielectric layer described data line in correspondence offers the first via hole, the position that described gate insulation layer and described intermediate dielectric layer described source electrode in correspondence offers the second via hole, and described data line and described source electrode are electrically connected to by described the first via hole and described the second via hole.
10. array base palte according to claim 9, it is characterized in that, described the first electrode is pixel electrode, described the second electrode is public electrode, the position that described gate insulation layer, described intermediate dielectric layer described drain electrode in correspondence offers the 3rd via hole, and described pixel electrode and described drain electrode are electrically connected to by described the 3rd via hole;
Or, described the first electrode is public electrode, described the second electrode is pixel electrode, the position that described gate insulation layer, described intermediate dielectric layer described drain electrode in correspondence offers the 3rd via hole, the position that described passivation layer described drain electrode in correspondence offers the 4th via hole, and described pixel electrode and described drain electrode are electrically connected to by described the 3rd via hole and described the 4th via hole.
11. array base paltes according to claim 8, it is characterized in that, described array base palte also comprises pixel electrode, described pixel electrode is arranged on the top of described gate insulation layer, the position that described gate insulation layer described drain electrode in correspondence offers the 3rd via hole, and described pixel electrode is electrically connected to by described the 3rd via hole with described drain electrode;
Described gate insulation layer and described cushion offer the first via hole in the position of the described data line of correspondence, the position that described gate insulation layer described source electrode in correspondence offers the second via hole, and described data line and described source electrode are electrically connected to by described the first via hole and described the second via hole.
12. 1 kinds of display device, is characterized in that, comprise the array base palte described in claim 1-11 any one.
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|---|---|---|---|
| CN201320416813.XU CN203422543U (en) | 2013-07-12 | 2013-07-12 | Array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320416813.XU CN203422543U (en) | 2013-07-12 | 2013-07-12 | Array substrate and display device |
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| CN203422543U true CN203422543U (en) | 2014-02-05 |
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| CN201320416813.XU Withdrawn - After Issue CN203422543U (en) | 2013-07-12 | 2013-07-12 | Array substrate and display device |
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| CN (1) | CN203422543U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103383946A (en) * | 2013-07-12 | 2013-11-06 | 京东方科技集团股份有限公司 | Array substrate, display device and preparation method of array substrate |
| CN106062858A (en) * | 2014-03-05 | 2016-10-26 | Lg 电子株式会社 | Display device using semiconductor light emitting device |
| WO2019140718A1 (en) * | 2018-01-22 | 2019-07-25 | 深圳市华星光电半导体显示技术有限公司 | Display substrate |
| CN111681608A (en) * | 2020-06-09 | 2020-09-18 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit structure and display device |
| US10790311B2 (en) | 2018-01-22 | 2020-09-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display substrate |
| CN114299823A (en) * | 2020-09-22 | 2022-04-08 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, light detection method and display device |
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2013
- 2013-07-12 CN CN201320416813.XU patent/CN203422543U/en not_active Withdrawn - After Issue
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| CN103383946A (en) * | 2013-07-12 | 2013-11-06 | 京东方科技集团股份有限公司 | Array substrate, display device and preparation method of array substrate |
| CN103383946B (en) * | 2013-07-12 | 2016-05-25 | 京东方科技集团股份有限公司 | The preparation method of a kind of array base palte, display unit and array base palte |
| US9559125B2 (en) | 2013-07-12 | 2017-01-31 | Boe Technology Group Co., Ltd. | Array substrate, display device, and method for manufacturing the array substrate |
| US9735182B2 (en) | 2013-07-12 | 2017-08-15 | Boe Technology Group Co., Ltd. | Array substrate, display device, and method for manufacturing the array substrate |
| CN106062858A (en) * | 2014-03-05 | 2016-10-26 | Lg 电子株式会社 | Display device using semiconductor light emitting device |
| CN106062858B (en) * | 2014-03-05 | 2019-05-03 | Lg 电子株式会社 | Use the display equipment of light emitting semiconductor device |
| WO2019140718A1 (en) * | 2018-01-22 | 2019-07-25 | 深圳市华星光电半导体显示技术有限公司 | Display substrate |
| US10790311B2 (en) | 2018-01-22 | 2020-09-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display substrate |
| CN111681608A (en) * | 2020-06-09 | 2020-09-18 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit structure and display device |
| CN111681608B (en) * | 2020-06-09 | 2021-06-22 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit structure and display device |
| CN114299823A (en) * | 2020-09-22 | 2022-04-08 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, light detection method and display device |
| CN114299823B (en) * | 2020-09-22 | 2023-12-29 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, light detection method and display device |
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