CN106773404B - Wide-viewing-angle pixel structure and array substrate - Google Patents
Wide-viewing-angle pixel structure and array substrate Download PDFInfo
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- CN106773404B CN106773404B CN201611245381.5A CN201611245381A CN106773404B CN 106773404 B CN106773404 B CN 106773404B CN 201611245381 A CN201611245381 A CN 201611245381A CN 106773404 B CN106773404 B CN 106773404B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Abstract
The invention provides a wide-viewing-angle pixel structure and an array substrate. The wide-view pixel structure comprises a scanning line group and a data line group which are vertically arranged, and two pixel regions formed by the scanning line group and the data line group, wherein the scanning line group comprises a first scanning line, a second scanning line and a third scanning line which are sequentially arranged in parallel, and the data line group comprises a first data line and a second data line which are arranged in parallel; the first scanning line, the second scanning line, the first data line and the second data line form a first pixel area; the second scanning line, the third scanning line, the first data line and the second data line form a second pixel area; the first pixel region includes a first main region and a first sub region, the second pixel region includes a second main region, a second sub region and a first thin film transistor, and the first sub region and the second sub region are connected by the first thin film transistor. On the premise of realizing a wide view angle, the structure can reduce the number of thin film transistors, and is favorable for realizing high aperture opening ratio.
Description
Technical Field
The invention relates to the technical field of display, in particular to a wide-viewing-angle pixel structure and an array substrate.
Background
The Vertical Alignment (VA) mode has the advantages of wide viewing angle and high contrast, and is a common mode of Thin Film Transistor liquid crystal Display (TFT-LCD) for large-sized TV. Color Shift (Color Shift) phenomenon at different viewing angles is a significant problem faced by VA products. In order to solve the problem of color shift at large viewing angles, a general countermeasure is to adopt an 8-domain design, i.e., to divide one pixel into 2 regions, namely, a main region (main region) and a sub region (sub region). Under the condition of applying voltage, the liquid crystal in each area has four different inversions, and the voltage of the sub area is lower than that of the mian area, so that the liquid crystal in one pixel has 8 different inversions, and a wide view angle is realized. Fig. 1 shows a conventional wide viewing angle pixel design, where 101 is a data line, 201 is a scan line, 301 is a main region, and 401 is a sub region. There are 3 Thin Film Transistors (TFT), 2 of which are used to charge the pixel, 1 of which is used to discharge the sub region, and the pixel also includes a shared capacitor (share capacitor) used to realize different potentials of the sub and main regions.
In the above structure in the prior art, 3 TFTs are required to be used for each pixel, and in order to further reduce the use of TFTs and achieve a high aperture ratio, a method or a structure is needed to improve the above structure.
Disclosure of Invention
The invention provides a wide-viewing-angle pixel structure and an array substrate, which are used for solving the technical problem of low aperture ratio caused by a large number of TFTs in the prior art.
One aspect of the present invention provides a wide viewing angle pixel structure, including: the pixel structure comprises a scanning line group, a data line group and two pixel regions, wherein the scanning line group and the data line group are vertically arranged, the two pixel regions are formed by the scanning line group and the data line group, the scanning line group comprises a first scanning line, a second scanning line and a third scanning line which are sequentially arranged in parallel, and the data line group comprises a first data line and a second data line which are arranged in parallel; the first scanning line, the second scanning line, the first data line and the second data line form a first pixel area; the second scanning line, the third scanning line, the first data line and the second data line form a second pixel area; the first pixel region includes a first main region and a first sub region, the second pixel region includes a second main region, a second sub region and a first thin film transistor, and the first sub region and the second sub region are connected by the first thin film transistor.
Furthermore, the first sub-area comprises a second thin film transistor and a first sub-area pixel electrode, wherein the gate of the second thin film transistor is connected with the first scan line, the source of the second thin film transistor is connected with the first data line, and the drain of the second thin film transistor is respectively connected with the first sub-area pixel electrode and the drain of the first thin film transistor.
Furthermore, the second sub-area comprises a third thin film transistor and a second sub-area pixel electrode, the grid electrode of the third thin film transistor is connected with the second scanning line, the drain electrode of the third thin film transistor is connected with the second sub-area pixel electrode, the source electrode of the third thin film transistor and the source electrode of the first thin film transistor are both connected with the second data line, and the grid electrode of the first thin film transistor is connected with the third scanning line.
Further, the second main region includes a second main region pixel electrode and a fourth thin film transistor, wherein a gate of the fourth thin film transistor is connected to the second scan line, a drain of the fourth thin film transistor is connected to the second main region pixel electrode, and a source of the fourth thin film transistor is connected to the second data line.
Further, the first main region includes a first main region pixel electrode and a fifth thin film transistor, wherein a gate of the fifth thin film transistor is connected to the first scan line, a source of the fifth thin film transistor is connected to the first data line, and a drain of the fifth thin film transistor is connected to the first main region pixel electrode.
Further, the polarities of the first sub-area pixel electrode and the second sub-area pixel electrode are opposite.
Further, the polarity of the second main area pixel electrode is the same as that of the second sub area pixel electrode.
Further, the polarity of the first main region pixel electrode is the same as that of the first sub region pixel electrode.
Another aspect of the present invention provides an array substrate, including: the wide-viewing-angle pixel structure comprises a substrate and the wide-viewing-angle pixel structure, wherein the wide-viewing-angle pixel structure is arranged on the substrate.
According to the wide-viewing-angle pixel structure and the array substrate, the first thin film transistor is used for discharging the first sub-area and the second sub-area at the same time, and the first sub-area or the second sub-area is not required to be respectively connected with the shared capacitor through the respective thin film transistor, so that the structure not only reduces the number of the thin film transistors, but also reduces the use of the shared capacitor, and further improves the aperture opening ratio.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
FIG. 1 is a schematic circuit diagram of a prior art wide-viewing-angle pixel structure;
FIG. 2 is a schematic circuit diagram of a wide-viewing-angle pixel structure according to an embodiment of the present invention;
fig. 3 is a schematic view of a wide-viewing-angle pixel structure according to an embodiment of the invention.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
Referring to fig. 2 and fig. 3, an embodiment of the invention provides a wide-viewing-angle pixel structure, including: a scanning line group and a data line group which are vertically arranged, and two pixel regions formed by the scanning line group and the data line group, wherein the scanning line group comprises a first scanning line 11, a second scanning line 12 and a third scanning line 13 which are sequentially arranged in parallel, and the data line group comprises a first data line 21 and a second data line 22 which are arranged in parallel; the first scanning line 11, the second scanning line 12, the first data line 21 and the second data line 22 form a first pixel region; the second scanning line 12, the third scanning line 13, the first data line 21 and the second data line 22 form a second pixel region; the first pixel region includes a first main region 1 and a first sub region 2, the second pixel region includes a second main region 3, a second sub region 4, and a first thin film transistor TFT1, and the first sub region 2 and the second sub region 4 are connected through a first thin film transistor TFT 1.
The first scan line 11, the second scan line 12, and the third scan line 13 are parallel to each other, and the second scan line 12 is located between the first scan line 11 and the third scan line 13. The first pixel area and the second pixel area are two pixel areas which are adjacent up and down, the first sub-area 2 and the second sub-area 4 are connected through the first thin film transistor TFT1, the first thin film transistor TFT1 discharges the first sub-area 2 and the second sub-area 4 in the first pixel area and the second pixel area, the potential of the first sub-area 2 and the second sub-area 4 relative to a common line is reduced, when the liquid crystal display panel is actually lighted, the first main area 1 and the second main area 3 are brighter, the first sub-area 2 and the second sub-area 4 are darker, each pixel area (the first pixel area or the second pixel area) is provided with 8 liquid crystal inversion directions, and therefore a wide view angle is achieved. Since the first sub-area 2 and the second sub-area 4 are connected through the first TFT1, the first TFT1 can discharge the first sub-area 2 and the second sub-area 4 simultaneously, so that the above structure can reduce the number of TFTs on the premise of achieving a wide viewing angle, which is beneficial to achieving a high aperture ratio.
In an embodiment of the present invention, the first sub-area 2 includes a second thin film transistor TFT2 and a first sub-area pixel electrode 20, wherein a gate of the second thin film transistor TFT2 is connected to the first scan line 11, a source of the second thin film transistor TFT2 is connected to the first data line 21, and a drain of the second thin film transistor TFT2 is connected to the first sub-area pixel electrode 20 and a drain of the first thin film transistor TFT1, respectively.
The first thin film transistor TFT1 is simultaneously connected to the first sub-area 2 and the second sub-area 4, and thus the first sub-area 2 and the second sub-area 4 can be simultaneously discharged through the first thin film transistor TFT1 so that the potentials of the first sub-area 2 and the second sub-area 4 are lower than those of the first main area 1 and the second main area 3, respectively, so that for each pixel area (the first pixel area or the second pixel area), the liquid crystal in 8 can be inverted, thereby achieving a wide viewing angle, reducing the number of thin film transistors, and achieving a high aperture ratio. In addition, because the first sub-area 2 and the second sub-area 4 are discharged by using the structure, compared with the prior art, the discharge of the first sub-area 2 or the second sub-area 4 is not required to be realized by being connected with a shared capacitor, so the structure also reduces the use of the shared capacitor, and further improves the aperture ratio.
In another embodiment of the present invention, the second sub-area 4 comprises a third TFT3 and a second sub-area pixel electrode 40, the gate of the third TFT3 is connected to the second scan line 12, the drain of the third TFT3 is connected to the second sub-area pixel electrode 40, the source of the third TFT3 and the source of the first TFT1 are both connected to the second data line 22, and the gate of the first TFT1 is connected to the third scan line 13.
Further, the polarities of the first sub-area pixel electrode 20 and the second sub-area pixel electrode 40 are opposite.
In yet another embodiment of the present invention, the second main region 3 includes the second main region pixel electrode 30 and a fourth thin film transistor TFT4, wherein a gate of the fourth thin film transistor TFT4 is connected to the second scan line 12, a drain of the fourth thin film transistor TFT4 is connected to the second main region pixel electrode 30, and a source of the fourth thin film transistor TFT4 is connected to the second data line 22.
Further, the polarity of the second main region pixel electrode 30 is the same as that of the second sub-region pixel electrode 40.
In a specific embodiment of the present invention, the first main region 1 includes a first main region 1 pixel electrode and a fifth thin film transistor TFT5, wherein a gate of the fifth thin film transistor TFT5 is connected to the first scan line 11, a source of the fifth thin film transistor TFT5 is connected to the first data line 21, and a drain of the fifth thin film transistor TFT5 is connected to the first main region 1 pixel electrode.
Further, the first main region pixel electrode 10 and the first sub-region pixel electrode 20 have the same polarity.
When the above-described structure is operated, first, the charging of the corresponding pixel regions (the first main region 1 and the first sub region 2) connected to the first scan line 11 is completed, and the pixel electrodes connected to the first scan line 11 and the first data line 21 are positive in polarity in the drawing. When the first scan line 11 is turned on, the first main area 1 pixel electrode and the first sub-area pixel electrode 20 on the first scan line 11 are simultaneously charged with a negative polarity. Then the first scan line 11 is turned off, the second scan line 12 is turned on, and the second main area pixel electrode 30 and the second sub area pixel electrode 40 on the second scan line 12 are charged with a positive polarity. At the same time, the first thin film transistor TFT1 is turned on to discharge the first and second sub-area pixel electrodes 20 and 40 on the first and second scan lines 11 and 12. The control of the potential of the pixel electrodes (the first sub-area pixel electrodes 20 and the second sub-area pixel electrodes 40) of the sub-areas of the pixel area is realized by controlling the size of the first thin film transistor TFT1 and the on time of each scan line (the first scan line 11, the second scan line 12, and the third scan line 13).
An embodiment of the present invention further provides an array substrate, including: the wide viewing angle pixel structure in the above embodiments is disposed on a substrate.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (6)
1. A wide view pixel structure, comprising: the pixel structure comprises a scanning line group, a data line group and two pixel regions, wherein the scanning line group and the data line group are vertically arranged, the two pixel regions are formed by the scanning line group and the data line group, the scanning line group comprises a first scanning line, a second scanning line and a third scanning line which are sequentially arranged in parallel, and the data line group comprises a first data line and a second data line which are arranged in parallel; the first scanning line, the second scanning line, the first data line and the second data line form a first pixel area; the second scanning line, the third scanning line, the first data line and the second data line form a second pixel region; the first pixel region comprises a first main region and a first sub region, the second pixel region comprises a second main region, a second sub region and a first thin film transistor, and the first sub region and the second sub region are connected through the first thin film transistor; the first sub-area comprises a second thin film transistor and a first sub-area pixel electrode, wherein the grid electrode of the second thin film transistor is connected with the first scanning line, the source electrode of the second thin film transistor is connected with the first data line, and the drain electrode of the second thin film transistor is respectively connected with the first sub-area pixel electrode and the drain electrode of the first thin film transistor; the second sub-area comprises a third thin film transistor and a second sub-area pixel electrode, the grid electrode of the third thin film transistor is connected with the second scanning line, the drain electrode of the third thin film transistor is connected with the second sub-area pixel electrode, the source electrode of the third thin film transistor and the source electrode of the first thin film transistor are both connected with the second data line, and the grid electrode of the first thin film transistor is connected with the third scanning line; the polarity of the first sub-area pixel electrode is opposite to that of the second sub-area pixel electrode; when the pixel structure works, the first scanning line is firstly opened to charge the first main area pixel electrode and the first sub area pixel electrode, then the first scanning line is closed, and the second scanning line and the third scanning line are simultaneously opened to charge the second main area pixel electrode and the second sub area pixel electrode and discharge the first sub area pixel electrode and the second sub area pixel electrode.
2. The wide-view pixel structure of claim 1, wherein the second main region comprises a second main region pixel electrode and a fourth thin film transistor, wherein a gate of the fourth thin film transistor is connected to the second scan line, a drain of the fourth thin film transistor is connected to the second main region pixel electrode, and a source of the fourth thin film transistor is connected to the second data line.
3. The wide view pixel structure of claim 1, wherein the first main region includes a first main region pixel electrode and a fifth thin film transistor, wherein a gate of the fifth thin film transistor is connected to the first scan line, a source of the fifth thin film transistor is connected to the first data line, and a drain of the fifth thin film transistor is connected to the first main region pixel electrode.
4. The wide-viewing-angle pixel structure of claim 2, wherein the second main-region pixel electrode and the second sub-region pixel electrode have the same polarity.
5. The wide-viewing-angle pixel structure of claim 3, wherein the first main-region pixel electrode and the first sub-region pixel electrode have the same polarity.
6. An array substrate, comprising: a substrate base plate and a wide view pixel structure according to any one of claims 1-5, wherein the wide view pixel structure is disposed on the substrate base plate.
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| CN201611245381.5A CN106773404B (en) | 2016-12-29 | 2016-12-29 | Wide-viewing-angle pixel structure and array substrate |
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| CN106773404B true CN106773404B (en) | 2020-09-08 |
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| CN107861278B (en) * | 2017-12-26 | 2020-01-03 | 昆山龙腾光电股份有限公司 | Liquid crystal display device having a plurality of pixel electrodes |
| CN110346995B (en) * | 2019-07-26 | 2021-07-27 | 苏州华星光电技术有限公司 | Array substrate |
| CN110931512B (en) * | 2019-11-27 | 2022-05-31 | 深圳市华星光电半导体显示技术有限公司 | Display panel and electronic device |
| CN111240106A (en) * | 2020-03-12 | 2020-06-05 | Tcl华星光电技术有限公司 | Display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015125365A (en) * | 2013-12-27 | 2015-07-06 | 株式会社ジャパンディスプレイ | Liquid crystal display |
| CN105045009A (en) * | 2015-08-24 | 2015-11-11 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015125365A (en) * | 2013-12-27 | 2015-07-06 | 株式会社ジャパンディスプレイ | Liquid crystal display |
| CN105045009A (en) * | 2015-08-24 | 2015-11-11 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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