JP4592384B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device and a driving method thereof.

  Conventionally, a TN mode liquid crystal display device has been used, but the use of a VA mode or IPS mode liquid crystal display device having better viewing angle characteristics than the TN mode is spreading. In recent years, MVA mode or S-IPS mode liquid crystal display devices with further improved viewing angle characteristics have been used for TVs and monitors.

  The VA mode using the vertical alignment type liquid crystal layer has an advantage that a display with a high contrast ratio can be realized because the quality of black display is higher than that of the IPS mode. However, it has a drawback that the viewing angle dependency of the γ characteristic is larger than that of the IPS mode.

  Therefore, Patent Document 1 proposes a method of averaging the viewing angle dependency in the γ characteristic by dividing each pixel into a plurality of sub-pixels and supplying a different voltage for each sub-pixel. The liquid crystal display device described in Patent Document 1 has a configuration in which a display signal voltage is independently supplied to each of a plurality of subpixels included in a pixel. That is, when a pixel has two subpixels (a first subpixel and a second subpixel), a display signal voltage is supplied to the second subpixel separately from the source bus line that supplies the display signal voltage to the first subpixel. It is necessary to provide a source bus line. Therefore, dividing the pixel into two doubles the number of source bus lines and source driving circuits. Two different display signal voltages supplied from the first subpixel and the second subpixel are determined in advance for each data to be displayed, and are stored in a lookup table.

On the other hand, Patent Document 2 and Patent Document 3 describe a liquid crystal display device including a plurality of sub-pixels having different luminances with respect to a certain supplied display signal voltage. In this liquid crystal display device, since the common display signal voltage is supplied from the common source bus line to the first sub-pixel and the second sub-pixel, the number of source bus lines and source driving circuits is set according to the number of divisions. It has the advantage that there is no need to increase it.
JP 2003-295160 A JP 2004-62146 A JP 2004-78157 A JP-A-6-332009

  However, when the present inventors prototyped and evaluated the liquid crystal display devices described in Patent Documents 2 and 3, sufficient reliability may not be obtained, and this decrease in reliability is caused by a DC voltage applied to the liquid crystal layer. It was found that this is due to the application of.

  In general, the liquid crystal display device is AC driven to prevent a DC voltage from being applied to the liquid crystal layer regardless of the display mode. That is, by driving the direction of the electric field generated in the liquid crystal layer at regular intervals, the electric field (DC voltage) in a certain direction is driven so as not to remain when time averaged. The voltage applied to the liquid crystal layer of each pixel of the active matrix liquid crystal display device corresponds to the difference between the common voltage (Vcom) supplied to the counter electrode and the display signal voltage supplied to the pixel electrode. In this case, the polarity of the display signal voltage when the common voltage supplied to the counter electrode is used as a reference is inverted every certain time. The period for inverting the polarity of the display signal voltage is, for example, one vertical scanning period (typically one frame period of the input image signal).

  In an active matrix liquid crystal display device using a transistor, a voltage called “pull-in voltage (drain pull-in voltage)” due to the influence of parasitic capacitance (Cgd) between the gate and the drain immediately after the transistor is turned off. Is applied to the liquid crystal layer. The pull-in voltage depends on the size of the liquid crystal capacitance (capacitance composed of sub-pixel electrode / liquid crystal layer / counter electrode, pixel capacitance is composed of liquid crystal capacitance and auxiliary capacitance), and the liquid crystal capacitance depends on voltage. To do. Therefore, in order to prevent the generation of the DC voltage due to the pull-in voltage, the display signal voltage is set so as to cancel the pull-in voltage for each data (image data, input image signal) to be displayed.

  However, in a liquid crystal display device including a plurality of sub-pixels having different luminances with respect to one supplied display signal voltage as described in Patent Document 2 and Patent Document 3 described above, for each sub-pixel, Since the applied voltage to be supplied cannot be adjusted, the generation of DC due to the pull-in voltage cannot be prevented, and sufficient reliability may not be obtained.

  The present invention has been made to solve the above-described problems, and its main object is to improve the reliability of a liquid crystal display device having a pixel division structure.

  The liquid crystal display device of the present invention includes a liquid crystal layer, a plurality of electrodes for applying a voltage to the liquid crystal layer, and a pixel whose luminance changes in accordance with a display signal voltage supplied through a transistor, A liquid crystal display device having a first sub-pixel having a first luminance and a second sub-pixel having a second luminance lower than the first luminance with respect to one supplied display signal voltage. The pull-in voltage of the first subpixel is substantially equal to the pull-in voltage of the second subpixel.

  In one embodiment, each of the first subpixel and the second subpixel includes a counter electrode, a liquid crystal capacitor formed by a subpixel electrode facing the counter electrode via the liquid crystal layer, and the subpixel An auxiliary capacitance formed by an auxiliary capacitance electrode electrically connected to the pixel electrode, an insulating layer, and an auxiliary capacitance counter electrode facing the auxiliary capacitance electrode via the insulating layer, and the counter electrode Is a single electrode common to the first subpixel and the second subpixel, and the storage capacitor counter electrode is electrically independent for each of the first subpixel and the second subpixel. A first transistor and a second transistor provided corresponding to each of the first sub-pixel and the second sub-pixel, wherein the first transistor and the second transistor have a common gate bus The sub-pixels of each of the first sub-pixel and the second sub-pixel are turned on / off by a scanning signal voltage supplied to the pixel and the first transistor and the second transistor are in an on-state. After the display signal voltage is supplied to the electrode and the auxiliary capacitance electrode from a common source bus line, and the first transistor and the second transistor are turned off, the first subpixel and the second subpixel The voltage of each auxiliary capacitance counter electrode changes, and the amount of change defined by the direction and magnitude of the change differs between the first subpixel and the second subpixel.

A liquid crystal display device according to a preferred embodiment includes a liquid crystal layer, a plurality of electrodes for applying a voltage to the liquid crystal layer, and a pixel whose luminance changes according to a display signal voltage supplied through a transistor, A liquid crystal display device in which a pixel has a first sub-pixel having a first luminance and a second sub-pixel having a second luminance lower than the first luminance with respect to a certain supplied display signal voltage. Each of the first subpixel and the second subpixel includes a counter electrode, a liquid crystal capacitor formed by a subpixel electrode facing the counter electrode through the liquid crystal layer, and the subpixel electrode. An auxiliary capacitance formed by an auxiliary capacitance electrode electrically connected to the auxiliary capacitance electrode, an insulating layer, and an auxiliary capacitance counter electrode facing the auxiliary capacitance electrode via the insulating layer, The first sub-pixel and the first sub-pixel; A single electrode common to the sub-pixels, and the auxiliary capacitor counter electrode is electrically independent for each of the first sub-pixel and the second sub-pixel, and the first sub-pixel and the second sub-pixel The first transistor and the second transistor are provided corresponding to each of the sub-pixels, and the first transistor and the second transistor are on / off controlled by a scanning signal voltage supplied to a common gate bus line. When the first transistor and the second transistor are in the ON state, a common source bus line is used for the sub-pixel electrode and the auxiliary capacitance electrode of each of the first sub-pixel and the second sub-pixel. After the display signal voltage is supplied from the first transistor and the second transistor are turned off, the first subpixel and the second transistor are turned off. The voltage of the storage capacitor counter electrode of each sub-pixel changes, and the amount of change defined by the direction and magnitude of the change differs between the first sub-pixel and the second sub-pixel, In the first sub-pixel and the second sub-pixel, the difference between the sub-pixel pull-in voltage and the second sub-pixel pull-in voltage is reduced.
(1) The area where the drain of the transistor overlaps with the gate bus line is different.
(2) The area where the sub-pixel electrode overlaps the common source bus line is different.
(3) The area where the sub-pixel electrode overlaps with the source bus line connected to the pixel adjacent in the row direction is different.
(4) The capacitances of the auxiliary capacitors are different.
(5) The area where the CS bus line connected to the storage capacitor counter electrode overlaps the sub-pixel electrode is different.
(6) At least one of the thicknesses of the liquid crystal layers is satisfied.

  In one embodiment, the liquid crystal layer is a vertical alignment type liquid crystal layer. Preferably, the liquid crystal layer has a plurality of domains for each of the pixels.

  In one embodiment, the area of the first subpixel is smaller than the area of the second subpixel. In this case, at least one of (1) to (6) is adjusted to reduce the pull-in voltage of the first subpixel. In one embodiment, the area of the second subpixel is not less than three times the area of the first subpixel.

  The liquid crystal display device of the present invention includes two sub-pixels (bright sub-pixel and dark sub-pixel) whose pixels have different luminances, thereby improving the viewing angle dependency of the γ characteristic. There are various pixel division methods. For example, when the method described in Patent Document 2 or 3 is adopted, two subpixels having different luminances with respect to a certain supplied display signal voltage. Can be obtained with a relatively simple configuration. Further, since the pull-in voltages of the bright subpixel and the dark subpixel are set to be substantially equal to each other, the generation of the DC voltage is suppressed, and the reliability of the liquid crystal display device is improved. In particular, by applying the pixel division technique, the reliability and / or display quality of a VA mode liquid crystal display device in which the viewing angle dependency of the γ characteristic is improved can be improved. The liquid crystal display device of the present invention is particularly suitable for a large liquid crystal television.

  Hereinafter, a configuration of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

  The liquid crystal display device according to the embodiment of the present invention has a pixel division structure as schematically shown in FIG. That is, one pixel P shown in FIG. 1B is divided into two subpixels SP1 and SP2, and the luminance of each of the subpixels SP1 and SP2 is varied within a certain range, so that Improve viewing angle dependency. Here, two divisions are illustrated, but the number of subpixels (number of divisions) is not particularly limited. The bright sub-pixel and the dark sub-pixel do not mean that the brightness of the bright sub-pixel is higher than the brightness of the dark sub-pixel in all gradations. It is sufficient that the luminance is higher than that of the dark subpixel. For example, when the pixel division technique described in Patent Document 2 is employed, as will be described later, when displaying black (minimum luminance) and white (maximum luminance), there is no luminance between sub-pixels, and luminance in halftones. The difference increases (see FIG. 6).

  When the pixel division technique described in Patent Document 2 is applied to a VA mode liquid crystal display device, the area ratio of the bright sub-pixel and the dark sub-pixel is the area of the bright sub-pixel (here, SP1) as shown in FIG. Patent Document 2 describes that the smaller the dark sub-pixel (here, SP2), the γ characteristic at an oblique viewing angle is further improved. Note that the “pixel” in this specification refers to the minimum unit that the liquid crystal display device performs display, and in the case of a color display device, “pixel” that displays individual colors (typically R, G, or B). (Or dot) ".

  First, the pixel division configuration of the liquid crystal display device according to the embodiment of the present invention will be described. Various configurations have been proposed in order to provide a plurality of subpixels having different luminances, but the liquid crystal display device of this embodiment is a VA mode liquid crystal display having a pixel division configuration described in Patent Document 2. Device.

  FIG. 3 schematically shows an electrical configuration of a pixel included in the liquid crystal display device according to the embodiment of the present invention. Here, a two-divided structure is illustrated, but is not limited thereto.

  As shown in FIG. 3, the pixel P is divided into a sub-pixel SP1 and a sub-pixel SP2. Corresponding TFTs 14a and 14b and auxiliary capacitors CS1 and CS2 are connected to the subpixel electrodes 11a and 11b constituting the subpixels SP1 and SP2, respectively. The gate electrodes of the TFTs 14 a and 14 b are connected to a common gate bus line (scanning line) 12, and the source electrodes of the TFTs 14 a and 14 b are connected to a common (identical) source bus line (signal line) 13. The auxiliary capacitors CS1 and CS2 are connected to the corresponding CS bus line (auxiliary capacitor line) 15a and CS bus line 15b, respectively. The auxiliary capacitors CS1 and CS2 are provided between the auxiliary capacitor electrode electrically connected to the sub-pixel electrodes 11a and 11b, the auxiliary capacitor counter electrode electrically connected to the CS bus lines 15a and 15b, respectively. The insulating layer (not shown, for example, a gate insulating film) is formed. The auxiliary capacitor counter electrodes of the auxiliary capacitors CS1 and CS2 are independent from each other, and have a structure in which different auxiliary capacitor counter voltages (also referred to as “CS signals”) can be supplied from the CS bus lines 15a and 15b, respectively. . In the example shown later, a part of the CS bus line constitutes a storage capacitor counter electrode.

  After the display signal voltage is supplied from the common source bus line 13 to the subpixel electrode 11a and the subpixel electrode 11b and the TFTs 14a and 14b are turned off, the voltages of the auxiliary capacitor counter electrodes of the auxiliary capacitors CS1 and CS2 (that is, , The voltage supplied from the CS bus line 15a or the CS bus line 15b) (by the direction and magnitude of the change) are changed to be applied to the liquid crystal capacitors of the respective subpixels SP1 and SP2. Thus, a state in which the effective voltage is different, that is, a state in which the luminance is different is obtained. When this configuration is adopted, a display signal voltage can be supplied from one source bus line 13 to the two subpixels SP1 and SP2, so that the number of subbuses and source drivers can be increased without increasing the number of source bus lines and the number of source drivers. The brightness of the pixels SP1 and SP2 can be made different from each other.

  Next, a driving method of the liquid crystal display device will be described with reference to FIG. 5 showing an equivalent circuit of the liquid crystal display device shown in FIG. 4 and voltage waveforms (timing) of each signal.

  In the voltage waveform shown in FIG. 5, the sub-pixel SP1 is a bright sub-pixel and the sub-pixel SP2 is a dark sub-pixel. Vg is a gate voltage, Vs is a source voltage, Vcs1 and Vcs2 are voltages of auxiliary capacitors of the subpixel SP1 and the subpixel SP2, and Vlc1 and Vlc2 are voltages of pixel electrodes of the subpixel SP1 and the subpixel SP2, respectively. In general, AC driving such as frame inversion, line inversion, and dot inversion is performed so that the liquid crystal is not polarized.

  In this embodiment, as shown in FIG. 5, with respect to the median value Vsc of the source voltage in the nth frame, Vsp is given to the source voltage as positive polarity, and Vsn is given to the source voltage as negative polarity in the next (n + 1) th frame. In addition, dot inversion driving is performed for each frame. A signal obtained by amplifying the voltage with the amplitude voltage Vad and shifting the phases of CS1 and CS2 by 180 degrees is input to CS1 and CS2.

  First, with reference to FIG. 5, the change with time of the voltage of each signal at the nth frame will be described.

  At time T1, Vg changes from VgL to VgH, the TFTs of both subpixels are turned on, and the subpixel SP1, subpixel SP2, and auxiliary capacitors CS1 and CS2 are charged with the voltage Vsp.

At time T2, Vg changes from VgH to VgL, the TFTs of both subpixels are turned off, and the subpixel SP1, subpixel SP2 and auxiliary capacitors CS1, CS2 are electrically insulated from the source bus line. Immediately after this, due to the pull-in phenomenon due to the influence of the parasitic capacitance or the like, pull-in voltages of Vd1 and Vd2 are generated in the subpixel SP1 and the subpixel SP2, respectively, and the voltage of each subpixel is Vlc1 = Vsp−Vd1.
Vlc2 = Vsp−Vd2
It becomes.

At this time,
Vcs1 = Vcom−Vad
Vcs2 = Vcom + Vad
It is.

  The pull-in voltages Vd1 and Vd2 are expressed by the following equations.

Vd1, Vd2 = (VgH−VgL) × Cgd / (Clc (V) + Cgd + Ccs)
Here, VgH and VgL are voltages when the TFT is turned on and off, Cgd is a parasitic capacitance generated between the gate and drain of the TFT, Clc (V) is a capacitance (capacitance value) of liquid crystal capacitance, and Ccs is Indicates the capacitance (capacitance value) of the auxiliary capacitor.

Next, at time T3, the voltage Vcs1 of the CS bus line CS1 changes from Vcom−Vad to Vcom + Vad, and the voltage of the CS bus line CS2, Vcs2 changes from Vcom + Vad to Vcom−Vad. At this time, the pixel voltages Vlc1 and Vlc2 of each sub-pixel are
Vlc1 = Vsp−Vd1 + 2 × K × Vad
Vlc2 = Vsp−Vd2-2 × K × Vad
It becomes. However, K = Ccs / (Clc (V) + Ccs).

At time T4, Vcs1 changes from Vcom + Vad to Vcom−Vad, and Vcs2 changes from Vcom−Vad to Vcom + Vad. At this time, the subpixel voltages Vlc1 and Vlc2 are
Vlc1 = Vsp−Vd1
Vlc2 = Vsp−Vd2
It becomes.

At time T5, Vcs1 changes from Vcom−Vad to Vcom + Vad, and Vcs2 changes from Vcom + Vad to Vcom−Vad. At this time, the subpixel voltages Vlc1 and Vlc2 are
Vlc1 = Vsp−Vd1 + 2 × K × Vad
Vlc2 = Vsp−Vd2-2 × K × Vad
It becomes.

Thereafter, Vcs1, Vcs2, Vlc1, and Vlc2 alternately repeat time T4 and time T5 for every integral multiple of the horizontal scanning period 1H until Vg = VgH and writing is performed. Therefore, the effective values of Vlc1 and Vlc2 are
Vlc1 = Vsp−Vd1 + K × Vad
Vlc2 = Vsp−Vd2−K × Vad
It becomes.

In the nth frame, the effective voltage applied to the liquid crystal layer of each subpixel is
V1 = Vsp−Vd1 + K × Vad−Vcom
V2 = Vsp−Vd2−K × Vad−Vcom
Therefore, the subpixel SP1 is a bright subpixel and the subpixel SP2 is a dark subpixel.

  Next, the change with time of the voltage of each signal at the (n + 1) th frame will be described.

  In the (n + 1) frame, Vs is inverted in order to invert the polarity. Therefore, at time T1, Vg changes from VgL to VgH, the TFTs of both subpixels are turned on, and the auxiliary capacitors CS1 and CS2 are charged with the voltage Vsn.

At time T2, as in the nth frame, the TFTs of both subpixels are turned off. Immediately after this, the pull-in voltages of Vd1 and Vd2 are generated in the subpixel SP1 and the subpixel SP2, respectively.
Vlc1 = Vsn-Vd1
Vlc2 = Vsn-Vd2
It becomes.

At time T3, the voltage Vcs1 of the CS bus line CS1 changes from Vcom + Vad to Vcom−Vad, and the voltage Vcs2 of the CS bus line CS2 changes from Vcom−Vad to Vcom + Vad. At this time, the pixel voltages Vlc1 and Vlc2 of each sub-pixel are
Vlc1 = Vsn−Vd1-2 × K × Vad
Vlc2 = Vsn−Vd2 + 2 × K × Vad
It becomes.

At time T4, Vcs1 changes from Vcom−Vad to Vcom + Vad, and Vcs2 changes from Vcom + Vad to Vcom−Vad. At this time, the subpixel voltages Vlc1 and Vlc2 are
Vlc1 = Vsn-Vd1
Vlc2 = Vsn-Vd2
It becomes.

At time T5, Vcs1 changes from Vcom + Vad to Vcom−Vad, and Vcs2 changes from Vcom−Vad to Vcom + Vad. At this time, the subpixel voltages Vlc1 and Vlc2 are
Vlc1 = Vsn−Vd1-2 × K × Vad
Vlc2 = Vsn−Vd2 + 2 × K × Vad
It becomes.

Thereafter, as in the case of the n frame, Vcs1, Vcs2, Vlc1, and Vlc2 alternately repeat time T4 and time T5. Therefore, the effective values of Vlc1 and Vlc2 are
Vlc1 = Vsn−Vd1−K × Vad
Vlc2 = Vsn−Vd2 + K × Vad
It becomes.

The effective voltage applied to the liquid crystal layer of each subpixel of the (n + 1) th frame is
V1 = Vsn−Vd1−K × Vad−Vcom
V2 = Vsn−Vd2 + K × Vad−Vcom
Therefore, the subpixel SP1 is a bright subpixel and the subpixel SP2 is a dark subpixel.

  Further, as schematically shown in FIG. 6, the pixel division configuration described in Patent Document 2 has a bright subpixel and a dark subpixel in low gradation (low luminance) and high gradation (high luminance) display. There is almost no difference in luminance from the pixels (that is, corresponding to the effective voltage applied to the liquid crystal layer), and there is a difference in luminance between the bright subpixel and the dark subpixel in the halftone display. Effectively improves the viewing angle dependency of the γ characteristic of the mode.

  However, if this configuration is adopted, the display signal voltage cannot be adjusted independently for each sub-pixel as described above, and the pull-in voltage Vd cannot be canceled for both sub-pixels, and a DC voltage is applied. Problem occurs.

  Here, this phenomenon will be described in detail.

  The pull-in voltage Vd is expressed by the following equation (1). Here, VgH and VgL are voltages when the TFT is turned on and off, Cgd is a parasitic capacitance generated between the gate and drain of the TFT, Clc (V) is a capacitance (capacitance value) of liquid crystal capacitance, and Ccs is Indicates the capacitance (capacitance value) of the auxiliary capacitor. Note that the capacitance Clc of the liquid crystal capacitance depends on the magnitude of the voltage applied to the liquid crystal layer. This is because the orientation direction of the liquid crystal molecules having dielectric anisotropy changes depending on the voltage, and the capacitance of the liquid crystal capacitance varies depending on the luminance to be displayed. In general, as the voltage applied to the liquid crystal layer increases, the dielectric constant of the liquid crystal layer increases, and thus the capacitance of the liquid crystal capacitor increases.

  Vd = (VgH−VgL) × Cgd / (Clc (V) + Cgd + Ccs) (1)

  As can be seen from the equation (1), the pull-in voltage Vd depends on the capacitance of the liquid crystal capacitance, that is, depends on the luminance (gradation) to be displayed.

  Since Vd varies depending on the gradation, the DC level of the drain voltage (also referred to as the median value of the potential of the subpixel electrode in the case of AC driving, or the effective level of the drain voltage) varies depending on the gradation. Accordingly, when the level of the counter voltage is made constant for all gradations, a gradation in which a DC component is applied to the liquid crystal layer is generated. In order to prevent this, conventionally, the median value of the display signal voltage (source voltage or drain voltage) (the median value of the potential of the sub-pixel electrode in the case of AC driving at each gradation) is determined according to the gradation. Vd is compensated so that the DC level of the drain voltage substantially coincides with the counter voltage so that no DC component is applied to the liquid crystal layer.

  However, when the above-described pixel division technique is employed, Vd is different between the subpixel SP1 (here, the bright subpixel) and the subpixel SP2 (here, the dark subpixel), so that the DC level of the drain voltage of the subpixel SP1 is set to be lower. When matched with the counter voltage, the DC level of the drain voltage of the subpixel SP2 does not match the counter voltage, and a DC component is applied to the liquid crystal layer of the subpixel SP2. In this way, a DC component is applied to the liquid crystal layer (and the alignment film) of at least one sub-pixel to cause polarization. As a result, a problem occurs in the reliability of the liquid crystal display device.

  Next, in order to estimate the pull-in voltage Vd of each subpixel, the capacitance connected to the subpixel electrode is calculated in consideration of the parasitic capacitance. 7A and 7B show the capacitors connected to the sub-pixel electrodes and their names, and FIG. 8 shows an equivalent circuit diagram.

  When the parasitic voltage connected to the subpixel electrode of each subpixel is taken into consideration and the pull-in voltage Vd of each subpixel is calculated, the following equation (2) is obtained. The superscripts 1 and 2 of each parameter in the equation (2) indicate that they correspond to the first subpixel SP1 and the second subpixel SP2, respectively. Cgd is a parasitic capacitance between the gate and drain (subpixel electrode), Csd is a parasitic capacitance between the source and drain (subpixel electrode) ((self) is a source (source) for supplying a signal voltage to the subpixel electrode. (Other) means a source bus line connected to a pixel adjacent to the pixel to which the subpixel electrode belongs in the row direction.

As shown in FIGS. 7A and 7B, each of the auxiliary capacitors CS1 and CS2 includes an auxiliary capacitor counter electrode / an insulating film / an auxiliary capacitor electrode, and the auxiliary capacitor counter electrode is a CS bus line. The auxiliary capacitance electrodes 16a and 16b are formed by extending portions of the drain electrodes D1 and D2. Insulating film 17 is, for example, a gate insulating film formed of an inorganic insulating film such as SiN _x. The subpixel electrodes 11a and 11b are electrically connected to the drain electrodes D1 and D2, respectively. For example, the subpixel electrodes 11a and 11b are connected to the auxiliary capacitance electrodes 16a and 16b, respectively. Here, a configuration in which the subpixel electrodes 11a and 11b are provided on the interlayer insulating film 19 covering the drain electrodes D1 and D2 and the auxiliary capacitance electrodes 16a and 16b is adopted, and the auxiliary capacitance electrodes 16a and 16b and the subpixel are provided. For example, the electrodes 11a and 11b are electrically connected in a contact hole (not shown) formed in the interlayer insulating film 19. The interlayer insulating film 19 is formed using a transparent photosensitive resin.

  When such a configuration is adopted, as shown in FIG. 7B, the original auxiliary capacitance Ccs1 (here, Ccs1 (D)) formed between the auxiliary capacitance electrode 16a and the auxiliary capacitance counter electrode 15a is represented. ), A parasitic capacitance Ccs1 (B) is formed between the sub-pixel electrode 11a and the auxiliary capacitance counter electrode 15a. When optimizing the capacitance of the auxiliary capacitance, it is necessary to optimize the capacitances of Ccs1 (D) and Ccs1 (B).

Vd1 = (VgH−VgL) × Cgd1 (self) / (Clc1 (V) + Cgd1 (self)
+ Ccs1 (D) + Ccs1 (B) + Csd1 (self) + Csd1 (other))
Vd2 = (VgH−VgL) × Cgd2 (auto) / (Clc2 (V) + Cgd2 (auto)
+ Ccs2 (D) + Ccs2 (B) + Csd2 (self) + Csd2 (other))
(2)

  In the liquid crystal display device according to the embodiment of the present invention, Clc1 (V), Cgd1 (self), Ccs1 (D), Ccs1 (B), Csd1 (self), and Csd1 of the first subpixel so that Vd1 = Vd2. (Others) and at least one of Clc2 (V), Cgd2 (O), Ccs2 (D), Ccs2 (B), Csd2 (O), and Csd2 (Other) of the second subpixel are adjusted. In the liquid crystal display device of this embodiment, since the gate bus line is provided in common for the two subpixels, (VgH−VgL) is equal.

  Here, the difference in voltage applied to the liquid crystal layer of each sub-pixel is estimated. FIG. 9 shows a graph in which the display signal voltage supplied to each sub-pixel through a transistor, that is, the above-mentioned K value × 2 is plotted against the source voltage Vs. For the calculation of Clc (V), the dielectric constant of a liquid crystal material having a negative dielectric anisotropy for general vertical alignment was used. Further, the value of each Ccs was calculated as ½ of the value of Clc when the source voltage supplied to the sub-pixel electrode is maximum (here, 7.0 V). Of course, the ratio between Ccs and Clc depends on the structure of the pixel and the like, but in a liquid crystal display device currently generally used, Ccs / Clc is 0.5 or more. 5 was used.

  As can be seen from FIG. 9, the voltage difference applied to each sub-pixel is larger when the source voltage is lower, and the voltage difference decreases as the source voltage increases. Since Vd increases as the value of K increases, the pull-in voltage Vd increases when the source voltage is low, and the difference between Vd1 and Vd2 is also large. Therefore, when Vd1 and Vd2 are made substantially equal when the source voltage is low (when black is displayed in the VA mode), Vd1 and Vd2 can be made substantially equal over the entire gradation, resulting in generation of a DC voltage. Can be suppressed.

  A specific example for setting Vd1 = Vd2 in the liquid crystal display device according to the embodiment of the present invention will be described below.

  When the area ratio between the first subpixel SP1 and the second subpixel SP2 is 1: 1 or close to this, the liquid crystal layer of the first subpixel (bright subpixel) is higher than the liquid crystal layer of the second subpixel. Since an effective voltage is applied, Vd1 becomes smaller than Vd2 as can be seen from the above equation (2). Therefore, the above parameters Clc (V), Cgd (self), Ccs (D), Ccs (B), Csd (self), and Csd (others) need to be set to increase Vd1.

  On the other hand, in order to further improve the viewing angle dependency of the γ characteristic, the area of the first subpixel (bright subpixel) is larger than the area of the second subpixel (dark subpixel). When the area ratio with the second subpixel is set to 1: 3 or more, Clc1 becomes smaller than Clc2, and as a result, Vd1 becomes larger than Vd2. In this case, the above parameters Clc (V), Cgd (self), Ccs (D), Ccs (B), Csd (self), and Csd (others) need to be set so as to decrease Vd1. .

  Here, a configuration for reducing Vd1 when the area ratio of the first subpixel and the second subpixel is set to about 1: 3 will be described. Instead of decreasing Vd1, Vd2 may be increased, or Vd1 may be decreased and Vd2 may be increased. Here, decreasing (or increasing) Vd1 is based on a design that does not consider adjusting Vd1.

  In order to reduce Vd1, as can be seen from the above formula (2), Cgd1 of the numerator is reduced, or Clc1 (V), Ccs1 (D), Ccs1 (B), Csd1 (self) and Csd1 of the denominator. What is necessary is just to enlarge at least one of (other).

  In order to reduce Cgd1, for example, as shown in FIG. 10, the area S1 where the drain (drain electrode) of the transistor (TFT1) of the first subpixel SP1 overlaps the gate electrode (gate bus line) is reduced to the second subpixel SP1. The drain of the transistor (TFT2) of the pixel SP2 is made smaller than the area S2 overlapping the gate bus line. FIG. 10A is a plan view schematically showing the pixel configuration of the liquid crystal display device of this embodiment, and FIG. 10B is a plan view schematically showing the structure in the vicinity of the TFT.

As shown in FIG. 10, by reducing the area of the drain (drain electrode) of the TFT 14a, Vd1 and Vd2 can be made equal without changing the transistor characteristics between the TFT 14a and the TFT 14b. Here, the gate electrode, the source electrode, the drain electrode, and the like include those having the same potential as the respective electrodes, the gate electrode includes the gate bus line, the source electrode includes the source bus line, and the drain electrode. Includes sub-pixel electrodes. Further, when the semiconductor layer constituting the TFT has a region (for example, an n ⁺ layer) having the same potential as each electrode, these are included.

  FIG. 11 schematically shows a pixel configuration of another liquid crystal display device of this embodiment. In the example shown in FIG. 11, the parasitic capacitance Csd1 (self) is increased by increasing the area where the source bus line connected to the TFT 14a and the first subpixel electrode 11a overlap, and thereby Vd1 and Vd2 And are equal. Of course, the parasitic capacitance Csd2 (self) may be reduced or used in combination.

  FIG. 12 schematically shows a pixel configuration of still another liquid crystal display device of the present embodiment. In the example shown in FIG. 12, the area where the source bus line connected to the TFT in the column adjacent to the TFT 14a (the source bus line connected to the pixel adjacent in the row direction) and the first subpixel electrode 11a overlaps. By increasing it, the parasitic capacitance Csd1 (others) is increased, thereby making Vd1 and Vd2 equal. Of course, the parasitic capacitance Csd2 (others) may be reduced or used in combination.

  FIG. 13 schematically shows a pixel configuration of still another liquid crystal display device of the present embodiment. In the example shown in FIG. 13, Vd1 and Vd2 are made equal by increasing the capacitance Ccs1 (at least one of Ccs1 (D) and Ccs1 (B)) of the auxiliary capacitance of the first subpixel SP1. . For example, only Ccs1 (B) can be changed by changing the area where the CS bus line overlaps with the sub-pixel electrode. Of course, the auxiliary capacitance Ccs2 (at least one of Ccs2 (D) and Ccs2 (B)) of the auxiliary capacitance of the second subpixel SP2 may be reduced or used together.

  FIG. 14 schematically shows a pixel configuration of still another liquid crystal display device of the present embodiment. In the example shown in FIG. 14, Clc1 (V) is increased by decreasing the thickness d1 of the liquid crystal layer of the first subpixel SP1, thereby making Vd1 and Vd2 equal. Of course, Clc2 (V) may be reduced or used in combination.

  Since the liquid crystal capacitance Clc is proportional to the dielectric constant of the liquid crystal layer and the electrode area (subpixel area) and inversely proportional to the thickness of the liquid crystal layer, the dielectric constant of the liquid crystal layer may be changed.

  The configurations described with reference to FIGS. 10 to 14 may be used alone, or two or more arbitrary configurations selected from these may be appropriately combined.

  Here, the configuration for reducing Vd1 has been described, but conversely, the configuration for increasing Vd1 is Clc1 (V), Cgd1 (self), Ccs1 (D), Ccs1 (B) of the first subpixel. ), Csd1 (self), Csd1 (other) and at least one of Clc2 (V), Cgd2 (self), Ccs2 (D), Ccs2 (B), Csd2 (self), and Csd2 (other) of the second subpixel. Since the relationship between the above and the above description may be reversed, the description is omitted.

  According to the present invention, by applying the pixel division technique, it is possible to improve the reliability of the VA mode liquid crystal display device in which the viewing angle dependency of the γ characteristic is improved. The liquid crystal display device of the present invention is particularly suitable for a large liquid crystal television.

(A) is a schematic diagram which shows the pixel division structure which the liquid crystal display device of embodiment by this invention has, (b) is a schematic diagram which shows a normal pixel. It is a schematic diagram for explaining that the γ characteristic at an oblique viewing angle is further improved when the area of the bright subpixel (SP1) is smaller than that of the dark subpixel (SP2). It is a figure which shows typically the electric constitution of the pixel which the liquid crystal display device of embodiment by this invention has. It is a figure which shows the equivalent circuit of the liquid crystal display device of embodiment by this invention. FIG. 5 is a diagram showing voltage waveforms and timings of signals for driving the liquid crystal display device shown in FIG. 4. It is a schematic diagram for demonstrating the gradation dependence of the luminance difference of a 1st subpixel (bright subpixel) and a 2nd subpixel (dark subpixel). It is a figure which shows the capacity | capacitance and name which were connected to each sub-pixel electrode in the liquid crystal display device of embodiment by this invention, (a) is a top view, (b) is along 7b-7b 'line in (a). FIG. It is an equivalent circuit diagram including the parasitic capacitance of the liquid crystal display device of the embodiment according to the present invention. It is the graph which plotted the value x2 of the above-mentioned K (= Ccs / (Clc (V) + Ccs)) with respect to the source voltage supplied to each sub pixel. (A) is a top view which shows typically the pixel structure of the liquid crystal display device of embodiment by this invention, (b) is a top view which shows typically the structure of the TFT vicinity. It is a figure which shows typically the pixel structure of the other liquid crystal display device of embodiment by this invention. It is a figure which shows typically the pixel structure of the further another liquid crystal display device of embodiment by this invention. It is a figure which shows typically the pixel structure of the further another liquid crystal display device of embodiment by this invention. It is a figure which shows typically the pixel structure of the further another liquid crystal display device of embodiment by this invention, (a) is a top view, (b) is sectional drawing.

Explanation of symbols

11a, 11b Pixel electrode 12 Gate bus line (scanning line)
13 Source bus line (signal line)
14a, 14b TFT
15a, 15b CS bus line (auxiliary capacitance wiring, auxiliary capacitance counter electrode)
16a, 16b Auxiliary capacitance electrode 17 Insulating film 19 Interlayer insulating film SP1 First sub-pixel (bright sub-pixel)
SP2 Second subpixel (dark subpixel)
D1 Drain electrode of TFT 14a D2 Drain electrode of TFT 14b

Claims (4)

A liquid crystal layer; a plurality of electrodes for applying a voltage to the liquid crystal layer; and a pixel whose luminance changes in accordance with a display signal voltage supplied via a transistor, wherein the pixel is supplied with a certain display A liquid crystal display device having a first subpixel having a first luminance with respect to a signal voltage and a second subpixel having a second luminance lower than the first luminance,
Each of the first subpixel and the second subpixel includes a counter electrode and a liquid crystal capacitor formed by a subpixel electrode facing the counter electrode via the liquid crystal layer;
An auxiliary capacitance formed by an auxiliary capacitance electrode electrically connected to the sub-pixel electrode, an insulating layer, and an auxiliary capacitance counter electrode facing the auxiliary capacitance electrode via the insulating layer;
The counter electrode is a single electrode common to the first subpixel and the second subpixel, and the storage capacitor counterelectrode is electrically connected to each of the first subpixel and the second subpixel. Independent
A first transistor and a second transistor provided corresponding to each of the first subpixel and the second subpixel;
The first transistor and the second transistor are on / off controlled by a scanning signal voltage supplied to a common gate bus line, and the first transistor and the second transistor are turned on when the first transistor and the second transistor are in an on state. A display signal voltage is supplied from a common source bus line to the subpixel electrode and the auxiliary capacitance electrode of each of the subpixel and the second subpixel, and the first transistor and the second transistor are turned off. Thereafter, the voltage of the storage capacitor counter electrode of each of the first subpixel and the second subpixel changes, and the amount of change defined by the direction and magnitude of the change is the same as that of the first subpixel. Unlike the second sub-pixel,
In the first subpixel and the second subpixel, the difference between the pull-in voltage of the first subpixel and the pull-in voltage of the second subpixel is reduced.
(1) The area where the drain of the transistor overlaps with the gate bus line is different.
(2) The area where the sub-pixel electrode overlaps the common source bus line is different.
(3) The area where the sub-pixel electrode overlaps with the source bus line connected to the pixel adjacent in the row direction is different.
(4) The capacitances of the auxiliary capacitors are different.
(5) The area where the CS bus line connected to the storage capacitor counter electrode overlaps the sub-pixel electrode is different.
(6) The thickness of the liquid crystal layer is different.
A liquid crystal display device satisfying at least one of the above. The liquid crystal display device according to claim 1 , wherein the liquid crystal layer is a vertical alignment type liquid crystal layer. Area of the first subpixel is smaller than the area of the second subpixel, a liquid crystal display device according to claim 1 or 2. 4. The liquid crystal display device according to claim 3 , wherein at least one of (1) to (6) is adjusted to reduce a pull-in voltage of the first subpixel. 5.

Images