JP3346493B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device in which a plurality of liquid crystal cells are arranged in a matrix.

A liquid crystal display device is a large-scale semiconductor integrated circuit (L).
Due to the rapid advancement and development of SI) technology, it has been widely used in recent years because it can be driven at a low voltage by a normal LSI, has low power consumption, and is small, lightweight and inexpensive. In such a liquid crystal display device, further improvement in display quality and simplification of a panel configuration are desired.

[0003]

2. Description of the Related Art FIG. 18 shows a configuration diagram of an example of a liquid crystal panel of a conventional liquid crystal display device. In the figure, a gate bus line GB for transmitting a scanning voltage and a data bus line (drain bus line) DB for transmitting a signal voltage intersect, and a thin film transistor (TFT) TR and a pixel electrode 1 are arranged near the intersection. Have been.

The gate of the transistor TR is connected to the gate bus line GB, the drain of TR is connected to the data bus line DB, and the source of TR is the pixel electrode 1
It is connected to the. FIG. 19 shows an equivalent circuit of this one pixel. In the figure, the same components as those in FIG. 18 are denoted by the same reference numerals. 19, between the gate and the source of the thin film transistor TR is present parasitic capacitance C _GS, also the pixel electrode 1, i.e. the liquid crystal cell is a liquid crystal capacitance C _LC and the liquid crystal resistance R
It is represented by a parallel circuit with _LC .

[0005] In such an equivalent circuit, a pulse voltage of FIG. 20 (A) to show such a peak value [Delta] V _G to the gate bus line GB is applied. The gate pulse voltage to the high-level period T _on after being changed from V _goff to V _{go n} is a thin film transistor TR is turned on for the selected period, the low-level period T _off is a V _goff TFT TR and the non-selection period of the off I do.

[0006] At the selection period T _on, first FIG. 20
As shown in (B), the negative potential −ΔV _D applied to the data bus line DB is applied to the pixel electrode 1 via the source of the transistor TR. Thereafter, when the gate pulse voltage falls from V _gon to V _goff, parasitic capacitance C
_{Due to GS} , the potential of the pixel electrode 1 decreases by ΔV (C _GS ) as shown in FIG. This ΔV (C _GS ) is expressed by the following equation using the peak value ΔV _G of the gate pulse voltage, the parasitic capacitance C _GS and the liquid crystal capacitance C _LC .

[0007]

(Equation 1)

When driving the liquid crystal cell, a positive / negative AC voltage is applied to maintain reliability. Therefore, the polarity of the voltage applied to the liquid crystal cell (pixel electrode) 1 is inverted for each drive timing (for each frame).
And an active matrix substrate on which the pixel electrodes 1 are mounted via liquid crystal. The potential of the opposite substrate on which the opposite electrode and the liquid crystal alignment film are formed is reduced by ΔV (C _GS ) to correct the potential.

However, the liquid crystal generally has a different dielectric constant depending on the twisted state, and therefore the liquid crystal capacitance _CLC differs depending on the applied voltage. That is, the liquid crystal capacitance C _LC is a function of the voltage V _D applied to the data bus line DB C _LC (V _D) becomes, [Delta] V (C _GS) varies depending on the voltage V _D applied to the data bus line DB. Therefore, when a fixed pattern such as black is displayed on a screen on a white background, for example, a DC bias is applied to a certain area to generate polarization charges, and when the display pattern is changed, the previous display pattern remains as an afterimage. Further, the change of ΔV (C _GS ) due to the voltage V _D becomes asymmetric with respect to the potential of the counter substrate by white display or black display, and is applied to the liquid crystal cell 1 by any reduction ΔV (C _GS ). When a DC bias is applied, a flicker phenomenon occurs.

When the non-selection period T _off is _reached , the liquid crystal resistance R _LC
For leak path due to the presence, the holding voltage of the liquid crystal cell 1, the voltage -V _D which is applied during the selection period T _on,
It decreases as shown in FIG. 13C according to the time constant by the product of C _LC and R _LC . Here, assuming that the voltage holding ratio is ΔV _LC , ΔV _LC is represented by the following equation.

ΔV _LC = (V _LC rms / V _D ) × 100 (%) (2) In the above equation, V _LC rms is a non-selection period T of the liquid crystal cell 1.
the effective voltage is _off, which expressed as the following equation using the C _LC and R _LC.

[0012]

(Equation 2)

Usually, the _RLC is very large, for example 1 × 1
Since it is about 0 ¹² Ω, there is almost no effect on the voltage holding ratio ΔV _LC . However, at the time of liquid crystal injection in the panel process reduces the 1-2 orders of magnitude R _LC in pollution, also because after panel formation also change over time, the effective voltage V _LC rms is reduced, the reduction in voltage holding ratio [Delta] V _LC It becomes remarkable.

In order to solve the above two problems simultaneously, conventionally, as shown in the equivalent circuits of FIGS. 21 and 22,
The storage capacitor _CS is provided in parallel with the liquid crystal capacitor _CLC . FIG.
1 is an equivalent circuit diagram of a conventional C _S independent system, in which the storage capacitance C _S
Connect one end to the connection point between the source of the liquid crystal capacitance C _LC and a transistor TR, which are connected to the other end of the C _S to C _S line CB.

[0015] Figure 22 is an equivalent circuit diagram of a conventional C _S on gate type, the other end of the storage capacitor C _S not C _S line,
Which are connected to the gate bus line GB ₂ adjacent.
In either case, equation (1) is modified by the storage capacity C _S as follows.

[0016]

(Equation 3)

The storage capacitor C _S is a potential change ΔV (C _GS ) of the pixel electrode due to a voltage change applied to the gate bus line GB.
In order to suppress this, a large value of about three times the liquid crystal capacitance _CLC is required.

[0018]

However [0007] storage capacitor C _S of the large becomes the value described above is because it must be formed between the pixel electrode, the aperture ratio is greatly decreased. Also,
In C _S independent method shown in FIG. 21 requires C _S line CB is a dedicated bus line, which gate bus lines GB
Intersects with the data bus line DB in order to be provided in parallel with the data bus line DB. Further, the data bus line intersects the storage capacitor electrode.

[0019] Thus, by the intersection of the cross and the storage capacitor electrodes of the conventional C _S independent method described above and C _S line CB of the data bus line DB, the load capacitance of the data bus lines DB by the capacity of each intersection increases In this case, a signal delay occurs, which is a problem.

Meanwhile, C for the _S-gate scheme of sharing storage capacitor C _S and the gate bus line GB _1, GB _2, there is no intersection between the data bus lines DB and a private bus line and the storage capacitor electrode shown in FIG. 22 But the gate bus line G
Since the load capacitance of B ₁ and GB ₂ increases, a high-resolution panel having a large number of pixels requires a low-resistance gate bus line, which limits the scanning signal delay and the material and shape of the bus line.

The present invention has been made in view of the above points,
An object of the present invention is to provide a liquid crystal display device that solves the above-mentioned problem by forming the storage electrode in a predetermined configuration or devising the configuration of a liquid crystal panel.

[0022]

FIG. 1 is a schematic view of a liquid crystal display device.
FIG. 4 shows an equivalent circuit diagram of the section . 19, the same components as those of FIG. 19 are denoted by the same reference numerals, and the description thereof will be omitted. Shown in FIG.
In the liquid crystal display device, the storage capacitor electrode is provided independently of the charge storage capacitor electrode and the gate bus line (GB), and corrects a voltage drop of the pixel potential due to capacitive coupling with the gate bus line (GB). Correction capacitor electrode (1
5), each of which is independently arranged so as to overlap the pixel electrode, and a pulse having a polarity opposite to that of the pulse applied to the gate bus line (GB) is applied to the correction capacitance electrode. Has been applied. In the figure, C _Q indicates the charge holding capacity by the above-described charge holding capacity electrode, and C _C indicates the _CGS correction capacity by the correction capacity electrode.

FIG. 2 is an equivalent circuit diagram for explaining the principle of the present invention . The present invention relates to two pixel electrodes adjacent to each other in a direction parallel to the direction of the gate bus line, that is, a first pixel electrode represented by a liquid crystal capacitor C _LC1 and a liquid crystal resistor R _LC1 , and a liquid crystal capacitor C _LC2.
Across a and a second pixel electrode represented by a liquid crystal resistance R _LC2
The electrodes are arranged in an island shape . The capacitance due to this island-shaped electrode is denoted by _CX .

[0024]

[0025]

[0026]

[0027]

According to the present invention, as shown in FIG. 2, the signal voltages applied from the data bus line DB in opposite phases are represented by V ₁ and V ₂ , and the thin film transistor TR is represented by switches S ₁ and S ₂ . When the thin film transistors (switches) S ₁ and S ₂ of the pixels on the same line are on, A
Signal voltages V ₁ and V ₂ are applied to points B and B. C at this time
The potential V ₃ of the point is expressed by the following equation.

V ₃ = (V ₁ + V ₂ ) / 2 From this equation, it is found that the potential V _{3 at the} point C is constant. Thereafter, when the switches S ₁ and S ₂ are turned off, charges of C _LC1 and C _X begin to leak due to the liquid crystal resistors R _LC1 and R _LC2 . In this case, A, the potential at the point B in order to leak in the same direction at the same time, the potential V ₃ is also constant potential.

In this state, the liquid crystal capacitors C _LC1 , C _{LC
Since LC2} and the storage capacitance _CX can be considered as a parallel capacitance, the amount of charge leakage of _CLC1 and _CLC2 is conventionally τ
₁ (= R _LC1 × C _LC1 or R _LC2 × C _LC2 ), whereas in the present invention, C _X constitutes τ ₂ (= R _LC1 × (C _LC1 + C _X )). Alternatively, a time constant is represented by R _LC2 × (C _LC2 + C _X )), and this time constant is larger than before. This time constant increase (τ ₂ −
τ ₁ ) reduces the charge leakage.

[0030]

Thus, even when the gate signal of the preceding gate bus line is turned off, the storage capacitor electrode does not float, and crosstalk by the next gate bus line at the time of the off state is prevented. . Therefore, it is possible to prevent image deterioration such as afterimages and flicker which may occur in the third aspect of the present invention due to the island-shaped storage capacitor electrode structure.

[0032]

FIG. 3 is a block diagram showing a first embodiment of the present invention.
In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, the data bus line DB and the gate bus line GB are orthogonal to each other. Near the intersection of the data bus line DB and the gate bus line GB on the active matrix substrate, the pixel electrode 11 and the TF
T12 is provided. The gate electrode of the TFT 12 is connected to the gate bus line GB, the drain electrode is connected to the data bus line DB, and the source electrode is connected to the pixel electrode 11.

The output terminal of the gate drive driver 13 is connected to the gate bus line GB while the inverter circuit 14
_Is connected to the _CGS correction capacitance electrode 15 via the. This _CGS correction capacitance electrode 15 is arranged on the pixel electrode 11 in parallel with the gate bus line GB. The area of the C _GS correction capacitance electrode 15 may be the same as the parasitic capacitance C _GS formed in the TFT 12.
May be much smaller than that of

The charge storage capacitor electrode 16 is arranged in parallel with the gate bus line GB and across the pixel electrode 11, and is drawn out to the panel terminal portion.
Connected to a fixed potential. At this time, the extraction electrode is extracted in a direction opposite to the terminal electrode connected to the gate drive driver 13 so as not to cross over the gate bus line GB. The area of the charge storage capacitance electrode 16 may be large enough to obtain the same capacitance as the liquid crystal capacitance _CLC, and may be smaller than the conventional storage electrode. Therefore, the aperture ratio is improved as compared with the related art.

FIG. 4 shows an equivalent circuit diagram of FIG. In the figure,
1 and 3 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 4, C _Q is a charge holding capacitor formed by the charge holding capacitor electrode 16, the pixel electrode 11, and the substrate therebetween, and C _C is formed by the _CGS correction capacitor electrode 15, the pixel electrode 11, and the substrate therebetween. C _GS correction capacity.

According to the present embodiment, C which is the storage capacitance C _S
Electrode 1 for obtaining _GS correction capacitance C _C and charge retention capacitance C _Q
5 and 16 can be made smaller than before, so that the aperture ratio can be increased, and the load capacitance of the bus line can be reduced, so that the signal delay can be suppressed, and the material and shape of the bus line can be designed. Conditions can be relaxed.

FIG. 5 is a block diagram of a second embodiment of the present invention, and FIG.
Shows an equivalent circuit diagram of the second embodiment of the present invention. In both figures, the same components as those in FIGS. 1 and 3 are denoted by the same reference numerals, and description thereof will be omitted. Second embodiment shown in FIGS. 5 and 6 the gate bus line GB 'is formed on the pixel electrode 11, it is characterized in that also serves as an electrode for forming the charge storage capacitor C _Q. In this embodiment, an extraction electrode for connecting to a fixed potential is not required.

In this embodiment, the immediately preceding gate bus line G is placed on the pixel electrode adjacent in the data bus line DB direction.
Since B ′ is provided, in order to obtain the same aperture ratio as in the first embodiment, it is necessary to lengthen the pixel electrode 11 in the data bus line direction by the width of the gate bus line. However, the same effect as in the first embodiment is obtained. Having.

FIG. 7 is a block diagram of a third embodiment of the present invention.
Shows a sectional view of FIG. In FIG. 8, two glass substrates having a thickness of about 1 mm serving as transparent substrates are prepared, and one of them is an active matrix substrate on which a TFT is formed. TFT is a glass substrate (active matrix substrate)
Titanium (Ti), chromium (Cr), aluminum (Al), or the like is laminated on the entire surface by sputtering, and the gate bus lines GB and the gate electrodes 24 are patterned.
At this time, the storage capacitor electrode 21 is simultaneously formed of the same material.

As shown in FIGS. 7 and 8, the storage capacitor electrode 21 includes an n-th pixel electrode 11 _n and an (n + 1) -th pixel electrode 1 adjacent to each other in the longitudinal direction of the gate bus line GB.
1 n _{+ 1} and islands straddling both formed on the (lead wire required, the data bus line DB _n, without intersection of the DB n _{+ 1).}

Next, as shown in FIG.
And on the glass substrate 23 on which the gate electrode 24 is formed,
Silicon dioxide (SiO ₂ ) or silicon nitride (SiN)
After the gate insulating film 25 is formed by PCVD, a semiconductor layer 26 of amorphous silicon (a-Si) material is continuously laminated by PCVD and patterned by a transistor pattern.

Further, an n ⁺ type a-Si material and titanium (Ti)
Alternatively, a drain electrode 28, a source electrode 29, and a data bus line (DB _n , DB
_{n + 1} ). At this time, the data bus line is
As shown by B _n and DB _{n + 1} , the n-th pixel electrode 11 _n orthogonal to and adjacent to the gate bus line GB (n
It is formed every other pixel between the (+1) th pixel electrodes 11.
Therefore, the right side of the (n-1) th pixel electrode 11 _n-1 and
(N + 2) th to the left of the pixel electrode 11 n _{+ 2,} the data bus line DB _n, respectively adjacent to the data bus line DB _n-1 to _{DB n-1, DB n +} 2 are formed (none Figure Not shown).

Then, transparent ITO (Indium Tin Oxid)
According to e), pixel electrodes such as 11 _n and 11 _{n + 1} are formed by patterning. Here, the pixel electrodes 11 _n , 11 _{n + 1} and the storage capacitor electrode 21 have a certain degree of overlap. This overlap ratio of the storage capacitor C _S and the liquid crystal capacitance C _LC is for example 1: is more effective when the 2.

Thereafter, a protective insulating film and a liquid crystal alignment film (none are shown) are applied to the drain electrode 28, the source electrode 29, the pixel electrodes 11 _n , 11 _{n + 1 and the} like in FIG. create. A color filter, a black matrix, and a liquid crystal alignment film are patterned on another glass substrate to form a counter substrate. Finally, the active matrix substrate and the opposing substrate are opposed to each other, and a liquid crystal is sealed between them to complete a liquid crystal panel.

FIG. 9 shows an equivalent circuit of the liquid crystal panel of the third embodiment completed in this way. In the figure, the same components as those in FIGS. 2, 7 and 8 are denoted by the same reference numerals,
The description is omitted. In Figure 9, TFT 12 _n and 12 _{n + 1} corresponds to a switch S ₁ and S ₂ shown in FIG. 2, also C _S in series combined capacitance of the two C _X shown in FIG. 2, the accumulation of FIG. 7 5 shows the storage capacitance of the capacitance electrode 21.

The n-th liquid crystal cell 31 _n in FIG. 9 is represented by a parallel circuit of a liquid crystal resistor R _LCn and a liquid crystal capacitance C _LCn .
The (n + 1) th liquid crystal cell 31 _{n + 1} is represented by a parallel circuit of a liquid crystal resistor R _{LCn + 1} and a liquid crystal capacitance C _{LCn + 1} . The storage capacitor C _S is connected between the sources of the TFTs 12 _n and 12 _{n + 1} .

Thus, as described with reference to FIG.
The TFT12 _n, 12 _{n + 1} is opposite the polarity of the signal voltage to each other on the data bus line DB _n and DB _{n + 1} when the on-applied write to the liquid crystal cell 31 _n, 31 _{n + 1,} the subsequent TFT
The capacitance C _LCn when 12 _n and 12 _{n + 1} are off,
The discharge (charge leakage amount) of C _{LCn + 1} and C _S can be reduced as compared with the related art.

In FIG. 7, signal voltages of opposite polarities are applied to the _nth data bus line DBn and the (n + 1) th data bus line DBn _{+ 1} . FIG. 10 shows an embodiment of a liquid crystal display device including a peripheral circuit for generating the signal voltage.

[0049] In the figure, odd-numbered data bus lines DB _n is a shift register 34 of FIG. 7 and the liquid crystal panel 33 in which each pixel of the configuration shown has a plurality arranged in a matrix in FIG. 8
, And the even-numbered data bus line DB _{n + 1} is connected to the shift register 35. Further, a plurality of gate bus lines GB arranged in the horizontal direction are led out to the right side of the liquid crystal panel 33 and connected to the shift register 36.

The personal computer 37 generates at least a line signal of a horizontal scanning cycle and a signal voltage (data), supplies the line signal to the shift register 36, and outputs the signal voltage to the latch 3.
8 while latch 40 via inverter 39
To supply. The output signal voltage of the latch 38 is transferred to the shift register 34 in parallel, and the output signal voltage of the latch 40 is transferred to the shift register 35 in parallel.

[0051] Therefore, the signal voltage applied to the odd-numbered data bus lines DB _n from the shift register 34, even-numbered data bus lines DB from the shift register 35
_The polarity of the signal voltage applied to _{n + 1} is inverted. According to the present embodiment, a dedicated bus line is not required without lowering the voltage holding ratio, and the storage capacitor can be provided without considering the material and shape, so that a high-quality liquid crystal display can be performed.

The third embodiment shown in FIGS.
The liquid crystal panel actually has a gate bus as shown in FIG.
Line GB and pixel electrode 11_n, 11_{n + 1}Parasitism between
Quantity C _GSExists. That is, the gate bus line GB
TFT (12_n) When switching from ON voltage to OFF voltage
And the storage capacity C_SPixel electrodes 11 at both ends of_n, 11_{n + 1}Passing
And the potentials of the storage capacitor electrodes 21 are all in a floating state.
And the parasitic capacitance C _GSThe pixel electrode 11_n, 11
_{n + 1}Has a large potential fluctuation.

That is, the storage capacity C _S is equal to the capacity of the liquid crystal cell 31.
Although there is a function of suppressing the voltage drop of the capacitances C _LCN and C _{LCN + 1} of _n and 31 _{n + 1} , there is a possibility that afterimages and flickers may occur due to the above-mentioned potential fluctuation.

FIG. 11 shows a schematic configuration diagram of a modification of the third embodiment of the present invention. 7 and 9 in FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 11, a single pixel electrode 11 _n is divided in a direction parallel to the data bus line DB, and _an island-shaped storage capacitor electrode 21 connecting the divided pixel electrodes 11 _an and 11 _bn is formed. .

The divided pixel electrode 11 _an is connected to the source S of the TFT 121 _n which is the first thin film transistor. The drain D of the TFT 12 _1n is connected to the data bus line DB, the gate G is connected to the m th gate bus line GB _m. Further, the divided pixel electrode 11 _bn is connected to the source S of the TFT 122 _n which is the third thin film transistor.
Drain D of this TFT12 _2n data bus line DB
And the gate G is connected to the (m + 1) th gate bus line G
_{Bm + 1} .

FIG. 12 is an explanatory diagram of the operation timing of FIG. As shown in FIG. 12, the gate signals of the gate bus lines GB _m and GB _{m + 1} are applied at a timing overlapping by a half pulse (for example, 30 μsec).
Therefore, when the signal voltage of the m-th gate bus line GB _m is changed to the off-voltage from TFT (12 _1n) ON voltage, m + 1 th gate bus line GB _{m + 1} is TFT (1
2 _2n ) The ON voltage is applied to turn on the TFT 122 _n .

Accordingly, the storage capacitor electrode 21 functions as a storage capacitor, and the fluctuation in the potential of the pixel electrodes 11 _an and 11 _bn due to the change in the potential of the gate bus line is reduced, thereby preventing the afterimage and flicker as described above. it can.

However, the m-th gate bus line GB _m
Is turned off, the signal voltage of the (m + 1) th gate bus line GB _{m + 1} is turned on, and the m + 1 data (m + 1) is placed on the m data of the divided pixel electrode 11 _bn supplied from the data bus line DB. Several μ from m data
s) is supplied, and crosstalk occurs with m data of the divided pixel electrode 11 _an .

FIG. 13 is a schematic block diagram of a fourth embodiment of the present invention. In the figure, the same components as those in FIG. In FIG.
Between the TFT 12 _2n divided pixel electrode 11 _bn in FIG. 11 is obtained by interposing a TFT 12 _3n is the second thin film transistor.

[0061] That is, the drain D of TFT12 _3n is T
Is connected to the FT12 _2n source S, the source S is connected to the divided pixel electrode 11 _bn. The gate G of the TFT 12 _3n is connected via a resistor R ₁ to the m th gate bus line GBM.

The resistor R ₁ can be easily formed by using, for example, an amorphous silicon film (specific resistance 10 ⁹ Ωcm), and the delay circuit having, for example, a time constant μs is determined by the resistor R ₁ and the gate capacitance of the TFT 123 _n. (Integrating circuit).

FIG. 14 is an explanatory diagram of the operation timing of FIG. As shown in FIG. 14, when the m-th gate bus line GB _m is TFT (12 _1n) on voltage, T (a few .mu.s) by the delay circuit of the aforementioned delayed TFT12 becomes the point P ON voltage _3n is turned on State. Therefore, the (m + 1) th gate bus line GB _{m + 1} is connected to the TFT (1
2 _2n ) When the ON voltage is reached, m data from the data bus line DB is supplied to the divided pixel electrode 11 _bn .

[0064] Then, m-th with the gate bus line GB _m is TFT (12 _1n) off voltage TFT 12 _1n are turned off, TFT 12 _3n by the above-mentioned delay circuit
Is turned off after t (several μs).

That is, the m-th gate bus line GB _m
Is turned off, the TFT _123n is still in the ON state, and the storage capacitor electrode 21 is connected to the storage capacitor C _S.
And does not float. Then, after several μs of m data from the data bus line DB, m
When the +1 data is supplied, the TFT _123n is in the off state, and no crosstalk occurs in the divided pixel electrode _11bn .

As described above, the provision of the island-shaped storage capacitor electrode 21 makes it possible to prevent the reduction of the voltage holding ratio by eliminating the use of the dedicated bus line as described in the third embodiment, and to reduce the resistance. afterimage by R ₁ and TFT 12 _3n, flicker, it is possible to prevent crosstalk,
High quality liquid crystal display can be performed.

FIG. 15 is a schematic diagram showing a modification of the fourth embodiment of the present invention. In the figure, the same components as those in FIG. FIG.
In 5, instead of the resistor R ₁ in FIG. 13, TFT 12 _3n
The gate G, which are connected to the m-th and (m + 1) th gate bus line GB _m, a control gate bus lines formed between the GB m + ₁ m 'th gate bus line GB _m'. The same gate signal voltage delayed by t (several μs) from the m-th gate bus line GB _m is applied to the m′-th gate bus line GB _m ′.

FIG. 16 is a diagram for explaining the operation timing of FIG. In FIG. 16, as in FIG. 14, after the m-th gate bus line GB _m becomes the off-state voltage, t (several μs) elapses, and the m′-th gate bus line GB _m ′ becomes the off-state voltage. Thus by TFT121n there is TFT 12 _3n from the OFF state after several μs turned off, the variation of the pixel potential is reduced, preventing an afterimage, flicker similarly to FIG. 13, of course, it is possible to prevent crosstalk.

Next, FIG. 17 shows a schematic configuration diagram of a fifth embodiment of the present invention. In the figure, the same components as those in FIG. FIG. 17A is a schematic configuration diagram, and FIG. 17B is an explanatory diagram of operation timing.

In FIG. 17A, two pixel electrodes 11 _n and 1 adjacent to each other in a direction parallel to the gate bus line (GB).
1 _{n + 1} are connected by an island-shaped storage capacitor electrode 21,
A resistor R ₂ is interposed between the gate G of the TFT 12 _{n + 1} and the gate bus line GB.
And FIG. The resistance R ₂ is, for example, an amorphous silicon film (specific resistance 10 ⁹ Ω) as in the fourth embodiment.
cm), and a delay circuit having a time constant t (several μs) is constituted by the resistor R ₂ and the gate capacitance of the TFT 12 _{n + 1} .

The operation timing will be described. As shown in FIG. 17B, when the gate bus line GB is turned on, the TFT 12 _n is turned on, and after the time t (several μs), the TFT 12 _{n + 1} is turned on. State. At this time, the nth data bus line DB is connected to the pixel electrode 11 _n.
n data than _n is supplied to the pixel electrode 11 n _{+ 1} (n
(N + 1) data is supplied from the (+1) th data bus line DB _{n + 1} . When the gate bus line GB is turned off, the TFT 12 _n is turned off.
T12 _{n + 1} is turned off after t time (several μs).

That is, when the gate bus line GB is turned off, the TFT 12 _{n + 1} is still in the ON state, so that the pixel electrode 11 _{n + 1} and the storage capacitor electrode 21 do not enter a floating state, and the storage capacitor those that form serve as C _S.

As a result, the pixel electrodes 11 _n and 11 _{n + 1}
And the occurrence of afterimages, flicker and crosstalk can be prevented, and a high-quality liquid crystal display can be performed.

[0074]

[0075]

As described above, according to the present invention, two signal electrodes adjacent in the direction of the gate bus line are connected via the island-shaped storage capacitor electrode, and the signal voltage supplied to the adjacent data bus line is controlled. Since the amount of charge leakage can be made smaller than before by inverting the polarity and applying them at the same time, a dedicated bus line is not required, and the storage capacitor can be provided without considering the material and shape. As a result, a high quality liquid crystal display device can be realized.

[0076]

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a main part of a liquid crystal display device .

FIG. 2 is an equivalent circuit diagram for explaining the principle of the present invention .

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a third embodiment of the present invention.

FIG. 8 is a sectional view of FIG. 7;

FIG. 9 is an equivalent circuit diagram of a third embodiment of the present invention.

FIG. 10 is an overall configuration diagram of an embodiment of the present invention.

FIG. 11 is a schematic configuration diagram of a modified example of the third embodiment of the present invention.

12 is an explanatory diagram of the operation timing of FIG.

FIG. 13 is a schematic configuration diagram of a fourth embodiment of the present invention.

14 is an explanatory diagram of the operation timing of FIG.

FIG. 15 is a schematic configuration diagram of a modification of the fourth embodiment of the present invention.

16 is an explanatory diagram of the operation timing of FIG.

FIG. 17 is a schematic configuration diagram of a fifth embodiment of the present invention.

FIG. 18 is a configuration diagram of an example of one pixel of a conventional liquid crystal panel.

FIG. 19 is an equivalent circuit diagram of one pixel of a conventional liquid crystal panel.

FIG. 20 is a time chart showing an applied voltage of each bus line and an applied voltage of a liquid crystal cell.

FIG. 21 is an equivalent circuit diagram of a conventional _CS independent system.

Figure 22 is an equivalent circuit diagram of a conventional C _S on-gate method.

[Explanation of symbols]

11, 11 _n , 11 _{n + 1} , 50 ₁ , 50 ₂ pixel electrodes 11 _an , 11 _bn divided pixel electrodes 12, 12 _n , 12 _{n + 1} , 51 ₁ , 51 ₂ , 52 ₁ , 52 ₂ ,
53 _1, 53 _2, TR thin film transistor (TFT) 13 gate bus line driver 14,39 inverter 15 C _GS correction capacitor electrode 16 charge storage capacitor electrode 21 storage capacitor electrode 33 liquid crystal panel C _LC, C _LC1, C _LC2 liquid crystal capacitance C _Q charge holding capacitance C _C C _GS correction capacitance R _LC1 , R _LC2 capacitance resistance C _X , C _S storage capacitance DB, DB _n , DB _{n + 1} Data bus line GB, GB 'Gate bus line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Yoshioka 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kazuhiro Takahara 1015 Kamedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-3-69916 (JP, A) JP-A-3-168617 (JP, A) JP-A-5-80354 (JP, A)

Claims (8)

(57) [Claims] 1. A plurality of data bus lines for supplying a signal voltage
IN (DB) and multiple gate buses that supply the scanning voltage
Line (GB) intersects with each other at each intersection.
A gate is connected to the gate bus line (GB),
Drain (or source) connected to tabus line (DB)
Thin film transistor (TR) and thin film transistor
(TR) source (or drain)ConnectedPixel
With electrode (1), Forming a storage capacitor with the pixel electrode
Storage capacitor electrode (C_S)WhenWas providedActive matri
Liquid crystal in which the liquid crystal substrate is opposed to the opposing substrate via the liquid crystal
In the display device, the storage capacitor electrode (C_s) Is provided independently of the charge storage capacitor electrode (16) and the gate bus line (GB).
And capacitive coupling with the gate bus line (GB).
Capacitor electrode for correcting the voltage drop of the pixel potential
(15), the charge storage capacitor electrode (16) and the correction capacitor electrode (1).
5) and each independently,Through the insulating filmThe pixel electrode
Place it so that it overlaps (1),And the correction capacitance
The area where the pole overlaps with the pixel electrode is determined by the charge retention.
The capacitance electrode is smaller than the area of the portion overlapping the pixel electrode
Formed to become  The correction bus electrode (15) is connected to the gate bus line.
Apply a pulse of the opposite polarity to the pulse applied to the
A liquid crystal display device comprising: 2. A plurality of data bus lines (DB) for supplying a signal voltage and a plurality of gate bus lines (GB) for supplying a scanning voltage intersect, and the gate bus line (GB) at each intersection. A thin film transistor (TR) having a gate connected to the data bus line (DB) and a drain (or source) connected to the data bus line (DB); and a pixel electrode (1) connected to the source (or drain) of the thin film transistor (TR). in the liquid crystal display device active matrix substrate is arranged opposite to the opposite substrate through the liquid crystal <br/> storage capacitor electrode for forming a storage capacitor and (C _S) is provided between the pixel electrode, wherein A storage capacitor electrode (C _S ) is arranged across two adjacent pixel electrodes in a unit of two adjacent pixel electrodes in a direction parallel to the direction of the gate bus line (GB). Sa
A liquid crystal display device having an island-shaped electrode structure (21). 3. The island-shaped storage capacitor electrode (21) is straddled.
The two adjacent pixel electrodes (11 _n , 1
1 _{n + 1} ) to the thin film transistors (12 _n , 1
The two adjacent data bus lines (DB _n , DB _{n + 1} ) connected via 2 _{n + 1} ) are arranged at positions not intersecting with the island-shaped storage electrodes (21). The liquid crystal display device according to claim 2, wherein: 4. The island-shaped storage electrode (21) is disposed so as to straddle.
The phase Tonariru two pixel electrodes being (11 _n, 1
1 _{n + 1} ) to the thin film transistors (12 _n , 1
The signal voltages of opposite polarities are applied to two adjacent data bus lines (DB _n , DB _{n + 1} ) connected via 2 _{n + 1} ). 3. The liquid crystal display device according to 3. (5)Multiple data bus lines to supply signal voltage
IN (DB) and multiple gate buses that supply the scanning voltage
Line (GB) intersects with each other at each intersection.
A gate is connected to the gate bus line (GB),
Tabas line (DB) drain (or source) is connected
Thin film transistor (TR) and thin film transistor
Pixel electrode connected to the source (or drain) of (TR)
A storage capacitor forming a storage capacitor between the electrode (1) and the pixel electrode;
Product capacitance electrode (C _S ) And active matrix
Liquid crystal display with a liquid crystal substrate facing the opposing substrate via liquid crystal.
In the indicating device, The single pixel electrode (11 _n ) Is the data bus line
(DB), the storage capacitor electrode
(C _S ) With the divided pixel electrodes (11 _an , 11 _bn )while
And an island-shaped electrode structure
Liquid crystal display device. 6.The divided pixel electrodes (11 _an , 1
1 _bn ) (11) _an ), The gate bus line (G
B _m ) Is connected to the first thin film transistor
And The other pixel electrode (11 _bn ), The gate bus line (G
B _m ) A second thin film tiger controlled via a delay means
Transistor and the gate bus line (G
B _{m + 1} ) Controlled in series with the third thin film transistor
That the road is connected 6. The liquid crystal table according to claim 5, wherein:
Indicating device. 7. The second thin film in place of the delay means
Transistor is connected by the gate bus line (GB _m )
A control gate bar controlled by a gate signal delayed by a predetermined time
6. The liquid crystal according to claim 5, wherein a line is provided.
Display device. 8. The gate bus line (GB _m ) and said gate bus line (GB _m )
The gate bus line (GB _{m + 1} ) of the next stage partially overlaps
The gate signal is applied at a certain timing.
The liquid crystal display device according to claim 6.