JPH06265939A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the liquid crystal display device which is high in display quality and is simple in the structure of peripheral circuits and a liquid crystal panel in the active matrix liquid crystal display device arranged with plural pieces of pixels consisting of liquid crystal cells in a matrix form. CONSTITUTION:A storage capacitance is constituted of a charge holding capacitance CQ and a CGS correction capacitance Cc. This CGS correction capacitance is the capacitance for correcting the voltage drop of a pixel potential by capacity coupling with a gate bus line GB. The charge holding capacitance CQ and the CGS correction capacitance Cc are constituted independently from each other. The area of the electrode of the CGS correction capacitance Cc is extremely small. The area of the electrode of CQ suffices with the area at which about the same capacity as the capacity of a liquid crystal capacitance CLC is obtainable. The area is made smaller than the area of the electrode of the conventional storage capacity CS as a whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device having a plurality of liquid crystal cell pixels arranged in a matrix.

A liquid crystal display device is a large-scale semiconductor integrated circuit (L
Due to the rapid progress and development of SI) technology, ordinary LSIs can be driven at a low voltage, consume less power, and are small in size, light in weight, and inexpensive, and thus have been widely used in recent years. For such a liquid crystal display device, further improvement in display quality and simplification of the panel structure are desired.

[0003]

2. Description of the Related Art FIG. 18 is a block diagram showing an example of a liquid crystal panel of a conventional liquid crystal display device. In the figure, a gate bus line GB for transmitting a scanning voltage and a data bus line (drain bus line) DB for transmitting a signal voltage intersect, and a thin film transistor (TFT) TR and a pixel electrode 1 are arranged near the intersection. Has been done.

The gate of the transistor TR is connected to the gate bus line GB, the drain of TR is connected to the data bus line DB, and the source of TR is the pixel electrode 1.
It is connected to the. The equivalent circuit of this one pixel is shown in FIG. In the figure, the same components as those in FIG. 18 are designated by the same reference numerals. In FIG. 19, a parasitic capacitance C _GS exists between the gate and source of the thin film transistor TR, and the pixel electrode 1, that is, the liquid crystal cell, has a liquid crystal capacitance C _LC and a liquid crystal resistance R.
It is represented by a parallel circuit with _LC .

In such an equivalent circuit, a pulse voltage having a peak value ΔV _G as shown in FIG. 20A is applied to the gate bus line GB. A high level period T _on after the gate pulse voltage changes from V _goff to V _{go n} is a selection period in which the thin film transistor TR is on, and a low level period T _off that is V _goff is a non-selection period in which the thin film transistor TR is off. To do.

[0006] When the selection period T _on comes, first, FIG.
As shown in (B), the negative potential −ΔV _D applied to the data bus line DB is applied to the pixel electrode 1 via the source of the transistor TR. After that, when the gate pulse voltage falls from V _gon to V _goff , the parasitic capacitance C
_{Due to GS} , the potential of the pixel electrode 1 is lowered by ΔV (C _GS ) as shown in FIG. This ΔV (C _GS ) is expressed by the following equation using the peak value ΔV _G of the gate pulse voltage, the parasitic capacitance C _GS and the liquid crystal capacitance C _LC .

[0007]

[Equation 1]

When driving the liquid crystal cell, positive and negative AC voltages are applied to maintain reliability. Therefore, since the polarity of the voltage applied to the liquid crystal cell (pixel electrode) 1 is inverted at each drive timing (at each frame), the thin film transistor TR
The potential of the counter substrate, which is opposed to the active matrix substrate on which the pixel electrode 1 is mounted and the liquid crystal alignment film is formed, is lowered by ΔV (C _GS ) to correct the potential.

However, since the liquid crystal generally has a different dielectric constant depending on its twisted state, the liquid crystal capacitance C _LC differs depending on the applied voltage. That is, the liquid crystal capacitance C _LC is a function of the voltage V _D applied to the data bus line DB C _LC (V _D) becomes, [Delta] V (C _GS) varies depending on the voltage V _D applied to the data bus line DB. Therefore, when a fixed pattern such as black on a white background is displayed on the screen, a DC bias is applied to a certain area to generate polarization charge, and when the display pattern is changed, the previous display pattern remains as an afterimage. Further, the change in ΔV (C _GS ) due to the voltage V _D is asymmetric with respect to the potential of the counter substrate due to white display or black display, and is applied to the liquid crystal cell 1 due to any decrease ΔV (C _GS ). When a DC bias is applied, a flicker phenomenon will occur.

At the non-selection period T _off , the liquid crystal resistance R _LC
Due to the existence of the leak path due to, the holding voltage of the liquid crystal cell 1 is more than the voltage −V _D applied during the selection period T _on .
It decreases as shown in FIG. 13 (C) according to the time constant of the product of C _LC and R _LC . Here, assuming that the voltage holding ratio is ΔV _LC , ΔV _LC is expressed by the following equation.

ΔV _LC = (V _LC rms / V _D ) × 100 (%) (2) where V _LC rms is the non-selection period T of the liquid crystal cell 1.
It is an effective voltage at _off , and can be expressed by the following equation using C _LC and R _LC .

[0012]

[Equation 2]

Usually, R _LC is very large, for example, 1 × 1.
Since it is about 0 ¹² Ω, it hardly affects the voltage holding ratio ΔV _LC . However, when liquid crystal is injected in the panel process, R _LC is reduced by about 1 to 2 digits due to contamination or the like, and changes with time after paneling, so that the effective voltage V _LC rms is reduced and the voltage holding ratio ΔV _LC is reduced. It will be noticeable.

In order to solve the above two problems at the same time, conventionally, as shown in the equivalent circuits of FIGS. 21 and 22,
The storage capacitor C _S was provided in parallel with the liquid crystal capacitor C _LC . Figure 2
1 is an equivalent circuit diagram of the conventional C _S independent system, which has a storage capacity C _S
Connect one end to the connection point between the source of the liquid crystal capacitance C _LC and a transistor TR, which are connected to the other end of the C _S to C _S line CB.

FIG. 22 is an equivalent circuit diagram of a conventional C _{S on-} gate system, in which the other end of the storage capacitor C _S is not a C _S line,
It is connected to the adjacent gate bus line GB ₂ .
In any case, the equation (1) is modified by the storage capacitance C _S as follows.

[0016]

[Equation 3]

The storage capacitance C _S is the potential change ΔV (C _GS ) of the pixel electrode due to the voltage change applied to the gate bus line GB.
To suppress this, a large value of about 3 times the liquid crystal capacitance C _LC is required.

[0018]

However, since the above-mentioned large value storage capacitor C _S has to be formed between the pixel electrode and the pixel electrode, the aperture ratio is greatly reduced. Also,
The C _S independent system shown in FIG. 21 requires a C _S line CB which is a dedicated bus line, which is a gate bus line GB.
Intersects the data bus line DB in order to be provided in parallel. Further, the data bus line intersects with the storage capacitor electrode.

Therefore, in the above-described conventional C _S independent system, the crossing of the data bus line DB with the C _S line CB and the crossing of the storage capacitance electrode increase the load capacitance of the data bus line DB due to the capacitance at each intersection. , Signal delay occurs and becomes a problem.

Meanwhile, C for the _S-gate scheme of sharing storage capacitor C _S and the gate bus line GB _1, GB _2, there is no intersection between the data bus lines DB and a private bus line and the storage capacitor electrode shown in FIG. 22 But the gate bus line G
Since the load capacitances of B ₁ and GB ₂ increase, a low-resistance gate bus line is required in a high-definition panel having a large number of pixels, which limits the scanning signal delay and the material and shape of the bus line.

The present invention has been made in view of the above points,
An object of the present invention is to provide a liquid crystal display device that solves the above-mentioned problems by making the storage electrode have a predetermined configuration or devising the configuration of the liquid crystal panel.

[0022]

FIG. 1 shows an equivalent circuit diagram for explaining the principle of the invention described in claim 1. 19, those parts which are the same as those corresponding parts in FIG. 19 are designated by the same reference numerals, and a description thereof will be omitted.
As shown in FIG. 1, the present invention divides the storage capacitance electrode into a charge retention capacitance electrode and a capacitance electrode for correcting a voltage drop of a pixel potential due to capacitive coupling with a gate bus line GB, and each has an independent structure. It was done. In the figure, C _Q is the charge holding capacitance by the charge holding capacitance electrode, and C _C is the C _GS correction capacitance by the correction capacitance electrode.

FIG. 2 is for explaining the principle of the invention according to claim 3 and the like.
A price circuit diagram is shown. The present invention is directed to the direction of the gate bus line
Two pixel electrodes adjacent to each other in the row direction, that is, a liquid crystal capacitance C
_LC1And liquid crystal resistance R_LC1A first pixel electrode represented by
Liquid crystal capacity C_LC2And liquid crystal resistance R _LC2The second image represented by
The island electrodes are connected to the element electrodes. This island electrode
Capacity is C_XIndicated by.

Further, although not shown in the drawings, claims 7 and 8
In the invention described above, a single pixel electrode is divided in a direction parallel to the data bus line, and the storage capacitor electrode has an island-shaped electrode structure for connecting the divided pixel electrodes, and the divided pixel electrode is formed. A first thin film transistor controlled by the gate bus line is connected to one of the two, and a second thin film transistor controlled by a delay means from the gate bus line to the other pixel electrode, and the next stage of the thin film transistor. A series circuit of third thin film transistors controlled by the gate bus line is connected.

[0025]

In the invention described in claim 1, when the area of the storage capacitor electrode is estimated, the area of the electrode of the C _GS correction capacitor C _C for correcting the pixel potential by the capacitive coupling with the gate bus line GB shown in FIG. It suffices if it is the same as the parasitic capacitance C _GS . Since this parasitic capacitance C _GS has a very small value, a very small area corresponding to the capacitance value is sufficient.

Further, a charge holding capacitor C for holding the pixel potential
_QThe area of the electrode of is the liquid crystal capacitance C_LCShaped as much as
Since it only has to be made, the area can be relatively small. Obey
C _CAnd C_QThe total electrode area of_SIndependence
It can be made smaller than the method.

Further, in the invention according to claim 3, as shown in FIG.
The data bus line DB in opposite phases.
The applied signal voltage is V₁, V₂, Thin film transistor TR
Switch S₁, S₂And the same line
Thin film transistor (switch) S of the pixel₁And S₂But
When each is on, signal voltage V is applied to points A and B.₁, V ₂
Is applied. Potential V at point C at this time₃Is given by
Be done.

V ₃ = (V ₁ + V ₂ ) / 2 From this equation, it is understood that the potential V _{3 at the} point C is a constant potential. After that, when the switches S ₁ and S ₂ are turned off, the charges of C _LC1 and C _X start to leak due to the liquid crystal resistors R _LC1 and R _LC2 . At this time, the potentials at points A and B simultaneously leak in the same direction, so that the potential V ₃ is also constant.

In this state, the liquid crystal capacitors C _LC1 and C _{LC
Since LC2} and the storage capacitance C _X can be considered as parallel capacitance, the amount of charge leakage of C _LC1 and C _LC2 is conventionally τ.
₁ (= R _LC1 × C _LC1 or R _LC2 × C _LC2 ) decreases in accordance with the time constant, whereas in the present invention, by forming C _X , τ ₂ (= R _LC1 × (C _LC1 + C _X ). Alternatively, R _LC2 × (C _LC2 + C _X )) indicates a time constant, and this time constant is larger than in the past. This time constant increase (τ ₂ −
τ ₁ ) reduces the amount of leakage of the charge.

According to the present invention, the pixel electrode, which is one of the divided pixel electrodes and is controlled by the gate signal of the gate bus line in the next stage by the third thin film transistor, is arranged in the previous stage. It is controlled by the second thin film transistor driven by the gate signal delayed by a predetermined time from the gate signal of the gate bus line.

As a result, even if the gate signal of the gate bus line of the previous stage is turned off, the storage capacitor electrode does not become in the floating state, and crosstalk by the gate bus line of the next stage at the time of the off state is prevented. . Therefore, the island-shaped storage capacitor electrode structure can prevent image deterioration such as afterimage and flicker that may occur in the invention of claim 3.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram of the first embodiment of the present invention.
In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. In FIG. 3, the data bus line DB and the gate bus line GB are orthogonal to each other. The pixel electrode 11 and the TF are formed near the intersection of the data bus line DB and the gate bus line GB on the active matrix substrate.
T12 and are provided. The gate electrode of the TFT 12 is connected to the gate bus line GB, the drain electrode is connected to the data bus line DB, and the source electrode is connected to the pixel electrode 11.

The output end of the gate drive driver 13 is connected to the gate bus line GB, while the inverter circuit 14 is connected.
It is connected to the C _GS correction capacitance electrode 15 via. The C _GS correction capacitance electrode 15 is arranged on the pixel electrode 11 in parallel with the gate bus line GB. The area of the C _GS correction capacitance electrode 15 may be the same as the parasitic capacitance C _GS formed in the TFT 12, and the charge holding capacitance electrode 16 to be described later
It can be much smaller than that.

Further, the charge storage capacitor electrode 16 is arranged in parallel with the gate bus line GB and across the pixel electrode 11, and this is led out to the panel terminal portion.
It is connected to a fixed potential. At this time, the extraction electrode is extracted in the direction opposite to the terminal electrode connected to the gate drive driver 13 so as not to cross over the gate bus line GB. The area of the charge storage capacitor electrode 16 may be large enough to obtain the same capacitance as the liquid crystal capacitance C _LC, and may be smaller than that of the conventional storage electrode. Therefore, the aperture ratio is improved as compared with the conventional case.

FIG. 4 shows an equivalent circuit diagram of FIG. In the figure,
The same components as those in FIGS. 1 and 3 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 4, C _Q is the charge holding capacitance formed by the charge holding capacitance electrode 16, the pixel electrode 11 and the substrate between them, and C _C is formed by the C _GS correction capacitance electrode 15 and the pixel electrode 11 and the substrate between them. C _GS correction capacity.

According to this embodiment, the storage capacity C _S becomes C
Electrode 1 for obtaining _GS correction capacitance C _C and charge retention capacitance C _Q
Since the total area of 5 and 16 can be made smaller than the conventional one, the aperture ratio can be increased, and the load capacitance of the bus line is reduced, so that the signal delay can be suppressed, and further the design of the material and shape of the bus line. The conditions can be relaxed.

FIG. 5 is a block diagram of the second embodiment of the present invention, and FIG.
Shows an equivalent circuit diagram of the second embodiment of the present invention. In both figures, the same components as those in FIGS. 1 and 3 are designated by the same reference numerals, and the description thereof will be omitted. The second embodiment shown in FIGS. 5 and 6 is characterized in that the gate bus line GB ′ is formed on the pixel electrode 11 and also serves as an electrode for forming the charge holding capacitance C _Q. In this embodiment, the extraction electrode for connecting to the fixed potential is unnecessary.

In this embodiment, the gate bus line G one line before is provided on the pixel electrode adjacent in the data bus line DB direction.
Since B'is provided, in order to obtain the same aperture ratio as in the first embodiment, it is necessary to lengthen the pixel electrode 11 in the data bus line direction by about the gate bus line width, but the same effect as in the first embodiment. Have.

FIG. 7 is a block diagram of the third embodiment of the present invention, and FIG.
Shows a sectional view of FIG. 7. In FIG. 8, two glass substrates having a thickness of about 1 mm to be transparent substrates are prepared, and one of them is used as an active matrix substrate on which TFTs are formed. TFT is a glass substrate (active matrix substrate)
Titanium (Ti), chromium (Cr), aluminum (Al), or the like is laminated on the entire surface by sputtering, and the gate bus line GB and the gate electrode 24 are patterned.
At this time, the storage capacitor electrode 21 is simultaneously formed from the same material.

As shown in FIGS. 7 and 8, the storage capacitor electrode 21 is an nth pixel electrode 11 _n and an (n + 1) th pixel electrode 1 which are adjacent to each other in the longitudinal direction of the gate bus line GB.
It is formed in an island shape (lead line is not required, there is no intersection with the data bus lines DB _n and DB _{n + 1} ) straddling both 1 _{n + 1} .

Next, as shown in FIG.
And on the glass substrate 23 on which the gate electrode 24 is formed,
Silicon dioxide (SiO ₂ ) and silicon nitride (SiN)
After the gate insulating film 25 is formed by PCVD method, a semiconductor layer 26 made of amorphous silicon (a-Si) material is continuously laminated by PCVD method and patterned by a transistor pattern.

Further, n ⁺ type a-Si material and titanium (Ti)
Alternatively, the drain electrode 28, the source electrode 29, and the data bus line (DB _n , DB in FIG. 7) made of tantalum (Ta) material are used.
_{n + 1} ) is formed. At this time, the data bus line is D in FIG.
As indicated by B _n and DB _{n + 1} , n-th pixel electrodes 11 _n and (n which are orthogonal to the gate bus line GB and are adjacent to each other are shown.
The +1) th pixel electrodes 11 are alternately formed.
Therefore, on the right side of the (n-1) th pixel electrode 11 _n-1 ,
(N + 2) th to the left of the pixel electrode 11 n _{+ 2,} the data bus line DB _n, respectively adjacent to the data bus line DB _n-1 to _{DB n-1, DB n +} 2 are formed (none Figure (Not shown).

Then, transparent ITO (Indium Tin Oxid)
By e), pixel electrodes such as 11 _n and 11 _{n + 1} are patterned and formed. Here, the pixel electrodes 11 _n and 11 _{n + 1} and the storage capacitor electrode 21 are overlapped to some extent. This overlap is more effective when the ratio of the liquid crystal capacitance C _LC to the storage capacitance C _S is 1: 2, for example.

Thereafter, a protective insulating film and a liquid crystal alignment film (neither shown) are applied to the drain electrode 28, the source electrode 29, the pixel electrodes 11 _n and 11 _{n + 1,} etc. of FIG. 8 to form an active matrix substrate. create. Moreover, a color filter, a black matrix, and a liquid crystal alignment film are patterned on another glass substrate to form a counter substrate. Finally, the active matrix substrate and the counter substrate are opposed to each other, and liquid crystal is sealed between them to complete the liquid crystal panel.

The equivalent circuit of the liquid crystal panel of the third embodiment thus completed is as shown in FIG. In the figure, the same components as those in FIGS. 2, 7 and 8 are designated by the same reference numerals,
The description is omitted. In FIG. 9, TFTs 12 _n and 12 _{n + 1} correspond to the switches S ₁ and S ₂ shown in FIG. 2, and C _S is a series combined capacitance of the two C _X shown in FIG. The storage capacitance by the capacitance electrode 21 is shown.

Further, the nth liquid crystal cell 31 _n in FIG. 9 is represented by a parallel circuit of a liquid crystal resistance R _LCn and a liquid crystal capacitance C _LCn ,
The n + 1th liquid crystal cell 31 _{n + 1} is represented by a parallel circuit of a liquid crystal resistance R _{LCn + 1} and a liquid crystal capacitance C _{LCn + 1} . The storage capacitor C _S is connected between the sources of the TFTs 12 _n and 12 _{n + 1} .

As a result, as described with reference to FIG.
The TFT12 _n, 12 _{n + 1} is opposite the polarity of the signal voltage to each other on the data bus line DB _n and DB _{n + 1} when the on-applied write to the liquid crystal cell 31 _n, 31 _{n + 1,} the subsequent TFT
The capacitance C _LCn when 12 _n and 12 _{n + 1} are off,
The discharge of C _{LCn + 1} and C _S (leakage amount of charge) can be made smaller than before.

In FIG. 7, signal voltages of opposite polarities are applied to the _nth data bus line DB _n and the (n + 1) th data bus line DB _{n + 1} . An embodiment of a liquid crystal display device including a peripheral circuit for generating this signal voltage is shown in FIG.

In the figure, the odd-numbered data bus lines DB _n of the liquid crystal panel 33 in which a plurality of pixels each having the structure shown in FIGS. 7 and 8 are arranged in a matrix form a shift register 34.
The even-numbered data bus line DB _{n + 1} is connected to the shift register 35. A plurality of gate bus lines GB arranged in the horizontal direction are led out to the right side of the liquid crystal panel 33 and connected to the shift register 36.

The personal computer 37 generates at least a line signal of horizontal scanning period and a signal voltage (data), supplies the line signal to the shift register 36, and the signal voltage is latched by the latch 3.
8 to the latch 40 via the inverter 39
Supply to. The output signal voltage of the latch 38 is transferred in parallel to the shift register 34, and the output signal voltage of the latch 40 is transferred in parallel to the shift register 35.

Therefore, the signal voltage applied to the odd-numbered data bus line DB _n from the shift register 34 and the even-numbered data bus line DB from the shift register 35.
_The polarities of the signal voltage applied to _{n + 1} are opposite to each other. According to this embodiment, the voltage holding ratio is not lowered, the dedicated bus line is not necessary, and the storage capacitor can be provided without considering the material and the shape, so that a high quality liquid crystal display can be performed.

By the way, a third embodiment shown in FIGS. 7 and 9
In the case of the liquid crystal panel of
Line GB and pixel electrode 11_n, 11_{n + 1}Between and
Quantity C _GSExists. That is, the gate bus line GB
TFT (12_n) When switching from on-voltage to off-voltage
And the storage capacity C_SPixel electrodes 11 on both ends of_n, 11_{n + 1}Over
And the potentials of the storage capacitor electrodes 21 are all in a floating state.
And the above parasitic capacitance C _GSThe pixel electrode 11_n, 11
_{n + 1}The electric potential fluctuation of becomes large.

That is, the storage capacitance C _S is _equal to the liquid crystal cell 31.
Although it has a function of suppressing the voltage drop of the capacitors C _LCN and C _{LCN + 1} of _n and 31 _{n + 1} , there is a possibility that an afterimage and flicker may occur due to the potential fluctuation.

Therefore, FIG. 11 shows a schematic block diagram of a modification of the third embodiment of the present invention. 7 and 9 in the figure
The same components as in FIG.

In FIG. 11, a single pixel electrode 11 _n is divided in the direction parallel to the data bus line DB, and _an island-shaped storage capacitance electrode 21 connecting the divided pixel electrodes 11 _an and 11 _bn is formed. .

The divided pixel electrode 11 _an is connected to the source S of the TFT 12 _1n which is the first thin film transistor. The drain D of the TFT 12 _1n is connected to the data bus line DB, and the gate G is connected to the m-th gate bus line GB _m . The divided pixel electrode 11 _bn is connected to the source S of the TFT 12 _2n which is the third thin film transistor.
The drain D of this TFT 12 _2n is a data bus line DB
And the gate G is the (m + 1) th gate bus line G.
B _{m + 1} .

Therefore, FIG. 12 shows an explanatory diagram of the operation timing of FIG. As shown in FIG. 12, the gate signals from the gate bus lines GB _m and GB _{m + 1} are applied at the timing of overlapping by half a pulse (for example, 30 μsec).
Therefore, when the signal voltage of the m-th gate bus line GB _m changes from the TFT (12 _1n ) ON voltage to the OFF voltage, the m + 1-th gate bus line GB _{m + 1} becomes the TFT (1
2 _2n ) turns on and the TFT 12 _2n is turned on.

Therefore, the storage capacitor electrode 21 functions as a storage capacitor, the potential fluctuations of the pixel electrodes 11 _an and 11 _bn due to the potential change of the gate bus line are reduced, and the above-mentioned afterimage and flicker can be prevented. it can.

However, the mth gate bus line GB _m
Signal voltage of the m + 1-th gate bus line GB _{m + 1} is the on voltage when the signal voltage of the divided pixel electrode 11 _bn supplied from the data bus line DB is m + 1 data ( Several μ from m data
s) is supplied, which causes crosstalk with m data of the divided pixel electrode 11 _an .

Therefore, FIG. 13 shows a schematic block diagram of the fourth embodiment of the present invention. 11, those parts that are the same as those corresponding parts in FIG. 11 are designated by the same reference numerals, and a description thereof will be omitted. In FIG.
A TFT 12 _3n which is a second thin film transistor is interposed between the TFT 12 _2n and the divided pixel electrode 11 _bn in FIG.

That is, the drain D of the TFT 12 _3n is T
The source S of the FT12 _2n is connected, and the source S is connected to the divided pixel electrode 11 _bn . The gate G of the TFT 12 _3n is connected to the m-th gate bus line GBm via the resistor R ₁ .

The resistor R ₁ can be easily formed by using, for example, an amorphous silicon film (specific resistance 10 ⁹ Ωcm). The resistor R ₁ and the gate capacitance of the TFT 12 _3n form a delay circuit having a time constant μs, for example. (Integrator circuit).

Here, FIG. 14 shows an explanatory diagram of the operation timing of FIG. As shown in FIG. 14, when the m-th gate bus line GB _m becomes the TFT (12 _1n ) ON voltage, the delay circuit delays T (several μs) and the P point becomes the ON voltage, and the TFT 12 _3n is turned ON. It becomes a state. Therefore, the m + 1-th gate bus line GB _{m + 1} is connected to the TFT (1
When the voltage becomes 2 _2n ) ON voltage, m data from the data bus line DB is supplied to the divided pixel electrode 11 _bn .

When the m-th gate bus line GB _m becomes the TFT (12 _1n ) off voltage, the TFT 12 _1n is turned off and the delay circuit described above causes the TFT 12 _3n.
Turns off after t (several μs).

That is, the m-th gate bus line GB _m
Is turned off, the TFT 12 _3n is still in the on state, so that the storage capacitor electrode 21 stores the storage capacitor C _S.
It does not become a floating state. After that, after a few μs of m data from the data bus line DB, m
At the time when +1 data is supplied, the TFT 12 _3n is in the off state, and crosstalk does not occur in the divided pixel electrode 11 _bn .

As described above, by providing the island-shaped storage capacitor electrode 21, it is possible to prevent the voltage holding ratio from being lowered by eliminating the need for a dedicated bus line as described in the third embodiment, and at the same time, to reduce the resistance. Afterimages, flicker, and crosstalk can be prevented by R ₁ and TFT 12 _3n ,
High quality liquid crystal display can be performed.

FIG. 15 shows a schematic block diagram of a modification of the fourth embodiment of the present invention. 13, those parts which are the same as those corresponding parts in FIG. 13 are designated by the same reference numerals, and a description thereof will be omitted. Figure 1
In 5, instead of the resistor R ₁ in FIG. 13, TFT 12 _3n
Is connected to an m′-th gate bus line GB _m ′ which is a control gate bus line formed between the m-th and m + 1-th gate bus lines GB _m and GB _{m + 1} . The m 'th gate bus line GB _m', m-th gate bus line GB _m from t (several .mu.s) delayed the same gate signal voltage is applied.

Therefore, FIG. 16 shows an explanatory diagram of the operation timing of FIG. Figure 16 is similar to FIG. 14, m-th gate bus line GB _m is then turned off voltage, elapsed t (several .mu.s), m 'th gate bus line GB _m' is turned off the voltage. As a result, the TFT 12 _3n is turned off after a few μs from the off state, so that the fluctuation of the pixel potential is reduced, and it is possible to prevent the afterimage and flicker as well as the crosstalk as in FIG.

Next, FIG. 17 shows a schematic block diagram of the fifth embodiment of the present invention. 7, those parts that are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted. 17A is a schematic configuration diagram, and FIG. 17B is an explanatory diagram of operation timing.

In FIG. 17A, two pixel electrodes 11 _n and 1 which are adjacent to each other in the direction parallel to the gate bus line (GB).
1 _{n + 1} is connected by an island-shaped storage capacitor electrode 21,
A resistor R ₂ is interposed between the gate G of the TFT 12 _{n + 1} and the gate bus line GB, and the other configuration is shown in FIG.
And the same as FIG. This resistance R ₂ is, for example, an amorphous silicon film (specific resistance 10 ⁹ Ω) as in the fourth embodiment.
cm) can be easily formed, and the resistor R ₂ and the gate capacitance of the TFT 12 _{n + 1} form a delay circuit having a time constant t (several μs).

The operation timing will now be described. As shown in FIG. 17B, when the gate bus line GB is turned on, the TFT 12 _n is turned on, and after t time (several μs), the TFT 12 _{n + 1} is turned on. It becomes a state. At this time, the nth data bus line DB is connected to the pixel electrode 11 _n.
n data is supplied from n, and (n is supplied to the pixel electrode 11 _{n + 1.}
(N + 1) data is supplied from the (+1) th data bus line DB _{n + 1} . Then, when the gate bus line GB is turned off, the TFT 12 _n is turned off.
T12 _{n + 1} is turned off after t time (several μs).

That is, since the TFT 12 _{n + 1} is still in the ON state when the gate bus line GB becomes the OFF voltage, the pixel electrode 11 _{n + 1} and the storage capacitor electrode 21 are not in the floating state and the storage capacitor is not. It functions as C _S.

As a result, the pixel electrodes, 11 _n , 11 _{n + 1}
It is possible to prevent the afterimage, flicker, and crosstalk from occurring due to the decrease in the potential fluctuation of (3), and it is possible to perform high-quality liquid crystal display.

[0074]

As described above, according to the first aspect of the invention, the area of the storage capacitor can be reduced as a whole, so that the aperture ratio can be increased and the display quality can be improved.
Further, the load capacitance of the bus line can be reduced, the signal delay can be suppressed, and the design condition of the material of the bus line can be relaxed.

According to the third aspect of the invention, the two signal electrodes adjacent to each other in the gate bus line direction are connected via the island-shaped storage capacitor electrode, and the signal voltage supplied to the adjacent data bus line is applied. Since the polarity of each can be reversed and applied at the same time to reduce the amount of electric charge leakage, a dedicated bus line is not required, and a storage capacitor can be provided without considering the material and shape. Therefore, a high quality liquid crystal display device can be realized.

Further, in the inventions according to claims 7 and 8,
A pixel signal, which is one of the divided pixel electrodes and is controlled by the gate signal of the gate bus line of the next stage by the third thin film transistor, is delayed by a gate signal delayed by a predetermined time from the gate signal of the gate bus line of the preceding stage. By controlling with the driven second thin film transistor, it is possible to prevent the occurrence of afterimages, flicker, and crosstalk that may occur due to the formation of the island-shaped storage capacitor electrode, and perform high-quality liquid crystal display. be able to.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram for explaining the principle of the invention according to claim 1.

FIG. 2 is an equivalent circuit diagram for explaining the principle of the invention according to claim 3.

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a third embodiment of the present invention.

8 is a cross-sectional view of FIG.

FIG. 9 is an equivalent circuit diagram of a third embodiment of the present invention.

FIG. 10 is an overall configuration diagram of an embodiment of the present invention.

FIG. 11 is a schematic configuration diagram of a modification of the third embodiment of the present invention.

12 is an explanatory diagram of the operation timing of FIG.

FIG. 13 is a schematic configuration diagram of a fourth embodiment of the present invention.

14 is an explanatory diagram of the operation timing of FIG.

FIG. 15 is a schematic configuration diagram of a modified example of the fourth embodiment of the present invention.

16 is an explanatory diagram of the operation timing of FIG.

FIG. 17 is a schematic configuration diagram of a fifth embodiment of the present invention.

FIG. 18 is a block diagram showing an example of one pixel of a conventional liquid crystal panel.

FIG. 19 is an equivalent circuit diagram of one pixel of a conventional liquid crystal panel.

FIG. 20 is a time chart showing an applied voltage of each bus line and an applied voltage of a liquid crystal cell.

FIG. 21 is an equivalent circuit diagram of a conventional C _S independent system.

FIG. 22 is an equivalent circuit diagram of a conventional C _{S on-} gate method.

[Explanation of symbols]

11, 11 _n , 11 _{n + 1} , 50 ₁ , 50 ₂ Pixel electrodes 11 _an , 11 _bn Divided pixel electrodes 12, 12 _n , 12 _{n + 1} , 51 ₁ , 51 ₂ , 52 ₁ , 5
2 ₂ , 53 ₁ , 53 ₂ , TR thin film transistor (TF
T) 13 Gate bus line drive driver 14,39 Inverter 15 C _GS correction capacitance electrode 16 Charge retention capacitance electrode 21 Storage capacitance electrode 33 Liquid crystal panel C _LC , C _LC1 , C _LC2 Liquid crystal capacitance C _Q Charge retention capacitance C _C C _GS correction Capacitance R _LC1 , R _LC2 Capacitance resistance C _X , C _S Storage capacitance DB, DB _n , DB _{n + 1} Data bus line GB, GB 'Gate bus line

Front Page Continuation (72) Inventor Kazuhiro Takahara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (10)

[Claims] 1. A plurality of data bus lines (DB) for supplying a signal voltage and a plurality of gate bus lines (GB) for supplying a scanning voltage intersect each other, and the gate bus lines (GB) at each intersection. A thin film transistor (TR) having a gate connected to the data bus line (DB) and a drain (or source) connected to the data bus line (DB), and a pixel electrode (1) connected to the source (or drain) of the thin film transistor (TR).
In a liquid crystal display device in which an active matrix substrate in which a storage capacitor electrode (C _S ) is connected in parallel is arranged to face a counter substrate via a liquid crystal, the storage capacitor electrode (C _S ) is connected to a charge storage capacitor electrode ( 1
6) and a capacitance electrode (15) for correcting the voltage drop of the pixel potential due to capacitive coupling with the gate bus line (GB), and the charge holding capacitance electrode (16) and the correction capacitance electrode (15) A liquid crystal display device characterized in that and are independently configured. 2. The liquid crystal display device according to claim 1, wherein a pulse having a polarity opposite to a pulse applied to the gate bus line (GB) is applied to the correction capacitor electrode (15). 3. A plurality of data bus lines (DB) for supplying a signal voltage and a plurality of gate bus lines (GB) for supplying a scanning voltage intersect with each other, and the gate bus lines (GB) at each intersection. A thin film transistor (TR) having a gate connected to the data bus line (DB) and a drain (or source) connected to the data bus line (DB), and a pixel electrode (1) connected to the source (or drain) of the thin film transistor (TR).
In an LCD device in which an active matrix substrate in which a storage capacitor electrode ( _CS ) and a storage capacitor electrode ( _CS ) are connected in parallel is arranged to face an opposing substrate via a liquid crystal, the storage capacitor electrode ( _CS ) is connected to the gate bus line ( A liquid crystal display device having an island-shaped electrode structure (21) for connecting between the two pixel electrodes adjacent to each other in units of the two pixel electrodes adjacent to each other in the direction parallel to the direction GB). . 4. The two pixel electrodes (11 _n , 11 _{n + 1} ) adjacent to each other connected to the island-shaped storage capacitor electrode (21) through the thin film transistors (12 _n , 12 _{n + 1} ) respectively. Two adjacent data bus lines (D
B _n , DB _{n + 1} ) is arranged at a position not intersecting with the island-shaped storage electrode (21).
The described liquid crystal display device. 5. The thin film transistors (12 _n , 12 _{n + 1} ) are provided to the two adjacent pixel electrodes (11 _n , 11 _{n + 1} ) connected to the island-shaped storage electrode (21), _respectively . Two adjacent data bus lines (D
The liquid crystal display device according to claim 3 or 4, wherein signal voltages having opposite polarities are applied to B _n and DB _{n + 1} ). 6. The two data bus lines (DB_n，
DB_{n + 1}Data bus line (D
B_{n + 1}) Connected to the thin film transistor (1
Two _{n + 1}), A delay means is formed at the gate of
The liquid crystal display device according to claim 3, 7. A plurality of data bus lines (DB) for supplying a signal voltage and a plurality of gate bus lines (GB) for supplying a scanning voltage intersect with each other, and the gate bus lines (GB) at each intersection. A thin film transistor (TR) having a gate connected to the data bus line (DB) and a drain (or source) connected to the data bus line (DB), and a pixel electrode (1) and a storage capacitor electrode (1) connected to the source (or drain) of the thin film transistor (TR). In a liquid crystal display device in which an active matrix substrate, which is connected in parallel with C _S ), is opposed to a counter substrate via a liquid crystal, a single pixel electrode (11 _n ) is parallel to the data bus line (DB). And a storage capacitor electrode (C _S ) having _an island-shaped electrode structure for connecting the divided pixel electrodes (11 _an , 11 _bn ). Crystal display device. 8. The divided pixel electrodes (11 _an , 1)
1 _bn ) on one side (11 _an ) of the gate bus line (G
The first thin film transistor controlled by B _m ) is connected to the other pixel electrode (11 _bn ), and the gate bus line (G
Second thin film transistor controlled by a delay means from B _m ) and the gate bus line (G
The liquid crystal display device according to claim 7, wherein a series circuit of a third thin film transistor controlled by B _{m + 1} ) is connected. 9. The control gate bus line for controlling the second thin film transistor by a gate signal delayed for a predetermined time by the gate bus line (GB _m ) instead of the delay means. 7. The liquid crystal display device according to 7. 10. The gate signal is applied at a timing when the gate bus line (GB _m ) and the next-stage gate bus line (GB _{m + 1} ) partially overlap each other. 9. The liquid crystal display device according to item 9.