KR101361057B1 - Display apparatus - Google Patents

Abstract

In the display device, a plurality of pixel parts are provided in a plurality of pixel areas defined by a plurality of gate lines and a plurality of data lines, each pixel part receiving a data signal in response to a gate signal to charge a first pixel voltage. A second pixel receives a data signal in response to one pixel and a gate signal and charges a second pixel voltage equal to the first pixel voltage. The plurality of voltage adjusting units level up the first pixel voltage charged in the current pixel unit in response to the next gate signal and level down the second pixel voltage. The dummy voltage controller is configured to level up the first pixel voltage of the last pixel portion connected to the last gate line and to level down the second pixel voltage of the last pixel portion. Therefore, the whitening phenomenon of the last pixel portion can be prevented.

Description

DISPLAY APPARATUS

1 is an equivalent circuit diagram of a pixel unit included in a display device according to an exemplary embodiment of the present invention.

FIG. 2A is an equivalent circuit diagram of an n-th pixel when an n-th gate signal is applied to an n-th gate line shown in FIG. 1.

FIG. 2B is an equivalent circuit diagram of the n-th pixel when the first gate signal is applied to the dummy gate line shown in FIG. 1.

3 is a waveform diagram illustrating a change in first and second pixel voltages according to an nth and a first gate signal.

4 is a layout of an n-th pixel illustrated in FIG. 1.

FIG. 5 is a cross-sectional view taken along the line II ′ of FIG. 4.

6 is a diagram illustrating a connection structure between a dummy gate line and a first gate line according to another exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of part II shown in FIG. 6.

8 is a plan view of a display device according to an exemplary embodiment.

9 is a plan view of a display device according to another exemplary embodiment of the present invention.

FIG. 10 is a block diagram of the gate driver illustrated in FIG. 9.

Description of the Related Art [0002]

100-display panel 110-array board

120-Opposing substrate 130-Liquid crystal layer

210-Data Driver 220-Gate Driver

300-display

The present invention relates to a display device, and more particularly, to a display device capable of improving display quality.

In general, a liquid crystal display device includes a lower substrate, an upper substrate opposed to the lower substrate, and a liquid crystal display panel formed of a liquid crystal layer formed between the lower substrate and the upper substrate to display an image. The LCD panel includes a plurality of gate lines, a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines.

The liquid crystal display device is inferior in viewing angle performance to other display devices. In order to solve such a viewing angle problem, a patterned vertical alignment (PVA) mode, a multi-domain vertical alignment (MVA) mode and a super-patterned vertical alignment (S- PVA) mode has been proposed.

The S-PVA mode liquid crystal display device includes pixels having two sub-pixels. In order to form domains having gray colors different from each other in the pixels, the two sub-pixels are divided into main and sub- Respectively. At this time, the eye of the person looking at the liquid crystal display recognizes the median value of the two sub-voltages, thereby preventing the gamma curve from being distorted below the mid-level gray level and thus reducing the side viewing angle. Thereby, side visibility of the liquid crystal display device can be improved.

S-PVA mode LCDs are classified into a coupling capacitor (CC) type and a two transistor (TT) type according to a driving method. The CC-type is a driving method in which a coupling capacitor is added between the main pixel electrode and the sub pixel electrode to drop the data voltage applied to the sub pixel electrode to apply a voltage lower than the main pixel voltage as the sub pixel voltage. The TT-type is a driving method for applying main and sub pixel voltages having different voltage levels to main and sub pixel electrodes using two transistors, respectively.

Korean Laid-Open Patent Publication No. 2005-0018520 proposes a new CC type S-PVA structure that improves the luminance reduction and character breakup of the conventional CC type S-PVA structure. However, since the voltage control of the main pixel and the subpixel is simultaneously performed with the turn-on of the next gate line in the liquid crystal display device according to the disclosed patent, the voltage of the last pixel line in which the next gate line does not exist is different. A whitening phenomenon occurs in which the luminance increases relative to the pixel line.

Accordingly, an object of the present invention is to provide a display device for preventing whitening of the last pixel line in a structure in which voltages of a main pixel and a subpixel are adjusted through adjacent gate lines of a CC type S-PVA structure.

According to an exemplary embodiment of the present invention, a display device includes a plurality of gate lines sequentially receiving a gate signal, an insulated intersection with the plurality of gate lines, a plurality of data lines receiving a data signal, the plurality of gate lines, and the plurality of data. It consists of a plurality of pixel units provided in one-to-one correspondence with a plurality of pixel regions defined by lines. Each pixel unit receives the data signal in response to the gate signal and charges a first pixel voltage and receives the data signal in response to the gate signal to receive a second pixel voltage equal to the first pixel voltage. It consists of a 2nd pixel to charge.

The display device includes a plurality of voltage adjusting units and a dummy voltage adjusting unit. The plurality of voltage adjusting units level up the first pixel voltage charged in the current pixel unit in response to a gate signal of a next stage, and level down the second pixel voltage. The dummy voltage controller is configured to level up the first pixel voltage of the last pixel part connected to the last gate line and to reduce the second pixel voltage of the last pixel part.

According to such a display device, by adding a dummy voltage adjusting unit for adjusting the voltage levels of the first and second pixel voltages of the last pixel portion, it is possible to prevent the side visibility from deteriorating in the last pixel portion. The display quality of the display device can be improved as a whole.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an equivalent circuit diagram of a pixel unit included in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment may include first to nth gate lines GL1 to GLn, first to mth data lines DL1 to DLm, and a dummy gate line D-GL. ) And a first connection line CL1. A plurality of pixel units are provided in a one-to-one correspondence in a plurality of pixel areas defined in a matrix form by the first to m th gate lines GL1 to GLn and the first to m th data lines DL1 to DLm.

In FIG. 1, an n−1 th pixel portion connected to an n−1 th gate line GLn−1 and an m th data line DLm, an n th gate line GLn, and an m th data line ( An equivalent circuit diagram of the n-th pixel portion connected to DLm) is shown. Here, each of the plurality of pixel units has the same structure. Therefore, hereinafter, the n-1 th pixel portion and the n th pixel portion will be described together.

Each pixel unit includes a first pixel P1 and a second pixel P2. The first pixel P1 includes a first thin film transistor T1, a first liquid crystal capacitor H-Clc, and a first storage capacitor H-Cst, and the second pixel P2 is a second thin film. The transistor T2 includes a second liquid crystal capacitor L-Clc and a second storage capacitor L-Cst.

In detail, the first thin film transistor T1 corresponds to a first gate electrode connected to a corresponding gate line (the n-th gate line GLn-1 or the n-th gate line GLn shown in FIG. 1). And a first source electrode connected to the data line (m-th data line DLm shown in FIG. 1) and a first drain electrode connected to the first liquid crystal capacitor H-Clc. The first liquid crystal capacitor H-Clc may include a first pixel electrode connected to the first drain electrode, a common electrode facing the first pixel electrode and applied with a common voltage Vcom, and the common with the first pixel electrode. It is defined by the liquid crystal layer (not shown) interposed between the electrodes. The first storage capacitor H-Cst is defined by the first pixel electrode, the storage electrode to which the common voltage is applied, and an insulating layer interposed between the first pixel electrode and the storage electrode.

The second thin film transistor T2 may correspond to a second gate electrode connected to a corresponding gate line (the n-th gate line GLn-1 or the n-th gate line GLn shown in FIG. 1). And a second source electrode connected to a data line (m-th data line DLm shown in FIG. 1) and a second drain electrode connected to the second liquid crystal capacitor L-Clc. The second liquid crystal capacitor L-Clc may include a second pixel electrode connected to the second drain electrode, the common electrode and the second pixel electrode facing the second pixel electrode and to which the common voltage Vcom is applied. It is defined by the liquid crystal layer interposed between the common electrode. The second storage capacitor L-Cst is defined by the second pixel electrode, the storage electrode to which the common voltage is applied, and an insulating layer interposed between the second pixel electrode and the storage electrode.

Gate signals are sequentially applied to the first to nth gate lines GL1 to GLn for one frame. Here, the time when the gate signal is applied to the first to nth gate lines GL1 to GLn is defined as a horizontal scan interval 1H. An operation of sequentially applying the gate signal to the first to nth gate lines GL1 to GLn in one frame unit is repeated.

Data signals are applied to the first to m th data lines DL1 to DLm. The data signal is output to the first to mth data lines DL1 to DLm in synchronization with the gate signals sequentially applied to the first to nth gate lines GL1 to GLn.

As illustrated in FIG. 1, when an n−1 th gate signal is applied to the n−1 th gate line GLn−1, first and second electrodes of the first and second pixels P1 and P2 are provided. The two thin film transistors T1 and T2 are turned on. Therefore, the data signal applied to the m th data line DLm passes through the first and second thin film transistors T1 and T2 and the first and second liquid crystal capacitors H-Clc and L-Clc. Is applied to the first and second pixel electrodes. Here, since the signals applied to the first and second pixel electrodes of the first and second liquid crystal capacitors H-Clc and L-Clc are the same, the first and second liquid crystal capacitors H-Clc and L are the same. -Clc) is charged with the same voltage. That is, when the voltages charged in the first and second liquid crystal capacitors H-Clc and L-Clc are defined as the first and second pixel voltages, the first and second periods during the n−1 th horizontal scanning period are defined. The pixel voltages have the same voltage level.

The display device is connected to the n-th gate line GLn and the n-th pixel part to adjust voltage levels of the first and second pixel voltages charged in the first and second pixels P1 and P2, respectively. It further includes a voltage adjusting unit (S1).

The voltage adjusting part S1 includes a third thin film transistor T3, a first up capacitor C-up1, and a first down capacitor C-down1. The third thin film transistor T3 includes a third gate electrode connected to the nth gate line GLn, a third source electrode connected to the second pixel electrode, the first down capacitor C-down1 and the first And a third drain electrode connected to the up capacitor C-up1.

The first down capacitor C-down1 is formed by the storage electrode, a cap electrode partially overlapping the storage electrode and connected to the third drain electrode, and an insulating layer interposed between the cap electrode and the storage electrode. Is defined. The first up capacitor C-up1 is formed by the first pixel electrode, the cap electrode partially overlapping the first pixel electrode, and an insulating layer interposed between the cap electrode and the first pixel electrode. Is defined.

When the third thin film transistor T3 is turned on in response to an nth gate signal applied to the nth gate line GLn, the second pixel electrode and the cap are formed by the third thin film transistor T3. The electrodes are electrically connected. Therefore, the voltage level of the first pixel voltage charged in the first liquid crystal capacitor H-Clc and the second pixel voltage charged in the second liquid crystal capacitor L-Clc is equal to the first up capacitor C. -up1) and the first down capacitor C-down1. Specifically, the first pixel voltage is leveled up by the first up capacitor C-up1 and the first down capacitor C-down1, and the second pixel voltage is leveled down. In this case, the level up level of the first pixel voltage and the level down level of the second pixel voltage are changed according to capacitance values of the first up capacitor C-up1 and the first down capacitor C-down1. .

The display device is connected to the dummy gate line D-GL and the n-th pixel part to adjust voltage levels of the first and second pixel voltages charged in the first and second pixels P1 and P2, respectively. The dummy voltage adjusting unit S2 is further included.

The dummy voltage controller S2 includes a fourth thin film transistor T4, a second up capacitor C-up2, and a second down capacitor C-down2. The fourth thin film transistor T4 includes a fourth gate electrode connected to the dummy gate line D-GL, a fourth source electrode connected to the second pixel electrode, the second down capacitor C-down2 and the fourth gate electrode. And a fourth drain electrode connected to the second up capacitor C-up2.

The second down capacitor C-down2 is formed by the storage electrode, a cap electrode partially overlapping the storage electrode and connected to the fourth drain electrode, and an insulating layer interposed between the cap electrode and the storage electrode. Is defined. The second up capacitor C-up2 is formed by the first pixel electrode, the cap electrode partially overlapping the first pixel electrode, and an insulating layer interposed between the cap electrode and the first pixel electrode. Is defined.

When the fourth thin film transistor T4 is turned on in response to the signal applied to the dummy gate line D-GL, the second pixel electrode and the cap electrode are connected by the fourth thin film transistor T4. Electrically connected. Therefore, the voltage level of the first pixel voltage charged in the first liquid crystal capacitor H-Clc and the second pixel voltage charged in the second liquid crystal capacitor L-Clc is equal to the second up capacitor C. -up2) and the second down capacitor C-down2. In detail, the first pixel voltage is leveled up by the second up capacitor C-up2 and the second down capacitor C-down2, and the second pixel voltage is leveled down.

As illustrated in FIG. 1, the dummy gate line D-GL is electrically connected to the first gate line GL1 through a first connection line CL1. Therefore, the first gate signal applied to the first gate line GL1 is applied to the dummy gate line D-GL. That is, after the n-th pixel unit is turned on in the current frame and the first gate signal is applied to the first gate line GL1 in the next frame, the dummy voltage controller S2 operates to operate the n-th pixel unit. Adjusting the voltage level of the first and second pixel voltage charged in the.

FIG. 2A is an equivalent circuit diagram of an n-th pixel when the n-th gate signal is applied to the n-th gate line illustrated in FIG. 1, and FIG. 2B is n when the first gate signal is applied to the dummy gate line illustrated in FIG. 1. 3 is an equivalent circuit diagram of the second pixel, and FIG. 3 is a waveform diagram illustrating changes of first and second pixel voltages according to the nth and first gate signals.

2A and 3, when the n-th gate signal Gn is generated in the i-th frame, the first and second thin film transistors T1 and T2 are turned on and the m-th data is turned on. The m-th data signal Dm applied to the line is applied to the first liquid crystal capacitor H-Clc and the second liquid crystal capacitor L-Clc via the first and second thin film transistors T1 and T2, respectively. do. Therefore, the first and second liquid crystal capacitors H-Clc and L-Clc are charged with first and second pixel voltages, respectively. As shown in FIG. 3, as an example of the present invention, the first and second pixel voltages have the same voltage level as 7V.

Here, the second up capacitor C-up2 and the second down capacitor C-down2 are connected in parallel with the first liquid crystal capacitor H-Clc while being connected in series with each other. Therefore, the 7V is divided by the voltage between the second up capacitor C-up2 and the second down capacitor C-down2. As an example of the present invention, an up voltage of 2V is charged in the second up capacitor C-up2, and a down voltage of 5V is charged in the second down capacitor C-down2.

2B and 3, the first gate signal G1 applied to the first gate line GL1 (shown in FIG. 1) is generated in the i + 1 th frame (i + 1-frame) to generate a dummy voltage. The fourth thin film transistor T4 of the controller S2 (shown in FIG. 1) is turned on. The second liquid crystal capacitor L-Clc and the second down capacitor C-down2 are connected in parallel by the turned-on fourth thin film transistor T4.

Therefore, charge sharing occurs between the second liquid crystal capacitor L-Clc and the second down capacitor C-down2. As a result, the second pixel voltage and the down voltage are changed to have the same voltage as each other at 6V. In this case, the sum of the down voltage and the up voltage increases from 7V to 8V, and the first pixel voltage charged in the first liquid crystal capacitor H-Clc also increases to 8V. Thus, after the first gate signal G1 is generated, the first pixel voltage is changed from 7V to 8V, and the second pixel voltage is changed from 7V to 6V.

As such, when different voltages are applied to the first and second pixels P1 and P2, the alignment angles of the liquid crystal molecules included in the liquid crystal layer are changed. As a result, the first and second pixels P1 and P2 display images of different gradations, and the user who uses the display device displays two images displayed by the first and second pixels P1 and P2. I admit it by mixing. Therefore, the side visibility of the display device can be improved.

4 is a layout of an n-th pixel illustrated in FIG. 1, and FIG. 5 is a cross-sectional view taken along the cutting line I-I ′ of FIG. 4.

4 and 5, the display device includes an array substrate 110, an opposing substrate 120 facing the array substrate 110, and an array substrate 110 between the array substrate 110 and the opposing substrate 120. It is made of an interposed liquid crystal layer 130.

An n-th gate line GLn, a dummy gate line D-GL, and a storage electrode CE1 formed of a gate metal are formed on the first base substrate 111 of the array substrate 110. The n-th gate line GLn and the dummy gate line D-GL extend in parallel to each other. The storage electrode CE1 is provided between the n-th gate line GLn and the dummy gate line D-GL, and the n-th gate line GLn and the dummy gate line D-GL. And electrically isolated. The common voltage is applied to the storage electrode CE1, and a gate signal is applied to the nth gate line GLn and the dummy gate line D-GL.

A fourth gate electrode GE1 and a second gate electrode GE2 branched from the n-th gate line GLn and a fourth branch branched from the dummy gate line D-GL on the first base substrate 111. The gate electrode GE4 is further provided.

A gate insulating layer 112 is further provided on the first base substrate 111 to cover the n-th gate line GLn, the dummy gate line D-GL, and the storage electrode CE1. On the gate insulating layer 112, an m-th data line DLm, first and second source electrodes SE1 and SE2 branched from the m-th data line DLm, and the first and second source electrodes SE1, First and second drain electrodes DE1 and DE2 are respectively spaced apart from SE2. As a result, a first thin film transistor T1 including the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 is formed on the array substrate 110, and the second gate The second thin film transistor T2 including the electrode GE2, the second source electrode SE2, and the second drain electrode DE2 is formed.

In addition, the gate insulating layer 112 further includes a fourth source electrode SE4 and a fourth drain electrode DE4 spaced apart from each other at predetermined intervals at positions corresponding to the fourth gate electrode GE4. Therefore, the fourth thin film transistor T4 including the fourth gate electrode GE4, the fourth source electrode SE4, and the fourth drain electrode DE4 is formed on the array substrate 110. The cap electrode CE2 branched from the fourth drain electrode DE4 and partially overlapped with the storage electrode CE1 is further provided on the gate insulating layer 112. A second down capacitor C-down2 is formed at a portion overlapping the cap electrode CE2 and the storage electrode CE1.

The array substrate 110 includes the first, second and fourth thin film transistors T1, T2, and T4, a passivation layer 113 covering the cap electrode CE2, and an organic insulating layer 114. The passivation layer 113 and the organic insulating layer 114 are sequentially stacked. The passivation layer 113 and the organic insulating layer 114 have a first contact hole C1 exposing the first drain electrode DE1 and a second contact hole C2 exposing the second drain electrode DE2. And a third contact hole C3 exposing the fourth source electrode SE4.

First and second pixel electrodes PE1 and PE2 are formed on the organic insulating layer 114. A first opening OP1 is formed between the first pixel electrode PE1 and the second pixel electrode PE2, and is electrically separated from each other by the first opening OP1.

The first pixel electrode PE1 is electrically connected to the first drain electrode DE1 through the first contact hole C1, and the second pixel electrode PE2 is connected to the second contact hole C2. The second drain electrode DE2 is electrically connected to the second drain electrode DE2 through the second drain electrode DE2. The first pixel electrode PE1 partially overlaps the storage electrode CE1 to form a first storage capacitor H-Cst, and the second pixel electrode PE2 partially overlaps the storage electrode CE1. Overlap with each other to form a second storage capacitor L-Cst.

The second pixel electrode PE2 is electrically connected to the fourth source electrode SE4 through the third contact hole C3. The first pixel electrode PE1 partially overlaps the cap electrode CE2. Therefore, a second up capacitor C-up2 is formed at a portion where the first pixel electrode PE1 and the cap electrode CE2 overlap each other.

The opposing substrate 120 includes a second base substrate 121, a black matrix 122, and a common electrode 123. The black matrix 122 is provided corresponding to an ineffective display area of the second base substrate 121, and the common electrode 123 is disposed on the black matrix 122 and the second base substrate 121. It is provided. A second opening OP2 is formed in the common electrode 123 to divide the first pixel electrode PE1 and the second pixel electrode PE2 into one or more domains. The second opening OP2 is formed at a position different from the first opening OP1.

The liquid crystal layer 130 is interposed between the counter substrate 120 and the array substrate 120. Accordingly, a first liquid crystal capacitor H-Clc is formed by the common electrode 123, the first pixel electrode PE1, and the liquid crystal layer 130, and the common electrode 123 and the second pixel. The second liquid crystal capacitor L-Clc is formed by the electrode PE2 and the liquid crystal layer 130.

6 is a diagram illustrating a connection structure between a dummy gate line and a first gate line according to another exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of part II shown in FIG. 6.

6 and 7, the dummy gate line D-GL is electrically connected to the first gate line GL1 through the first connection line CL1. The first connection line CL1 connects a first end of the first gate line GL1 and a first end of the dummy gate line D-GL. The first connection line CL1 is provided in a region where the first to nth gate lines GL1 to GLn are not provided and does not cross the first to nth gate lines GL1 to GLn. Therefore, the first connection line CL1 may be formed of a gate metal in the same manner as the first to nth gate lines GL1 to GLn.

In addition, the dummy gate line D-GL and the first gate line GL1 are electrically connected to each other through a second connection line CL2. The second connection line CL2 connects the second end of the first gate line GL1 and the second end of the dummy gate line D-GL. Since the second connection line CL2 is formed in a region where the first to nth gate lines GL1 to GLn are provided, the second metal connection line CL2 is insulated from and intersects the first to nth gate lines GL1 to GLn in an insulated manner. Is made of.

As illustrated in FIG. 7, the second connection line CL2 is provided on the gate insulating layer 112 covering the first to nth gate lines GL1 to GLn. The gate insulating layer 112 has a fourth contact hole 112a exposing a second end of the dummy gate line D-GL and a fifth contact hole exposing a second end of the first gate line GL1. 112b is formed. Therefore, the second connection line CL2 is electrically connected to the second end of the dummy gate line D-GL through the fourth contact hole 112a and through the fifth contact hole 112b. It is electrically connected to a second end of the first gate line GL1.

As such, the dummy gate line D-GL is electrically connected to the first gate line GL1 through the first and second connection lines CL1 and CL2, and thus, is connected to the first gate line G1. The delay time required for the first gate signal applied to the dummy gate line D-GL may be reduced.

8 is a plan view of a display device according to an exemplary embodiment.

Referring to FIG. 8, the display device 300 displays a display panel 100 for displaying an image, a data driver 210 for applying a data signal to the display panel 100, and a gate signal to the display panel 100. The gate driver 220 is applied.

The display panel 100 serves to display an image, and since the structure of the display panel 100 has been described in detail with reference to FIGS. 1 to 7, the description of FIG. 8 will be omitted.

The data driver 210 is electrically connected to the first to m th data lines DL1 to DLm. The data driver 210 generates a data signal and applies the data signal to the first to m th data lines DL1 to DLm. As an example of the present invention, the data driver 210 has a plurality of chip types. The chips may be mounted on the display panel 100 or on a film attached to the display panel 100.

The gate driver 220 is electrically connected to the first to nth gate lines GL1 to GLn. The gate driver 220 generates a gate signal and sequentially applies the gate signal to the first to nth gate lines GL1 to GLn. As an example of the present invention, the gate driver 220 has a plurality of chip forms. The chips may be mounted on the display panel 100 or on a film attached to the display panel 100.

As another example, the gate driver 220 may be formed directly on the display panel 100 through a thin film process. A structure in which the gate driver 220 is formed directly on the display panel 100 in the form of an amorphous silicon gate (ASG) will be described in detail with reference to FIGS. 9 and 10.

9 is a plan view of a display device according to another exemplary embodiment. FIG. 10 is a block diagram of the gate driver illustrated in FIG. 9. Of the components illustrated in FIG. 9, the same reference numerals are given to the same components as those illustrated in FIG. 8, and detailed description thereof will be omitted.

Referring to FIG. 9, a gate driver 230 having an amorphous silicon gate (ASG) shape is directly formed on the display panel 100 through a thin film process.

The gate driver 230 is electrically connected to the first to nth gate lines GL1 to GLn and the dummy gate line D-GL provided on the display panel 100. The gate driver 230 generates a gate signal and sequentially applies the gate signals to the first to n-th gate lines GL1 to Gln, and generates a dummy gate signal and applies it to the dummy gate line D-GL. Accordingly, unlike the exemplary embodiment of the present invention illustrated in FIG. 8, the dummy gate line D-GL is connected to the first gate line GL1 and does not receive the first gate signal as the dummy gate signal.

Referring to FIG. 10, the gate driving circuit 210 includes a plurality of stages SRC1 to SRCn + 1 that are connected to each other dependently. Each stage includes a first input terminal IN1, first and second clock terminals CK1 and CK2, a second input terminal IN2, a voltage input terminal V1, a reset terminal RE, and an output terminal OUT. And a carry terminal CR.

The first input terminal IN1 of the plurality of stages SRC1 to SRCn + 1 is electrically connected to the carry terminal CR of the previous stage to receive the previous carry voltage. However, the first input terminal IN1 of the first stage SRC1 among the plurality of stages SRC1 to SRCn + 1 is provided with a start signal STV for starting the gate driving circuit 210. The second input terminal IN2 of the plurality of stages SRC1 to SRCn + 1 is electrically connected to the output terminal OUT of the next stage and receives a next gate voltage. However, the start signal STV is provided to the second input terminal IN2 of the last stage SRCn + 1 among the plurality of stages SRC1 to SRCn + 1.

A first clock CKV is provided to a first clock terminal CK1 of odd-numbered stages SRC1, SRC3, ... SRCn + 1 of the plurality of stages SRC1 to SRCn + 1, and a second clock terminal is provided. A second clock CKVB having a phase inverted with the first clock CKV is provided at CK2. The second clock CKVB is provided to the first clock terminal CK1 of the even-numbered stages SRC2 to SRCn among the plurality of stages SRC1 to SRCn + 1, and the second clock terminal CK2 is provided. The first clock CKV is provided.

A source power supply voltage VSS is provided to voltage input terminals Vin of the plurality of stages SRC1 to SRCn + 1. In addition, the output terminal OUT of the last stage SRCn + 1 is electrically connected to the reset terminal RE of the plurality of stages SRC1 to SRCn + 1.

The first to third gate lines GL1 to GLn are electrically connected to the output terminals OUT of the first to nth stages SRC1 to SRCn among the plurality of stages SRC1 to SRCn + 1. Accordingly, the first to n th stages SRC1 to SRCn sequentially output gate signals through the output terminals OUT and apply them to the first to nth gate lines GL1 to GLn.

Meanwhile, the dummy stage SRCn + 1 of the plurality of stages SRC1 to SRCn + 1 is provided to reset the nth stage SRCn. That is, each of the first to nth stages SRC1 to SRCn is reset by a next stage, and the gate driver 230 resets the nth stage SRCn where no next stage exists. The dummy stage SRCn + 1 is added. Therefore, the output terminal OUT of the dummy stage SRCn + 1 is connected to the second input terminal IN2 of the nth stage SRCn, and the dummy gate signal output from the dummy stage SRCn + 1. By this, the nth stage SRCn is reset.

As shown in FIG. 9, when the display panel 100 includes a dummy gate line D-GL, an output terminal OUT of the dummy stage SRCn + 1 is electrically connected to the dummy gate line. do. Therefore, the dummy gate signal output from the dummy stage SRCn + 1 is applied to the dummy gate line D-GL. The dummy gate signal applied to the dummy gate line D-GL is a voltage of the first and second pixel voltages charged in the first and second pixels P1 and P2 of FIG. 1. Adjust the level.

According to an exemplary embodiment of the present invention, a first gate signal is input as the dummy gate signal from a first gate line GL1 operating in a next frame, and the first and second pixels P1 and P2 of the n-th pixel portion are shown in FIG. The first and second pixel voltages applied to the first and second pixel voltages are adjusted. However, there is a blank period in which the gate lines are not turned on between the frame sections in units of frames. Therefore, in the embodiment of the present invention illustrated in FIG. 1, the blank period at which the time point at which the first and second pixel voltages applied to the first and second pixels P1 and P2 of the n-th pixel part is adjusted is adjusted. Delayed by.

According to another embodiment of the present invention, since the dummy gate signal output from the dummy stage SRCn + 1 is generated immediately after the n-th 1H section in which the n-th pixel portion is turned on, the first and the nth pixel portions The first and second pixel voltages applied to the second pixels P1 and P2 may be adjusted immediately after the nth 1H period. Therefore, in another embodiment of the present invention, it is possible to prevent the voltage adjustment time point from being delayed.

Meanwhile, as shown in FIG. 10, the start signal STV indicating the start of one frame is applied to the second input terminal IN2 of the dummy stage SRCn + 1. Therefore, the dummy stage SRCn + 1 in which the next stage does not exist is reset in response to the start signal STV.

Although not illustrated in the drawing, the gate driver 230 is formed of a plurality of chips and mounted on the display panel 100, and the last of the plurality of chips outputs the gate signal to the n-th gate line GLn. The chip may be implemented to output the dummy gate signal for driving the dummy gate line.

According to such a display device, a dummy voltage adjuster for adjusting the voltage levels of the first and second pixel voltages of the last pixel portion is added, and the dummy voltage adjuster is first gated through a dummy gate line electrically connected to the first gate line. It operates by receiving a signal.

Accordingly, the whitening phenomenon does not occur in the last pixel portion, and as a result, the display quality of the display device may be improved as a whole.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (18)

A plurality of gate lines sequentially receiving a gate signal; A plurality of data lines crossing the plurality of gate lines insulated from each other and receiving a data signal; A first pixel that receives the data signal in response to the gate signal and charges a first pixel voltage; and a second pixel that receives the data signal in response to the gate signal and charges a second pixel voltage; A plurality of pixel units provided in one-to-one correspondence with a plurality of pixel areas defined by a plurality of gate lines and the plurality of data lines; A voltage adjusting unit for leveling up the first pixel voltage charged in the current pixel unit in response to a next gate signal, and for lowering the second pixel voltage; And A dummy voltage adjuster configured to level up the first pixel voltage of the last pixel portion connected to the last gate line and to downgrade the second pixel voltage of the last pixel portion; Wherein the first pixel comprises: A first switching element configured to output the data signal in response to the gate signal; And And a first liquid crystal capacitor connected to an output terminal of the first switching element, the first pixel electrode receiving the data signal and the common electrode receiving the common voltage to charge the first pixel voltage. The second pixel, A second switching element configured to output the data signal in response to the gate signal; And A second liquid crystal capacitor connected to an output terminal of the second switching element, the second pixel electrode receiving the data signal and the common electrode to charge the second pixel voltage equal to the first pixel voltage; The voltage control unit, A first down capacitor defined by the storage electrode receiving the common voltage and a first cap electrode facing the storage electrode; A first up capacitor defined by the first pixel electrode and the first cap electrode; And A third switching device electrically connecting the second pixel electrode and the first cap electrode in response to the next gate signal; The dummy voltage controller, Dummy gate lines; A second down capacitor defined by the storage electrode and a second cap electrode facing the storage electrode; A second up capacitor defined by the first pixel electrode and the second cap electrode; And And a fourth switching element electrically connecting the second pixel electrode and the second cap electrode in response to a signal applied to the dummy gate line. The display device of claim 1, wherein the second pixel voltage has the same voltage level as the first pixel voltage before the voltage is adjusted. The method of claim 1, wherein the dummy voltage adjuster comprises a dummy gate line. And raising the first pixel voltage of the last pixel portion in response to the dummy gate signal applied to the dummy gate line, and lowering the second pixel voltage of the last pixel portion. 4. The dummy gate line of claim 3, wherein the dummy gate line is electrically connected to a first gate line of the plurality of gate lines, and a first gate signal applied to the first gate line is applied as the dummy gate signal to the dummy gate line. Display device. 4. The gate driving circuit of claim 3, further comprising a gate driver electrically connected to the plurality of gate lines to sequentially output the gate signal. And the gate driver is electrically connected to the dummy gate line to provide the dummy gate signal. delete delete delete The display device of claim 1, wherein the first and second cap electrodes are provided on the same layer as the plurality of data lines. The display device of claim 1, wherein the first up capacitor is formed in an area where the first cap electrode overlaps the first pixel electrode. And the second up capacitor is formed in a region where the second cap electrode of the last pixel portion overlaps the first pixel electrode. The display device of claim 1, wherein the dummy gate line is electrically connected to a first gate line of the plurality of gate lines, and a first gate signal applied to the first gate line is applied to the dummy gate line. The method of claim 11, wherein the dummy voltage adjusting unit, And at least one connection line electrically connecting the dummy gate line and the first gate line. The method of claim 12, wherein the one or more connection lines, And a first connection line provided on the same layer as the plurality of gate lines and not overlapping the plurality of gate lines. The method of claim 12, wherein the one or more connection lines, And a second connection line provided on the same layer as the plurality of data lines and overlapping the plurality of gate lines. The method of claim 1, wherein the first pixel, A first storage capacitor defined by the storage electrode and the first pixel electrode and connected in parallel with the first liquid crystal capacitor; The second pixel, And a second storage capacitor defined by the storage electrode and the second pixel electrode and connected in parallel with the second liquid crystal capacitor. delete delete delete

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