JP3327287B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type liquid crystal display device, and more particularly, to an active matrix type liquid crystal display device which can be driven at a high contrast or at a low voltage.

[0002]

2. Description of the Related Art As shown in FIGS. 13 and 14, a conventional general active matrix type liquid crystal display device includes a thin film transistor array substrate 150 and a transparent transparent substrate provided in parallel with the thin film transistor array substrate 150. This is a schematic configuration including a counter substrate (glass substrate) 140 and a liquid crystal layer 130 sealed between the thin film transistor array substrate 150 and the counter substrate 140. FIG.
FIG. 3 is a plan view showing a unit pixel of the thin film transistor array substrate 150 below the liquid crystal layer 130 of the active matrix type liquid crystal display device shown in FIG. 14 (the orientation film 18 is omitted in FIG. 13). 14 is X in FIG.
FIG. 14 is a cross-sectional view taken along the line X, and also shows a portion above the thin film transistor array substrate 150.

In FIG. 13, a thin film transistor (TF)
T) is a gate electrode 1, an amorphous silicon film 119,
It comprises a drain electrode 3 and a source electrode 4. The gate electrode 1 is electrically connected to its own scanning line 11, the drain electrode 3 is electrically connected to its own signal line 12, and the source electrode 4 is electrically connected to the pixel electrode 5. Reference numeral 13 denotes an adjacent signal line, and a unit pixel is formed in a region surrounded by the scanning line 11, the preceding scanning line 101, and the signal lines 12 and 13.

In the liquid crystal display device having such a configuration, when the above-mentioned TFT is turned on for each matrix segment, an electric field is generated between the pixel electrode 5 and the counter electrode 123, and the electric field is sealed between the substrates 100 and 140. Liquid crystal layer 1
Numeral 30 causes an electro-optic effect so that an image can be displayed on the entire panel.

FIG. 15 is a diagram showing the parasitic capacitance between the gate and the source of the TFT. As shown in FIG. 15, in an active matrix type liquid crystal display device using a TFT, a gate-source parasitic capacitance Cgs is formed in a region where a gate electrode 1 and a source electrode 4 and a drain electrode 3 overlap each other in a TFT portion. Occurs.

FIG. 16 is a diagram showing an equivalent circuit of one pixel of a conventional liquid crystal display device having a TFT element. In FIG. 16, a parasitic capacitance Cgs is a parasitic capacitance between the gate electrode 1 and the source electrode 4 of the TFT, and CLC is a pixel electrode 5 and a counter electrode 12.
The capacitance of the liquid crystal layer 130 between the three, and Csc is a storage capacitance formed between the pixel electrode 5 and the scanning line 101.

FIG. 17 is a diagram showing a voltage waveform for driving the liquid crystal display device. When the potential of the gate electrode 1 is high, charges are gradually accumulated in the pixel electrode 5 and the potential of the pixel electrode 5 is reduced. Approaches the potential of the signal line. Here, when the gate potential is turned off, the potential of the pixel electrode 105 is reduced by being negatively pulled by the gate potential via the parasitic capacitance Cgs. This drop ΔV is called a feedthrough voltage.

In general, when focusing on one display pixel in order to ensure reliability, the liquid crystal display device is driven by applying an AC voltage having a different polarity for each display frame between the counter electrode 123 and the pixel electrode 5. I have to. Parasitic capacitance C of TFT
gs can be regarded as a MIS (Metal-Insulator-Semiconductor) capacitor. However, the applicant has determined that the effective value of the MIS capacitance differs between the positive writing and the negative writing, and the feedthrough voltage ΔV is large. It was found from the qualitative analysis that not only the difference between the positive writing and the negative writing but also the ΔV was larger in the case of the negative writing. The details will be described in detail in the description of the embodiments of the present invention, and will be described only briefly here.

In other words, the voltage applied to the liquid crystal layer is the difference between the potential of the common electrode and the potential of the pixel electrode (ΔVPI in FIG. 17). Considering that writing is switched for each frame, as the feedthrough voltage of negative writing is higher than the feedthrough voltage of positive writing, the time (non-selection period) other than the selection period (time during which the gate potential is high) is higher. This means that the voltage applied to the liquid crystal layer increases (ΔVPI increases). In addition, it has been qualitatively found that the difference between the feed-through voltage at the time of positive writing and that at the time of negative writing increases as the absolute value of Cgs increases (however, the ratio is almost equal).

This phenomenon is caused by increasing the size of the TFT or installing a plurality of TFTs, that is, by increasing the MIS capacitance coupled to the scanning line 11 and the pixel electrode 5 to increase the voltage larger than the voltage applied from the outside to the liquid crystal layer. The applicant has paid attention to the fact that it suggests that there is a possibility that an effect can be applied. However, in general, when the area of the TFT is increased, the aperture ratio is reduced, and the charge leakage at the time of off-state becomes a problem. Further, if a large delay occurs in the gate pulse, a considerable amount of charge flows into the pixel electrode before the TFT is turned off, and the voltage amplification effect is reduced.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in consideration of a conventional active matrix type liquid crystal display device. It is an object of the present invention to provide an active matrix type liquid crystal display device which is improved so as not to cause a problem such as a reduction in voltage amplification effect and can be driven at a high contrast or at a low voltage.

[0012]

According to the present invention, there are provided a plurality of scanning lines formed on an insulating substrate, a plurality of signal lines formed to intersect the scanning lines, and a plurality of scanning lines and signal lines. In an active matrix liquid crystal display device including a thin film transistor array substrate including a thin film transistor formed near an intersection and an additional capacitance portion connected to a pixel electrode connected to a source electrode of the thin film transistor, a part of the additional capacitance portion is provided. An active matrix liquid crystal display device characterized by being formed with an insulating film and a semiconductor between a scanning line connected to a gate electrode of a thin film transistor for switching the pixel electrode and a semiconductor is provided as a means for solving the above problem. .

[0013] In the active matrix type liquid crystal display device having the above structure, the semiconductor installation region provided between the pixel electrode and the scanning line partially overlaps the intersection of the signal line and the scanning line. Is preferred.

In the active matrix type liquid crystal display device having the above configuration, it is preferable that the semiconductors are formed in a line on the scanning lines.

In the active matrix type liquid crystal display device having the above configuration, it is preferable that the pixel electrode and the preceding scanning line are overlapped at a portion where the preceding semiconductor is not formed.

In the active matrix type liquid crystal display device having any one of the above structures, it is preferable that the semiconductor provided between the pixel electrode and the scanning line is made of an amorphous silicon film.

In the active matrix type liquid crystal display device having any one of the above structures, the semiconductor provided between the pixel electrode and the scanning line may be made of a polycrystalline silicon film. .

[0018]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 show an active matrix type liquid crystal display device according to a first embodiment of the present invention.
As shown in the figure, a thin film transistor array substrate 250,
A transparent counter substrate (glass substrate) 140 provided in parallel with and separated from the thin film transistor array substrate 250;
The thin film transistor array substrate 250 and the opposing substrate 14
0 is a schematic configuration including a liquid crystal layer 130 sealed between the liquid crystal layer 130 and the liquid crystal layer 130. FIG. 1 is a plan view showing a unit pixel of the thin film transistor array substrate 250 below the liquid crystal layer 130 of the active matrix type liquid crystal display device of the first embodiment shown in FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1 and also shows a portion above the thin film transistor array substrate 250.

In FIG. 1, a thin film transistor (TF)
T) is a gate electrode 1, an amorphous silicon film 119,
It comprises a drain electrode 3 and a source electrode 4. The gate electrode 1 is electrically connected to its own scanning line 11, the drain electrode 3 is electrically connected to its own signal line 12, and the source electrode 4 is electrically connected to the pixel electrode 5. Reference numeral 13 denotes an adjacent signal line, and a unit pixel is formed in a region surrounded by the scanning line 11, the preceding scanning line 101, and the signal lines 12 and 13. In order to form a storage capacitor, the upper side of the pixel electrode 5 and the lower side of the preceding scanning line 101 are overlapped via the gate insulating film 115. Similarly, the lower side of the scanning line 11 of the own stage overlaps with the upper side of the pixel electrode of the next stage to form a storage capacitor portion. Reference numeral 120 denotes an amorphous silicon film for forming an additional capacitance according to the present invention, which is provided along the upper side of the scanning line 11 of the own stage.

In order to manufacture the active matrix type liquid crystal display device of the first embodiment shown in FIGS. 1 and 2, first, a metal such as a Cr film is formed on a glass substrate 100 as a transparent insulating substrate by a sputtering method. A film is deposited and selectively etched to form a gate electrode 1 and a scanning line 11. Thereafter, a silicon nitride film is deposited on the surface including the gate electrode 1 and the scanning lines 11 by a CVD (Chemical Vapor Deposition) method to form a gate insulating film (insulating film) 115. Next, a gate insulating film 11 corresponding to the gate electrode 1 is formed.
Amorphous silicon film 11 which forms a semiconductor region by CVD so as to partially overlap with scanning line 5 and scanning line 11
9, 120 and these amorphous silicon films 119, 1
An n + -type amorphous silicon film 119a, 120a as an ohmic contact layer is selectively formed on the gate insulating film 115, and an ITO (indium oxide) film as a transparent electrode is formed on the gate insulating film 115 in the preceding scanning line 101.
And the pixel electrode 5 is selectively provided so as to partially overlap the amorphous silicon film 120 and the scanning line 11.

Next, the n + -type amorphous silicon layer 119a in the region corresponding to the gate electrode 1 is removed using the source and drain electrodes 4, 3 and the pixel electrode 5 as a mask, and a TFT is formed. Then, the TFT and the signal line 1
When the passivation 117 is formed for the purpose of covering and protecting the scan lines 2 and 13 and the scan lines 11 and 101, a thin film transistor array substrate 250 is obtained. Here, as shown in FIG. 1, a storage capacitor Csc is formed at an overlapping portion of the upper side of the pixel electrode 5 and the lower side of the preceding scanning line 101. And
To align the liquid crystal layer 130, an alignment film 18 made of an organic film such as a polyimide resin is formed on the passivation film 117 and subjected to an alignment process.

On the other hand, an opaque light-shielding layer 121, a color layer 122, and ITO are formed on the lower surface of the glass substrate 140 on the upper side of the counter electrode with the liquid crystal layer 130 interposed therebetween, that is, on the surface facing the glass substrate 100. The counter electrode 123 and the alignment film 28 are formed in this order.

FIG. 3 shows an equivalent circuit diagram of one pixel of the active matrix type liquid crystal display device according to the first embodiment of the present invention. The difference between the equivalent circuit of one pixel of the liquid crystal display device of the present embodiment and the equivalent circuit diagram of one pixel of the conventional active matrix type liquid crystal display device shown in FIG. A new MIS (Metal-Insula
tor-semiconductor) capacitance is formed.
That is, the difference from the conventional active matrix type liquid crystal display device is that the amorphous silicon film 120 is provided so as to overlap the scanning line 11 and the pixel electrode 5. Since the amorphous silicon film 120 can be formed at the same time as the step of forming the amorphous silicon film 119 in the TFT portion, there is no increase in the number of manufacturing steps and materials.

Next, the operation of the active matrix type liquid crystal display device of the first embodiment will be described.

The active matrix type liquid crystal display device of the first embodiment is similar to the conventional active matrix type liquid crystal display device in that the above-described TFT is provided for each matrix segment.
Is turned on, an electric field is generated between the pixel electrode 5 and the counter electrode 123, and the liquid crystal layer 130 sealed between the two substrates 100 and 140 causes an electro-optical effect, so that an image can be displayed on the entire panel. Become.

An operational difference between the liquid crystal display device of the present embodiment and the prior art is that the difference between the feedthrough voltage at the time of positive writing and the feedthrough voltage at the time of negative writing is larger than that of the prior art. The reason will be described below.

As calculated from the equivalent circuit of FIG. 3, the feedthrough voltage ΔV in the first embodiment is represented by the following approximate expression (1).

ΔV = (Vgon−Vgoff) * (Cgs + Cg−PI) / (Cgs + Cg−PI + CLC + Csc) (1) M connected to the gate electrode 1, the scanning line 11 and the pixel electrode 5
As the IS capacity, the gate-source capacity C in the TFT section
In addition to gs, a new scanning line 11-gate insulating film 115-
Capacitance Cg-PI formed by amorphous silicon film 120
Is provided. Then, the absolute value of the feed-through voltage increases based on the phenomenon described in the conventional technique, and the difference between the feed-through voltage at the time of positive writing and that at the time of negative writing increases. In the present invention, since the total amount of the MIS capacitance is large, the voltage applied between the counter electrode 123 and the pixel electrode 5 increases as compared with the conventional one. At this time, it is qualitatively described that the effect is larger as the applied MIS capacity is larger.

Referring to the equivalent circuit of FIG. 16 and the voltage waveform of FIG. 17, the feedthrough voltage ΔV
Is approximately derived as in equation (2). Where Vgo
n and Vgoff mean a high level voltage and a low level voltage of the gate voltage waveform, respectively.

ΔV = (Vgon−Vgoff) * Cgs / (CLC + Csc + Cgs) (2) Since the capacitance CLC of the liquid crystal layer 130 varies depending on the display state of the liquid crystal, it depends on the display state (white, halftone, black). V is different. A voltage that is the center of the pixel electrode potential in halftone display with the highest visibility is applied to the counter electrode 123 to prevent flicker.

In general, when focusing on one display pixel in order to ensure reliability, the liquid crystal display device is driven by applying an AC voltage having a different polarity between the counter electrode 123 and the pixel electrode 5 for each display frame. I have to.

Next, it will be described that the magnitude of the feedthrough voltage ΔV shown in the above equation (2) is different between the time of positive writing and the time of negative writing. This is due to the fact that the effective value of the parasitic capacitance Cgs differs between a positive write and a negative write.

The reason why the effective value of the parasitic capacitance Cgs causes a difference will be described in the following order.

First, the MIS shown in FIGS.
(Metal-Insulator-Semiconductor) Using a capacitor, the capacitance C between the gate electrode and ground and the gate voltage V
The relationship of G is determined.

The capacitance C can be regarded as a series connection of the capacitance Co of the gate insulating film and the capacitance Cs of the amorphous silicon film.
Assuming that the thickness of the oxide film (gate insulating film 115) is td, its relative dielectric constant is Ko, and the dielectric constant of vacuum is εo, the fixed capacitance Co per unit area of the oxide film is: Co = Koεo / td. (3) It is shown by. Next, the capacity of the amorphous silicon film differs depending on the distribution of generated carriers, and this distribution depends on the application of the gate voltage VG (Reference: "Basics of Amorphous Semiconductor", pp. 164 to 168, Ohmsha, 1982, January 1).
Published on January 30).

FIG. 5 is a diagram showing a change in the MIS capacitance when the gate is turned on and off. When an on-voltage is applied to the gate electrode 1, as shown in FIG. Carriers are generated. The carriers are distributed by the drift current flowing through the carriers due to the electric field in the amorphous silicon film 119a and the diffusion current flowing due to the density gradient of the carriers. In this case, in consideration of the above discussion and the fact that in the liquid crystal display device, the amorphous silicon film 119a is slightly exposed to light due to light reflection inside the panel and photocarriers are generated, it is considered that most carriers exist in the entire film. It can be approximated, and the capacitance Cs of the amorphous silicon film 119a can be regarded as Cs = 0 (4).

Next, when an off-voltage is applied to the gate electrode 1, that is, when the connection between the drain electrode 3 and the source electrode 4 is approximately opened in FIG. 15, as shown in FIG. Since the carrier density in the amorphous silicon film 119a is low, it can be regarded as almost an insulating film. That is, the variable capacitance Cs per unit area formed by the amorphous silicon film 119a is as follows: where the thickness of the amorphous silicon film is 1d and the dielectric constant is K, Cs = Kεo / ld (5). (Of course, if the gate voltage is further reduced, holes are formed and the state becomes close to that of FIG. 5A.) Considering the above, a C-VG curve is qualitatively drawn as shown in FIG. That is, when the MIS capacitance in the ON state of the TFT and the MIS capacitance in the OFF state are compared, the MIS capacitance in the ON state is qualitatively larger. Where TFT
It should be noted that the gate voltage at which is turned on is not absolutely determined, but is relatively determined depending on the potentials of the source electrode and the drain electrode.

Next, the reason why the magnitude of the feedthrough voltage ΔV differs between the case where a positive potential is written with respect to the common electrode potential and the case where a negative potential is written with reference to FIG. 7 will be qualitatively considered. .

When the TFT characteristics are approximated by two values of an on state and an off state, the MIS capacitance in each state, that is, the capacitance Cgs between the gate and the source electrode in the case of the TFT is different as described above. That is, when the gate voltage TFT is turned on to be written as Vth (threshold voltage), which is _{Cgs (V G> V th)} > Cgs (V G <V th) ··· (6).

[0041] When the above equation (2) rewrite considering equation (6), △ V = { (Vgon-Vth) * Cgs (V G> V th) / (CLC + Csc + Cgs (V G> V th))} + a {(Vth-Vgoff) * Cgs (V G <V th) / (CLC + Csc + Cgs (V G <V th))} ··· (7).

As described above, the threshold voltage Vth of the TFT is determined by the relative relationship between the source electrode potential and the drain electrode potential. Therefore, in FIG. 7, positive writing to the pixel in the liquid crystal display device, that is, the common electrode potential is applied to the pixel electrode. On the other hand, in the case of writing a positive potential, since a positive potential is applied to the common electrode for both the drain and source electrodes, the gate potential Vth at which the TFT turns off becomes relatively high as shown in FIG. I have.

On the other hand, in the case of negative writing, that is, writing a negative potential with respect to the common electrode potential to the pixel electrode,
Since a negative potential is applied to the common electrode for both the drain and source electrodes, the gate potential at which the TFT turns off is relatively low as shown in FIG. 7B.

From the result of the discussion on the gate voltage dependence of the MIS capacitance, the gate-source capacitance Cgs when the TFT is on is larger than the gate-source capacitance when the TFT is off (Equation (6)). ). Then, it can be seen from Expression (7) that in the case of negative writing, ΔV increases as Vth is lower (Vgon−Vth is larger).

However, during the on-time, a certain amount of current flows from the drain electrode 3 to the pixel electrode 5, so that the effect due to the variation of Cgs is slightly alleviated. Where a
Considering the on-resistance (〜１０10 ₆ ohms) of the TFT having -Si as the active region, the flowing current is very small. The voltage applied to the liquid crystal layer is the difference between the potential of the common electrode and the potential of the pixel electrode (ΔVPI in FIG. 17). In general, a liquid crystal display device performs positive writing and negative writing for each frame in order to ensure reliability. Considering that the switching is performed, as the feedthrough voltage of the negative write is higher than the feedthrough voltage of the positive write, the voltage is applied to the liquid crystal layer during a non-selection period (non-selection period) other than the selection section (gate potential high time). Voltage (大 き く VPI is large). The difference between the feed-through voltage at the time of positive writing and the feed-through voltage at the time of negative writing increases as the absolute value of Cgs increases (however, the ratio is almost equal). Therefore, in the present invention, a voltage amplification effect that a voltage higher than the voltage applied from the outside can be applied to the liquid crystal layer can be obtained by increasing the MIS capacitance coupled to the scanning line 11 and the pixel electrode 5.

FIG. 8 shows the result of actually performing a circuit simulation and quantitatively estimating the amount of increase in the voltage applied to the liquid crystal layer 130. FIG. 9 is an enlarged view of a portion surrounded by a line V in FIG. In the case where the pixel electrode 5 overlaps the scanning line 11 so that the overlap width W becomes 3 μm and the length L of the amorphous silicon 120 is increased, the drain voltage amplitude input from the external driving device shown in FIG. liquid crystal layer 130 for peak-to-peak) △ VD
The ratio of the applied voltage △ VPI (へ VPI / △ VD) was calculated.

FIG. 8 shows that a voltage larger than the drain voltage amplitude can be applied to the liquid crystal when the overlap length L between the scanning line 11 and the amorphous silicon film 120 is increased by about 13 μm or more. Although there is no particular upper limit for the overlap length L, the width of the pixel electrode 5 is maximized. However, as shown in FIG. 8, when the overlap length L becomes about 30 μm or more, the amplification factor gradually approaches a saturated state. Therefore, it is considered that the preferable overlap length L is 30 to 90 μm. When this is converted into the overlap area, 90 to
270 μm ₂ . Usually, the width of the scanning line 11 is 10 μm
In consideration of the width of the pixel electrode 5 being about 100 μm, the allowable amount of misalignment during manufacturing, and the aperture ratio, the width of the amorphous silicon film 120 is preferably about 10 μm. The length may be selected so as to satisfy the overlap length L. Although the overlap width W may fluctuate slightly due to misalignment or the like, the overlap length L is increased to 50 μm.
By setting the length to be longer, the saturation state is approached, which is preferable in that the variation in the amplification effect is suppressed.

The effect of amplifying the applied voltage is simply expressed by T
Although it is thought that it can be obtained by increasing the size of the FT or installing a plurality of TFTs, increasing the area of the TFT generally decreases the aperture ratio or increases the leakage current during the holding time. There is a problem of deteriorating characteristics. Further, when the gate pulse is delayed, a current flows from the drain electrode to the pixel electrode until the TFT is turned off, so that the applied voltage amplification effect is reduced.

According to the active matrix type liquid crystal display device of the first embodiment, since the amorphous silicon film 120 as a semiconductor layer is provided so as to overlap the scanning line 11 and the pixel electrode 5 of the own stage, the manufacturing cost is reduced. Therefore, it is possible to provide a liquid crystal display device with low power consumption because it can be driven at a low voltage without increasing the power consumption. Further, in the active matrix type liquid crystal display device of the first embodiment, when the power consumption is set to be equal to the conventional one, it is possible to provide a liquid crystal display device of high display quality realizing high contrast and high speed response.

Therefore, according to the active matrix type liquid crystal display device of the first embodiment, a reduction in the aperture ratio which should be considered in the conventional active matrix type liquid crystal display device,
It is possible to provide an active matrix type liquid crystal display device which can be driven at a high contrast or at a low voltage without problems such as a holding characteristic when a TFT is turned off and a decrease in an effect when a gate pulse is delayed.

In the present embodiment, the liquid crystal display device of the type in which a vertical electric field is applied to the glass substrate has been described as an example. However, for example, as described in Japanese Patent Application Laid-Open No. 7-225388, A liquid crystal display device that applies a parallel electric field to a glass substrate can be applied to any liquid crystal display device using a TFT. Further, in the present embodiment, the case where Cr is used as the wiring material has been described, but the wiring material used in the present invention is Cr.
It does not need to be, and other wiring materials may be used. Also,
In the present embodiment, the case where an amorphous silicon film is used as the semiconductor film has been described. However, in the present invention, similar effects are expected, although the degree of difference is different, when the semiconductor film is replaced with another semiconductor film such as a polycrystalline silicon film. it can.

As a liquid crystal display device having a similar structure, there is a technique of forming an MIS capacitor between the scanning line 101 in the preceding stage and the pixel electrode 5 instead of the scanning line 11 of the device itself.
Although disclosed in Japanese Patent No. 292449, it only functions as a storage capacitor and does not have a function of increasing the voltage between the pixel electrode 5 and the counter electrode 123 as in the present invention.

(Second Embodiment) FIG. 10 is a plan view showing a unit pixel of a thin film transistor array substrate below a liquid crystal layer of an active matrix type liquid crystal display device of a second embodiment.

The difference between the active matrix liquid crystal display device of the second embodiment shown in FIG. 10 and the active matrix liquid crystal display device of the first embodiment shown in FIGS. 5, the scanning line 101 and the signal line 1
This is the point that was extended to the crossover portion of No. 3.

The electrical operation of the active matrix type liquid crystal display device of the second embodiment is the same as that of the active matrix type liquid crystal display device of the first embodiment, except that a crossover portion between the scanning line 11 and the signal line 13 is provided. Since the amorphous silicon film 120 is pinched, interlayer short-circuit between the scanning line 11 and the signal line 13 in the manufacturing process is reduced.
However, compared to the first embodiment, the capacitance coupled to the scanning line 11 increases, and the delay of the gate pulse applied to the scanning line is large.

The active matrix type liquid crystal display device of the second embodiment has the above-described structure, and in addition to the effects of the active matrix type liquid crystal display device of the first embodiment, the manufacturing yield is reduced due to the reduction in interlayer short-circuit. There is an advantage that an improved and inexpensive liquid crystal display device can be provided.

(Third Embodiment) FIG. 11 is a plan view showing a unit pixel of a thin film transistor array substrate below a liquid crystal layer of an active matrix liquid crystal display device of a third embodiment.

The difference between the active matrix type liquid crystal display device of the third embodiment shown in FIG. 11 and the active matrix type liquid crystal display device of the second embodiment shown in FIG. 10 is between the scanning line 11 and the pixel electrode 5. That is, the provided amorphous silicon films 120 are formed in a line on the scanning line 11.

In the active matrix type liquid crystal display device of the second embodiment, the pixel electrode 5 and the left and right signal lines 12 and 13 are used.
A relatively large difference in the coupling capacitance with the capacitor (the capacitance via the amorphous silicon film is generally larger)
However, in the active matrix type liquid crystal display device according to the third embodiment, the difference in coupling capacitance between the signal lines 12 and 13 is reduced, and vertical crosstalk can be reduced as compared with the second embodiment. However, the delay of the gate pulse applied to the scanning line 11 is larger than in the second embodiment.

The active matrix type liquid crystal display device of the third embodiment has the above-described configuration, and in addition to the effect of the active matrix type liquid crystal display device of the second embodiment, has a good display characteristic in which vertical crosstalk is inconspicuous. There is an advantage that provision of a liquid crystal display device can be realized.

(Fourth Embodiment) FIG. 12 is a plan view showing a unit pixel of a thin film transistor array substrate below a liquid crystal layer of an active matrix type liquid crystal display device of a fourth embodiment.

The difference between the active matrix type liquid crystal display device of the third embodiment shown in FIG. 12 and the active matrix type liquid crystal display device of the other embodiments is that the pixel electrode 5 and the preceding scanning line 101 are overlapped. This is the point where the former amorphous silicon film 120 is overlapped at a portion where the amorphous silicon film 120 is not formed.

In the active matrix type liquid crystal display device of the fourth embodiment, unlike the other embodiments, the pixel electrodes 5,
Even when vertical misalignment occurs when the amorphous silicon film 120 is formed, the change in the total capacitance coupled to the pixel electrode 5 is small. Therefore, the occurrence of display unevenness due to a change in pixel potential due to a change in pixel capacitance on the display surface is reduced.

The active matrix type liquid crystal display device of the fourth embodiment has the above-described structure, and in addition to the effects of the active matrix type liquid crystal display device of the first embodiment, a liquid crystal having good display characteristics with no noticeable display unevenness. There is an advantage that provision of a display device can be realized.

[0065]

As described above, the active matrix type liquid crystal display device of the present invention comprises a plurality of scanning lines formed on an insulating substrate and a plurality of signal lines formed so as to intersect the scanning lines. An active matrix liquid crystal display device including a thin film transistor formed near the intersection of the scanning line and the signal line, and a thin film transistor array substrate including an additional capacitor connected to a pixel electrode connected to a source electrode of the thin film transistor. Since a part of the additional capacitance portion is formed via an insulating film and a semiconductor between a scanning line connected to a gate electrode of a thin film transistor for switching the pixel electrode, a manufacturing process and materials are increased. Instead, a MIS capacitor is formed between the scanning line and the pixel electrode other than the TFT portion, and a negative voltage with respect to the common electrode potential is written to the pixel ( The voltage between the pixel electrode and the common electrode is made larger than that of the conventional active matrix type liquid crystal display device by making the feedthrough voltage in the case of writing (write) larger than the feedthrough voltage in the case of writing positively (positive writing). can do. Therefore, according to the present invention, the power consumption of the liquid crystal display device can be reduced by the effect of the above configuration, or when the power consumption is set to be equal to the conventional one, the improvement of the contrast and the high-speed response can be realized. .

[Brief description of the drawings]

FIG. 1 is a plan view showing a unit pixel of a thin film transistor array substrate provided in an active matrix type liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of one pixel of the active matrix liquid crystal display device according to the first embodiment of the present invention.

FIG. 4A is a schematic cross-sectional view for explaining the operation of a MIS capacitor. (B) is an equivalent circuit diagram of the MIS capacitance shown in (a).

FIG. 5A is an explanatory diagram showing a change in a MIS capacitance when a gate is turned on. (B) MI in the gate-off state
FIG. 4 is an explanatory diagram showing a change in S capacitance.

FIG. 6 is a characteristic diagram showing the gate voltage dependence of the MIS capacitance.

FIG. 7A is an explanatory diagram for explaining a difference in feedthrough at the time of positive writing to a pixel electrode. (B) is an explanatory view for explaining a difference in feedthrough at the time of negative writing to the pixel electrode.

FIG. 8 is a characteristic diagram illustrating an effect of the active matrix liquid crystal display device according to the first embodiment of the present invention.

FIG. 9 is an enlarged view of a portion surrounded by a line V in FIG. 1;

FIG. 10 is a plan view illustrating a unit pixel of a thin film transistor array substrate provided in an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 11 is a plan view illustrating a unit pixel of a thin film transistor array substrate provided in an active matrix liquid crystal display device according to a third embodiment of the present invention.

FIG. 12 is a plan view illustrating a unit pixel of a thin film transistor array substrate provided in an active matrix liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 13 is a plan view showing a unit pixel of a thin film transistor array substrate provided in a conventional active matrix type liquid crystal display device.

FIG. 14 is a sectional view of a conventional active matrix type liquid crystal display device.

FIG. 15 is an explanatory diagram of a gate-source parasitic capacitance Cgs of the TFT section.

FIG. 16 is an equivalent circuit diagram of one pixel of a conventional active matrix type liquid crystal display device.

FIG. 17 is a diagram showing a voltage waveform of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 1 gate electrode 3 drain electrode 4 source electrode 5 pixel electrode 11 own scanning line 12 own column signal line 13 adjacent signal line 18, 28 alignment film 100, 140 glass substrate (insulating substrate) 101 previous scanning line 115 gate Insulating film 119, 120 Amorphous silicon film (semiconductor) 119a, 120a n + type amorphous silicon film 121 Light shielding layer 122 Color layer 123 Counter electrode 130 Liquid crystal layer 250 Thin film transistor array substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1343

Claims (10)

(57) [Claims] A plurality of scanning lines formed on an insulating substrate; a plurality of signal lines formed so as to intersect the scanning lines; a thin film transistor formed near an intersection of the scanning lines and the signal lines; A pixel electrode connected to one electrode of the thin film transistor, a scanning line of a stage connected to a gate electrode of the thin film transistor for switching the pixel electrode, and the pixel electrode overlap with each other via an insulating film and a semiconductor film. The semiconductor film is formed in a region separated from a storage capacitor formed between the pixel electrode of the next stage and the scanning line of the own stage via an insulating film. An active matrix type liquid crystal display device characterized in that: 2. The semiconductor device according to claim 1, wherein the semiconductor film extends along the scanning line of the own stage and extends to a region partially overlapping an intersection of an adjacent signal line and the scanning line of the own stage. The active matrix type liquid crystal display device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein the semiconductor film is formed continuously along the scanning line of the own stage.
An active matrix type liquid crystal display device as described above. 4. The active matrix liquid crystal display device according to claim 1, wherein said additional capacitor portion and the storage capacitor is characterized in that it is separated in the width direction of the current stage of the scan line. 5. The active matrix liquid crystal display device according to claim 1, characterized in that the additional capacitance portion and said storage capacitor portions are separated in the longitudinal direction of the current stage of the scan line. Wherein said storage capacitor is an active matrix type liquid crystal display device according to claim 1, characterized in that it is arranged in the vicinity of the transistor. 7. The active matrix type liquid crystal display device according to claim 1, wherein said semiconductor film is formed of a semiconductor forming an active region of said transistor. 8. The active matrix liquid crystal display device according to claim 7, wherein said semiconductor film is one selected from an amorphous silicon film and a polycrystalline silicon film. 9. A plurality of scanning lines formed on an insulating substrate, a plurality of signal lines formed so as to intersect the scanning lines, a thin film transistor formed near an intersection of the scanning lines and the signal lines, A pixel electrode connected to one electrode of the thin film transistor, a scanning line of a stage connected to a gate electrode of the thin film transistor for switching the pixel electrode, and the pixel electrode overlap with each other via an insulating film and a semiconductor film. And the pixel electrode overlaps with a previous scanning line via an insulating film to form a storage capacitor portion, and a pixel of a next stage is formed on the scanning line of the own stage. The electrodes overlap with each other via an insulating film to form a storage capacitor portion for a next-stage pixel electrode, and the insulating film and the semiconductor film forming the additional capacitor portion include an insulating film and a semiconductor film forming the transistor. And the same structure as the semiconductor film,
An active matrix type liquid crystal display device, wherein the size of the additional capacitance portion is determined so that a voltage higher than a voltage applied from the outside can be applied to the liquid crystal layer. 10. The method of claim 9, wherein the length along the extending direction of the scanning lines of the additional capacitor portion is shorter than the length along the extending direction of the scanning lines of the storage capacitor Active matrix type liquid crystal display device.